SDA 6000/6001 "M2"
April/2002
PRODUCT INFORMATION
SDA 6000/6001 "M2"
16-bit Microcontroller and Graphics Engine
for TV and Display Appliances
The SDA 6000/6001 integrates a high-
speed 16-bit C166 microcontroller with digi-
tal signal processing for VBI data acquisi-
tion and the most flexible display controller
ever seen since Megatext.
The SDA 6000/6001 is the cost-effective
solution for consumer products that require
flexible pixel graphics for the optimum user
interface:
x
Television sets with
Teletext up to Level 2.5
Electronic Program Guides
(NexTView and others)
HTML-, GIF-, and
JPEG-based applications
x
Telecommunication devices with gray-
scale or color pixel displays
x
Display-oriented consumer info-devices
Main Features
x
True 16-bit microcontroller core (C166)
clocked at 33 MHz for excellent real-time
support
x
External memory interface supporting
SDRAM (16, 64, or 128 Mbit), ROM and
Flash up to 32 Mbit
x
PMQFP128 package with 0.8 mm pin
pitch for easy soldering
x
advanced CMOS technology for high-
performance and low power dissipation
(3.3/2.5 V)
x
New digital data slicer for high-quality
VBI line acquisition even with distorted
CVBS signals
x
RGB output
analog
digital (controlling of flat panel displays)
x
Flash card interfacing
x
Double vertical display resolution in
interlaced mode (SDA 6001)
Development and
Support Package
x
Data sheet / specification
x
Starter kit from www.willert.de
x
Reference layout and evaluation board
for easy and fast development start
x
Application notes and technical articles
x
A huge selection of tools that can facili-
tate various aspects of software devel-
opment with M2 can be found in the "ser-
vice" area at www.micronas.com.
Dedicated Tools
To increase productivity in Graphical User
Interface (GUI) development, a suite of
highly innovative software tools has been
created: the M2 Advanced Tools Environ-
ment (MATE) Toolbox
x
Multi-level graphics API:
flexibility through basic GDI functions,
efficiency through powerful OSD Service
Interface Commerce
x
M2 builder with comprehensive resource
editing, management and code genera-
tion facilities
x
M2 display simulator allowing to proto-
type SDA 6000/6001-based applica-
tions on a standard developer's PC
PRODUCT INFORMATION
SDA 6000/6001 "M2"
April/2002
All information and data contained in this product information are without any commitment, are not to be consid-
ered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or
development sample availability and delivery are exclusively subject to our respective order confirmation form. By
this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third
parties which may result from its use.
Micronas GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. +49-761-517-0
Fax +49-761-517-2174
E-mail: docservice@micronas.com
www.micronas.com
No part of this publication may be reproduced, photo-
copied, stored on a retrieval system, or transmitted
without the express written consent of Micronas GmbH.
Edition April 10, 2002; Order No. 6251-557-1PI
Functional Blocks
x
Powerful 16-bit microcontroller core
(compatible to C166 family) running at
33 MHz
x
2 kB IRAM and 2 kB XRAM for excellent
real-time support
x
Peripherals similar to SAB C161RI
(WDT, RTC, etc.)
x
36 I/O pins (up to 42, depending on
memory configuration)
x
External Memory Interface supporting
PC100-type SDRAM (16, 64, or
128 Mbit), EPROM and/or Flash with up
to three devices in parallel
x
New digital slicer with four different pro-
grammable data services per VBI field
x
2D graphic accelerator with DMA facility
and hardware support for fast character-
drawing
x
Fully flexible screen refresh unit support-
ing all display modes from 40
25 char-
acters at 50 Hz up to SVGA 800
600
pixels in 64 k colors at 75 Hz progressive
scan or higher resolution at reduced
frame repetition rates.
x
Triple 5/6/5-bit RGB DAC with pixel clock
up to 50 MHz for analog RGB output
x
Internal bus/arbitration and buffer sys-
tem with optimized priorities for maxi-
mum throughput and minimum latency of
memory access
Fig. 1: System overview of the SDA 6000/6001
Fig. 2: Block diagram of the SDA 6000/6001
C166 Microcontroller
33 MHz Clock Frequency
PEC, GPT1+2, ASC0, SSC, I2C,
BTL, WDT, RTC, GP-I/Os etc.
Acquisition Interface
2D Graphic
Accelerator with DMA
FIFO Buffer
3 RGB DAC
External Memory Interface
Arbiter 1
Arbiter 2
SDA 6000/6001
Screen Refresh Unit
ADC
Full Slicer
I/O
Analog
C
Bus System
16 Bit/
100 MHz Bus
Ext.
SDRAM
Non-Volatile
Memory
SDA 6000/6001
Additional
Memory
16 Mbit
or
64 Mbit
or
128 Mbit
EPROM
or
FLASH
EPROM
or
FLASH
Display
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