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Micronas

Contents

Page

Section

Title

UAC 355xB

DATA SHEET

Introduction

1.1.

Features

Hardware Description

2.1.

General Information

2.2.

Universal Serial Bus (USB)

2.2.1.

Transceiver

2.2.2.

USB Interface

2.2.3.

Microcontroller

2.3.

GPIO

2.3.1.

GPIO port configurations

2.4.

General Purpose Timer

2.5.

Audio Interface

2.5.1.

Audio Streaming Interface

2.5.2.

Audio Control Interface

2.5.3.

Serial Data Output

2.5.4.

Direct Streaming

2.5.5.

Microcontroller Streaming

2.6.

The UAC 355xB Serial Audio Interfaces

2.6.1.

Synchronous I

S Input/Output

2.6.2.

Asynchronous I

S input

2.6.3.

Asynchronous I

S input with optional I

S output

2.7.

Power Supply

2.8.

C Bus Interface

2.8.1.

C Master

2.8.2.

C Slave

2.9.

Microphone and Line Input

2.10.

Analog Output

2.10.1.

Digital-to-Analog Converters

2.10.2.

Analog Filter

2.10.3.

Analog Volume

2.10.4.

Line-out/Headphone Amplifier

2.10.5.

Subwoofer Output

2.11.

Special I/O

2.11.1.

SOF (Start of Frame)

2.11.2.

SEN (Suspend Enable)

2.11.3.

Suspend

2.11.4.

Reset

2.12.

Clock System

Contents, continued

Page

Section

Title

Micronas

April 15, 2003; 6251-544-1DS

DATA SHEET

UAC 355xB

Audio Processing

3.1.

DSP Loop

3.2.

Automatic Gain Control

3.3.

Quasi-Peak

3.4.

Bass Control

3.5.

Treble Control

3.6.

Parametric Equalizer

3.7.

Volume, Mute, and Balance Control

3.8.

Subwoofer Output and Bass Management

3.9.

Micronas Dynamic Bass (MDB)

3.9.1.

Dynamic Amplification

3.9.2.

Adding Harmonics

Firmware

4.1.

Features

4.2.

Device Descriptor

4.3.

Configuration Descriptor

4.3.1.

Audio Class Requests

4.4.

Vendor-Specific Requests

4.4.1.

Bootloader

Specifications

5.1.

Outline Dimensions

5.2.

Pin Connections and Short Descriptions

5.3.

Pin Descriptions

5.3.1.

Power Supply Pins

5.3.2.

Analog Audio Pins

5.3.3.

Interface Pins

5.3.4.

Other Pins

5.4.

Pin Configuration

5.5.

Pin Circuits

5.6.

Electrical Characteristics

5.6.1.

Absolute Maximum Ratings

5.6.2.

Recommended Operating Conditions

5.6.3.

Characteristics

5.6.4.

S Interface Timing Characteristics

UAC 355xB Applications

6.1.

Recommended Low-Pass Filters for Analog Outputs

6.2.

External Clocking via XTI

6.3.

Typical Applications

Data Sheet History

UAC 355xB

DATA SHEET

April 15, 2003; 6251-544-1DS

Micronas

Universal Serial Bus (USB) Codecs

1. Introduction

UAC 355xB is Micronas' new USB audio IC family. It
contains a high-performance stereo audio ADC/DAC,
digital serial interfaces, and an additional DAC channel
for the subwoofer signal.

The audio ADC with direct microphone and line input
makes the UAC 355xB the ideal solution for all kinds of
USB codec applications. This includes the replace-
ment of analog sound cards in PCs. Integrated head-
phone amplifiers allow direct headphone connection.
Therefore, the IC can be employed as a single-chip
headset solution without an extra power supply (bus-
powered).

Apart from the standard audio processing, such as vol-
ume, bass, and treble, the UAC 355xB offers a pro-
grammable 5-band parametric equalizer for correcting
the frequency response of the applied speaker. Adjust-
able dynamic low-frequency processing for the sub-
woofer channel leads to a reduced number of external
analog components. Internal sampling rate converters
offer high flexibility in handling all sampling rates for
USB upstream and downstream independently.

The codec function of the UAC 355xB is extended by
additional interfaces like I

S, allowing all kinds of digi-

tal audio processing systems to be connected to the
USB (e.g., Dolby Digital or MP3 decoding chips, such
as DPL 4519G, MAS 3528E, or MAS 35x9F).

General-purpose inputs and outputs connect the
UAC 355xB to peripheral hardware, such as buttons,
keyboards, LEDs, etc. Via I

C, more complex periph-

erals, such as LCD displays can be controlled; and the
UAC 355xB itself can be remote-controlled via I

C in

non-USB environments.

All in all, the IC is designed as the ideal connecting
matrix between USB, analog and digital audio input
and output, home stereo, compressed audio, and all
kinds of human interface devices. Many functions are
adjustable to the customer's needs. Moreover, com-
plete firmware-plug-in download functionality of the on-
chip microcontroller turns the UAC 355xB into a cus-
tomer-specific IC. Micronas supplies standard ROM
firmware based on the USB Composite Class, Audio
Class, and HID Class, one for general codec applica-
tions and one firmware for headset applications.

Apart from the basic versions UAC3554/3555B with
Micronas' standard firmware, there is an emulator ver-
sion UAC 3556B, which contains an 8 KB program
RAM in addition to the program ROM. This version can
be used for firmware development, prototyping or
small quantity production.

1.1. Features

� single-chip, USB specification 2.0 compliant, stereo

audio A/D and D/A converter

� supports 8/16-bit mono/stereo recording and up to

24-bit playback

� supports streaming of compressed audio

(Dolby Digital, MP3) to external decoder

� Vendor Identification and Device Configuration with

external EEPROM

� bus-powered and self-powered mode possible

� remote wake-up

� 12 general-purpose I/O pins with HID support

� I

S input/output interface

� independent adaptive sample rates of 6.4 to 48 kHz

for USB recording and playback (enhanced full
duplex)

� audio baseband control: bass, treble, loudness, vol-

ume, balance, and mute

� dynamic bass management (Micronas Dynamic

Bass (MDB)

� digital speaker equalizer

(5-band parametric equalizer)

� adjustable digital active crossover filter for sub-

woofer

� THD better than

90 dB and SNR of typically

96 dB for D/A converters

� THD better than

90 dB and SNR of typically

92 dB for A/D converters

� power supply rejection ratio >95 dB for analog

outputs

� integrated low-power stereo headphone amplifier

� subwoofer output

� I

C interface (master/slave)

� customized firmware extensions with plug-ins

possible

Table 1�1: Members of the UAC 355xB Family

Version

Description

UAC 3554B

USB headset

UAC 3555B

USB codec

UAC 3556B

USB codec � emulator version with
internal program RAM

UAC 355xB

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2. Hardware Description

Fig. 2�1: Detailed block diagram of the UAC 355xB

GPIO

Control

I/O

Mic Bias

USB

Audio Processing Unit (APU)

3-Channel DAC

Analog Volume

Headphone

Amplifier

Oscillator

Analog Filter

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7

D+

OUTL

OUTR

28
27
26
25
24
23
22
21

FOPR

FOUTR

FINR

FOUTL

FINL

FOPL

VREG

MICBIAS

XTI

XTO

Supply

VDD

VSS

AREG0

AREG1

AVSS0

SGND

SREF

AVSS1

FOPS

STRB
RD
ADR3/GPIO11

ADR2/GPIO10
ADR1/GPIO9
ADR0/GPIO8

12
17
17

18
19
20

TEST
TRDY
RES
SUSPEND

SOF

VBUS

SEN

44
31
45
46

DAO
DAI

CLI
MCLK

16
13
14
15
40

SCL
SCA

USBWSO

43
42

USBCLK

ADC

l
e

MICIN

ADCL

ADCR

USBDAT

WSI

Voltage Reg.

OUTS

and

PLL

2-Ch.

Reference

Volt.

Reg.

USB

Interface

Audio

Streaming

Interface

Audio Control

Interface

Compressed

Audio

Micro-

Controller

Output

Transceiver

AVDD

(Subwoofer)

/PWM

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UAC 355xB

Micronas

April 15, 2003; 6251-544-1DS

2.1. General Information

This description summarizes all hardware platform
capabilities of the UAC 355xB. The function of a cer-
tain application, however, is defined in the microcon-
troller's firmware. This is explained in Section 4. "Firm-
ware" on page 21 for the standard codec and headset
firmware.

The basic functions (playback, recording, audio con-
trol, HID) of the UAC 355xB can entirely be used by
any USB operating system without additional drivers.

However, the IC offers far more functionality if vendor-
specific controlling or download code is used. With
external I

C controlling, the IC can even work as an

audio codec in a non-USB environment. The use of
this complete functionality is not described in the stan-
dard data sheet and can be found in separate applica-
tion notes (www.micronas.com).

A detailed block diagram of the UAC 355xB is depicted
in Fig. 2�4. The functions of the blocks are explained
in the following sections.

2.2. Universal Serial Bus (USB)

2.2.1. Transceiver

The differential input transceiver is used to handle the
USB data signal according to the full-speed (12 MB/s)
USB driver characteristics (USB SPEC 2.0). This block
is supplied by an internal voltage regulator. The inter-
nal pull-up resistor on the D+ line, indicating that the
UAC 355xB is connected to the USB bus, can be
switched on and off by firmware.

2.2.2. USB Interface

The USB interface does all the low-level USB protocol
handling, such as NRZI coding, bit stuffing and CRC
computation. A receiver/transceiver logic handles the
data traffic between the USB bus and the microcontrol-
ler memory.

2.2.3. Microcontroller

The microcontroller is an 8-bit RISC controller which
handles the Chapter-9 processing and the decoding of
class and vendor-specific USB requests. Detailed
information is available in a separate document. The
basic configuration is:

� 2 KB RAM

� 12 KB ROM

In addition to that, the UAC 3556B has an 8 KB RAM,
which can be used instead of the lower 8 KB ROM for

emulation purposes or as a RAM extension to the
standard 2 KB RAM.

In the emulation mode, the UAC 3556B loads the 8 KB
RAM via I

C from an external EEPROM, disables the

lower 8 KB ROM after that, and restarts the microcon-
troller, executing the code from RAM.

Another part of the RAM is reserved for download
plug-ins. This is available in both UAC 3554B and
UAC 3556B, and allows the addition of smaller por-
tions of code to the basic firmware for extended func-
tions or workarounds, if necessary. One example is
adding extra functions to the GPIO pins, like control of
external components via USB. Downloading of the
plug-in can be done either from the USB host with an
extra driver or from an external I

C EEPROM.

2.3. GPIO

There are two groups of different types of GPIOs:

� Input and output pins: GPIO[0 ...11]

� Control pins: RD, STRB

UAC 355xB

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Fig. 2�2: UAC 355xB parallel interface timing (read)

Fig. 2�3: UAC 355xB parallel interface timing (write)

The port pins can also be set into different electrical
states:

� weak or strong driver strength

� output or tristate

� internal pull-down on or off

There are two GPIO pins with special alternate func-
tions (see Table 2�1)

� GPIO[10] - Start Timer

� GPIO[11] - PWM Output

A description of these functions can be found in Sec-
tion 2.4. "General Purpose Timer" on page 9.

2.3.1. GPIO port configurations

The UAC 355xB can set the GPIO port into different
configurations.

Standard mode

In this mode the GPIO[0...11] pins are used as normal
I/O pins, which can be set or read from the microcon-
troller.

GPIO[11:8]

GPIO[7:0]

Address

Data

STRB

UAC 355xB reads data here

(Address is driven by UAC 355xB)

(External device drives data lines)

GPIO Address Mode: Read

83 ns

166 ns

(typical)

GPIO[11:8]

GPIO[7:0]

Address

Data

STRB

UAC 355xB reads data here

(Address is driven by UAC 355xB)

(External device drives data lines)

GPIO Address Mode: Read

83 ns

166 ns

(typical)

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UAC 355xB

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Address mode

In this mode the GPIO pins can be used in a memory
mapped fashion. There is a 16-Byte range of the
microcontrollers address space which is transparent to
the GPIOs. GPIO[0...7] are mapped to the data bus
and GPIO[8...11] are mapped to the lower four bits of
the address bus.

2.4. General Purpose Timer

The UAC 355xB audio codec family incorporates a
timer. It is a 16-bit counter with clock prescaler. The
clock runs at 12 MHz. The prescaler can be set to
divide by 1 to 256.

The current value of the counter can always be read
back.

The timer initiates interrupts on reaching the count
value MaxA.

The UAC 355xB can start the timer with a "high" level
on GPIO[10].

The timer can be switched to PWM generation to con-
figure GPIO[11] as PWM output.

The structure of the timer is shown in Fig. 2�4. The
PWM output and timer frequencies can be calculated
as shown in Figure 2�5.

Table 2�1: GPIO port configurations

Pin name

Standard mode

Address mode

GPIO[0]

Generic I/O

Generic parallel I/O

GPIO[1]

Generic I/O

Generic parallel I/O

GPIO[2]

Generic I/O

Generic parallel I/O

GPIO[3]

Generic I/O

Generic parallel I/O

GPIO[4]

Generic I/O

Generic parallel I/O

GPIO[5]

Generic I/O

Generic parallel I/O

GPIO[6]

Generic I/O

Generic parallel I/O

GPIO[7]

Generic I/O

Generic parallel I/O

GPIO[8]

Generic I/O

Addr [0]

GPIO[9]

Generic I/O

Addr [1]

GPIO[10]

� Generic I/O

� Start timer

Addr [2]

GPIO[11]

� Generic I/O

� PWM out

Addr [3]

no function

Shows I/O direction
Read (high level) input
Write (low level) output - timing diagram

STRB

no function

Strobe pulse, marks valid data

UAC 355xB

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Fig. 2�4: Timer structure

Fig. 2�5: PWM timing

2.5. Audio Interface

2.5.1. Audio Streaming Interface

The audio streaming interface directly connects the
USB interface to the APU in order to transmit the digital
audio data in both directions for playback and record.
The following data formats are supported:

2.5.2. Audio Control Interface

The Audio Control Interface links the microcontroller to
the APU and is used to initialize the APU and to trans-
mit audio-related USB control data, such as volume
setting, tone control etc.

The Audio Control Interface supports full access to all
APU registers via the microcontroller.

2.5.3. Serial Data Output

Used Pins: USBCLK, USBDAT

This interface provides a data path for transferring
compressed audio to peripheral ICs, such as Micro-
nas' Dolby Digital decoder MAS 3528E or to an MP3
decoder, e.g., the MAS 3507D or MAS 3509F. This
works independently from the normal USB playback.
The audio format on the USB-OUT pins is burst I

Note: If this interface is used, the "Asynchronous I

input with optional I

S output" is not available

and vice versa.

This interface operates in different modes:

2.5.4. Direct Streaming

In this mode, there is no preprocessing of the timing,
i.e., the data on USBDAT are in phase with the 12 MHz
data on the USB bus, which are sent to a specific end-
point. This can be bulk or isochronous data. The data
appear as they are sent on the USB bus.

2.5.5. Microcontroller Streaming

In this mode, the microcontroller copies the data from
the RAM to a shift register, which is connected to the
USBDAT pin. The shift clock can be programmed
between 6 MHz and 750 kHz and appears on USB-
CLK pin.

Table 2�2: Audio Formats

Playback

Record

16-bit MONO

8-bit MONO

16-bit STEREO

16-bit MONO

24-bit STEREO

16-bit STEREO

Prescaler

12 MHz

Counter

Max A

Max B

Control

GPIO[10]

PWM

Timer Interrupt

GPIO[11]

EXT_ENB

Tclk

Tclk = 12 MHz / Prescale

Timer frequency:

PWM frequency:
PWM = Tclk / (MaxA + MaxB)

MaxA

MaxB

MaxA

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UAC 355xB

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2.6. The UAC 355xB Serial Audio Interfaces

Used Pins: DAO, DAI, WSI, CLI, USBDAT, USBCLK

The UAC 3556B offers two digital serial interfaces
(I2S). They are directly connected to the APU.
The I

S interfaces operate in 16-bit or 32-bit mode.

The master clock (MCLK) is programmable to
18.432 MHz, 24.576 MHz or 36.864 MHz. Delayed
word strobe or standard I

S format can be selected via

the programmable delay bit. Word strobe polarity is
programmable, too. Detailed timing diagrams can be
found in Section 5.6.4. "I

S Interface Timing Charac-

teristics" on page 46.

2.6.1. Synchronous I

S Input/Output

Used Pins: DAO, DAI, WSI, CLI

In this mode, the UAC 355xB is master on the I

S, i.e,

it generates WSI and CLI for a fixed 48 kHz sampling
rate. External I

S sources must deliver data synchro-

nous to the output.

Fig. 2�6: Synchronous I

S Input/Output

2.6.2. Asynchronous I

S input

Used Pins: DAI, WSI, CLI

In this mode the UAC 355xB is slave, i.e., asynchro-
nous input is possible at a sampling rate range from
6.4 kHz to 48 kHz. The external I

S source provides

DAI, WSI, and CLI

Fig. 2�7: Asynchronous I

S input

2.6.3. Asynchronous I

S input with optional I

output

Used Pins:
Output:USBDAT, USBCLK, USBWSO
Input: WSI, CLI, DAI

In this mode the I

S burst interface pins USBDAT,

USBCLK and USBWSO can be used for synchronous
I

S output (if the burst interface is not used), as

described in Figure 2.6.1. The I

S input pins WSI, CLI,

DAI, however, operate asynchronously as described in
Figure 2.6.2.

Fig. 2�8: Asynchronous I

S input with optional

S output

DAI

CLI

WSI

DAO

MCLK (optional)

UAC

55xB

synchronous
input/output

DAI

CLI

WSI

asynchronous
input

355

USBDAT

USBCLK

USBWSO

DAI

CLI

WSI

synchronous
output

UAC

55x

asynchro-
nous

input

UAC 355xB

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2.7. Power Supply

The UAC3554/6B has on-chip voltage regulators pro-
viding the optimal supply voltages for the analog and
digital sections, thus allowing to power the IC by the
USB Bus supply lines, as well as from external supply.
They also serve to reduce cross-talk and EMI.

For stable operation, all regulators need external
capacitors.

The regulators are:

1. VREG:

3.4 V regulator for USB-signalling (saving external
regulator)

2. AREG0:

3.5 V regulator for analog back-end

3. AREG1:

3.5 V regulator for analog circuitry apart from back-
end.

Reference voltage for analog signals:

SREF:
1.7 V (optional 2.3 V) reference voltage for analog cir-
cuitry.

Note: It is recommended for AVSS0/1, SGND and

VSS to be connected. In certain applications,
however, it may be better to split signal ground
from the other grounds in order to reduce noise.

Five-Volt Mode

If a higher output level is required, the IC can operate
in 5 V mode. In this case, the IC is powered from an
external 5 V supply: AVDD has to be connected to
AREG0 and AREG1 and SREF must be switched to
5 V mode.

2.8. I

C Bus Interface

Pins: SDA, SCL

The UAC 355xB is equipped with an I

C bus master/

slave interface. Bus format and timing follow the origi-
nal specification for I

C (The I

C Specification V2.1).

It operates with 5 V signalling at 100 kHz or 400 kHz.
Both master and slave mode require support from the
microcontroller firmware.

2.8.1. I

C Master

This mode allows control of external I

C devices, such

as EEPROMs, LCD-Displays etc. This interface is
used to download configuration data and firmware
from an EEPROM after power-up. The bus protocol
(subaddressing and packet length) is defined by firm-
ware and therefore programmable.

Note: Micronas standard firmware (Section 4. "Firm-

ware" on page 21) provides support for USB to
I

C bridging, allowing control of I

C devices via

USB.

2.8.2. I

C Slave

In I

C slave mode, the interface provides an interrupt

to the microcontroller after detecting the assigned I

address (0x48). The corresponding interrupt service
routine handles this request and interprets incoming
data according to the application.
One example of handling could provide full access to
all memory locations.

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UAC 355xB

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2.9. Microphone and Line Input

Pins: ADCR, ADCL, MICIN, MICBIAS

The UAC 355xB provides a 2-channel ADC. The A/D
converters achieve a signal-to-noise ratio better than
90 dB (typ.) and a bandwidth of 20 kHz (at f

=48 kHz).

The left channel can be used as microphone or line
input, whereas the right channel is always line input.
Programmable input gain allows adaption of the input
levels to the ADC range.

The UAC 355xB allows direct connection to an electret
microphone and provides the microphone bias voltage
of 3.1 V (0.5 mA max.) on a separate pin, too. The
microphone bias is automatically switched on when
the microphone input is selected. The output resis-
tance of the MICBIAS pin is typically 180

There is a fixed +21.5 dB gain followed by a program-
mable gain of 0 dB to +22.5 dB. Table 2�3 shows the
microphone voltage versus gain setting and the input
impedance (depends on gain setting) for full range
ADC input (clipping level).

Table 2�3: Microphone input levels

Microphone
Voltage
[mV

]

3 V Mode

Microphone
Voltage
[mV

]

5 V Mode

Gain
Setting [dB]

Input
Impedance
[k

]

283

377

137

238

317

1.5

117

200

267

100

168

225

4.5

142

189

119

159

7.5

100

134

113

10.5

13.5

16.5

19.5

22.5

UAC 355xB

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The input gain for the line input is programmable in the
range of

3 dB to 19.5 dB. Table 2�4 shows the line

input voltage versus gain setting and the input imped-
ance (depends on gain setting) for full range ADC
input (clipping level).

After A/D conversion there is a digital quasi-peak
meter providing level information in APU register.
If Mic input is selected, there is the option to switch the
signal to both channels. In this case, the left channel is
copied to the right channel after the peak meter.

Fig. 2�9: Analog input configuration

Table 2�4: Line input levels

Line Input
Voltage
[mVpp]
3 V Mode

Line Input
Voltage
[mVpp]
5 V Mode

Gain
Setting [dB]

Input
Impedance
[k

]

3388

4517

2851

3801

1.5

2399

3198

2018

2691

1.5

1698

2264

1429

1905

4.5

1202

1603

1011

1349

7.5

851

1135

716

955

10.5

602

803

507

676

13.5

427

569

359

478

16.5

302

403

254

339

19.5

Q-Peak

Line

Mic

Mono

Mic-Bias

Preamp

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UAC 355xB

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2.10. Analog Output

Pins: OUTL, OUTR, OUTS
FOPL, FOPR, FOUTL, FOUTR, FINL, FINR, FOPS

The analog output system comprises the stereo audio
DAC, the subwoofer DAC, analog filters, op-amps for
external out-of-band-noise filters, analog volume,
mute, and the output amplifiers.

2.10.1. Digital-to-Analog Converters

The UAC 355xB uses three multibit sigma delta DACs
with high linearity and SNR better than 95 dBA.

2.10.2. Analog Filter

Pins: FOPL, FOPR, FOUTL, FOUTR, FINL, FINR,
FOPS

This block contains the op-amps for the optional ana-
log external out-of-band-noise filters. It is recom-
mended to use a second-order filter for the main chan-
nels (OUTL, OUTR) (see Section 6. "UAC 355xB
Applications" on page 48). It is possible to omit these
filters and to save the external components. In this
case, the op-amp has to be switched off and the pins
FOOTL/R, FINL/R and FOPL/R must be connected.
The output signal will contain more out-of-band noise,
which is not audible, however.

A first-order filter is required for the subwoofer output
in order to attenuate the out-of-band noise caused by
the sigma delta DACs.

2.10.3. Analog Volume

The analog volume covers a range from +6 dB to

18 dB with 1.5 dB step size. But this is the analog

component of the overall volume system which covers
a range from +12 dB to

114 dB with 1 dB step size

and additional mute position. It is split into analog and
digital volume. This splitting ensures that the DAC per-
formance parameters do not degrade at reduced vol-
ume settings. The splitting is embedded in the audio
processing and cannot be modified.

Note: Positive volumes will degrade the THD at high

input levels.

2.10.4. Line-out/Headphone Amplifier

Pins: OUTL, OUTR

Stereo Mode

The line-out/headphone amplifier output is provided at
the OUTL and OUTR pins connected either to stereo
headphones or to a power amplifier. The stereo head-
phones require external serial resistors in both chan-
nels. See Section 6. "UAC 355xB Applications" on
page 48.

Fig. 2�10: Loudspeaker connection for Stereo mode

Mono Mode

In Mono mode, the DC coupling capacitors and further
filter circuitry are not required. In this mode, the output
pins OUTL/R operate in bridge mode with complemen-
tary signals. Therefore, the maximum output power
increases, allowing small speakers to be driven
directly.

Fig. 2�11: Loudspeaker connection for Mono mode

2.10.5. Subwoofer Output

Pins: OUTS

The subwoofer output is designed for driving an exter-
nal amplifier. The audio processing provides a pro-
grammable split filter and active bass management
algorithms.

Note: If the capacitive load is too high, a serial resistor

is required.

OUTL

AVSS

OUTR

AVSS

OUTR

OUTL

UAC 355xB

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Micronas

2.11.Special I/O

Pins: SOF, SEN, SUSPEND, RESET

The following sections describe some pins with special
functions.

2.11.1. SOF (Start of Frame)

The SOF pin provides a 1 ms periodic signal which is
derived from the USB frame rate. It can be used for
test purpose or as an USB-synchronous reference for
vendor-specific external circuitry.

2.11.2. SEN (Suspend Enable)

Pin: SEN

This is a digital input that prevents the device from
entering the low-power mode (Suspend). The
UAC 355xB enters a low-power mode if:

� there is J-state on D+, D

lines (USB-Suspend) and

V bus high

� V bus is low (USB disconnected)

Note: Both cases must be supported by the firmware

In case of USB-Suspend, the SEN pin is also used as
an input for the remote wake-up function.

Table 2�5: SEN pin

2.11.3. Suspend

Pin: SUSPEND

The SUSPEND pin is a digital output pin which indi-
cates the low-power mode. It can be used to power
down external circuitry, such as power amplifiers in a
USB speaker.

2.11.4. Reset

Pin: RES

The RES pin resets the UAC 355xB. During power-up
the RES pin should be low until the clock system is up
and running. Then this pin can be released and the
UAC 355xB enters normal operating mode.

Note: In low-power mode, the RES pin must not be

low to avoid restart of the clock system and
therefore entering normal power mode.

Fig. 2�12: Timing diagram of the reset procedure

2.12. Clock System

Pins: XTI, XTO

The UAC 355xB requires a 12 MHz clock source,
which is realized as an on-chip oscillator with external
crystal. Also an external oscillator can be used. In this
case, the clock has to be connected to XTI (see also
Section 6. "UAC 355xB Applications" on page 48). The
12 MHz is the input clock for a PLL circuit which gener-
ates all clocks needed within the IC.

The clock for the APU is programmable either to
48 MHz or 72 MHz. In case of 48 kHz, the UAC 355xB
consumes less power, but on the other hand a
reduced feature-set for the audio processing has to be
taken into account (see Fig. 3�1 on page 17).

SEN

high

suspend enabled

low

suspend disabled/remote wake-up

Table 2�6: SUSPEND pin

SUSPEND

high

normal power

low

low power

20 ms

90%

AVDD

RES

VDD

C
3

i
c

r
o

r
i
l

1

,

2

;

6

-
5

-
1

3. Audio Processing

Fig. 3�1: Signal flow in the audio processing unit (APU)

Q-Peak

Line

Mic

Mono

i
s

f
/
50

�s/7

�

ADC

mix

USB

mix

USB

AGC

Bass/

Treble/

Comple-
mentary
High

Low

MDB

Loud-

ness

Vol.

l
anc

Level

Adjust

Q-Peak

Scale

S out

l
e

Scale

complete mix

S input

ADC+USBmix

USB L/R

ADC input

complete mix

ADC+USBmix

ADC input

USB L/R

S input

(downstream)

USB

(upstream)

Pass

Mic-Bias

Preamp

Sub-
woofer

Mono/

Stereo

Right

Invert

dashed blocks not available in reduced feature set

DSP-Loop

Vol.

S Synchronous Mode only

in reduced feature set

UAC 355xB

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Micronas

The audio processing is realized by APU firmware. The
audio building blocks can be split into USB-indepen-
dent features such as parametric equalizer, I

S I/O,

and blocks which belong to USB feature units, mixer
units, and selection units defined in the USB Device
Class Definition for Audio Devices.

The USB feature unit provides basic manipulation of
the incoming logical channels and can be controlled by
the standard windows mixer tool. The parameters for
the USB-independent features are predefined in the
internal ROM, in an external EEPROM or a special
host application which drives the IC.

The UAC 355xB supports two logical channels (i.e. left
and right) and a subwoofer channel which is derived
with a split filter from left and right. Multichannel or sur-
round systems, however, can also be realized using
more than one UAC 355xB, because phase or delay
distortion is eliminated in the device by locking the
audio processing to the USB frame rate. An overview
of the architecture is given in Fig. 3�1 on page 17.

If the APU works with a 48 MHz clock it is necessary to
select the reduced feature mode. The blocks, which
are not available in reduced feature mode are shown
with dashed lines in Fig. 3�1 on page 17.

3.1. DSP Loop

The DSP-Loop block symbolizes the option to route
the audio signal to an external DSP and back into the
UAC 355xB via I�S I/O. This allows to add more audio
processing algorithms.

3.2. Automatic Gain Control

The Automatic Gain Control (AGC) is one of the build-
ing blocks of the feature unit (USB Device Class Defi-
nition for Audio Devices 1.0, page 39).

Different sound sources fairly often do not have the
same volume level. The Automatic Gain Control solves
this problem by equalizing the volume levels within a
defined range. Below a threshold level the signals are
not affected. The level-adjustment is performed with
time constants in order to avoid short-time adjustments
due to signal peaks.

Fig. 3�2: Simplified AGC characteristics

3.3. Quasi-Peak

Two quasi-peak detectors are provided:

1. after the ADCs. This allows the programming of an

AGC in the microcontroller

or a VU-meter on the

host side.

2. in the DAC channel. This can be used, e.g., for a

VU-meter on the host side.

The feature is based on using fast attack and slow
decay time constants.

3.4. Bass Control

The bass control provides gain or attenuation to fre-
quency components below a corner frequency of
120 Hz. The bass control works identically on both
channels in a range of

12 dB to +12 dB.

3.5. Treble Control

The treble control provides gain or attenuation to fre-
quency components above a corner frequency of
6 kHz. The treble control works identically on both
channels in a range of

12 dB to +12 dB.

not supported by standard microcontroller firmware

Table 3�1: AGC parameters

Parameter

Settings

Default

Decay time

8 seconds
4 seconds
2 seconds
20 ms

4 seconds

Input Level

Output Level

dBr

AGC off

AGC on

DATA SHEET

UAC 355xB

Micronas

April 15, 2003; 6251-544-1DS

3.6. Parametric Equalizer

The parametric equalizer is an audio feature which is
not accessed via standard USB controls. It allows the
compensation of the frequency response of a speaker.
Alternatively, frequency responses can be set to suit
individual tastes. The equalizer consists of 5 individu-
ally adjustable bands. The control parameters and the
parameter range for each band is shown in Table 3�2.

The adjustment of the equalizer is supported by an
application program that allows to set up frequency
responses and to download the corresponding filter
coefficients into the UAC 355xB. When the frequency
response matches the requirements, it can be pro-
grammed into the external EEPROM or can be set by
a vendor specific device driver. The UAC 355xB is
shipped with a flat frequency response.

3.7. Volume, Mute, and Balance Control

The volume control is partly realized in the analog
back-end. This preserves high audio quality (SNR) at
low volume settings because signal and noise are
attenuated in the same way. This is not the case for
devices with pure digital volume control. The
UAC 355xB uses digital volume control only for the
fine tuning. The volume setting is smoothed by an
internal ramping algorithm in order to avoid audible
clicks during volume change. The splitting between
analog and digital volume is handled by the
UAC 355xB automatically.

The balance is implemented digitally by attenuating
one channel.

The mute control is part of the volume system in the
UAC 355xB. It functions simultaneously on both chan-
nels and can be switched on and off under USB con-
trol. Similar to the volume control, clicks are avoided
by a ramping algorithm.

3.8. Subwoofer Output and Bass Management

The subwoofer signal is created by combining the left
and the right channels directly behind the equalizer
block using the formula (L+R)/2. Due to division by 2,

the D/A converter will not be overloaded, even with
full-scale input signals. The subwoofer is filtered by a
third-order low-pass filter with programmable corner
frequency and programmable characteristic followed
by a level adjustment. At the main channels a comple-
mentary high-pass filter can be switched on. Sub-
woofer and main output use the same volume.

Please note, that the predefined subwoofer parame-
ters in the internal ROM are set in such a way, that the
low frequencies of both channels are summed up and
are distributed equally to left and right channel. This
reduces the risk of overload of the speakers, but
degrades the channel separation for low frequencies.
Since the human perception cannot extract information
about direction from low frequencies, this is no draw-
back.

Fig. 3�3: Subwoofer characteristics (e.g. f

= 200 Hz)

Table 3�2: Equalizer parameters

Parameter

Min

Max

Center Frequency

50 Hz

15 kHz

Gain/Attenuation

6 dB

+6 dB

Filter Quality (Q)

0.5

Table 3�3: Subwoofer parameters

Parameter

Settings/
Range

Default

Corner Frequ.

50 to 400 Hz

90 Hz

Characteristic

� sharp edge

� medium edge

� soft edge

� very soft edge

sharp edge

200.

2000

-5

medium

sharp

soft

very soft

UAC 355xB

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Micronas

3.9. Micronas Dynamic Bass (MDB)

The Micronas Dynamic Bass algorithm (MDB) imple-
ments a sophisticated bass boost system, which
extends the frequency range of loudspeakers or head-
phones.

The MDB is placed in the subwoofer path. For applica-
tions without a subwoofer, the enhanced bass signal
can be added back onto the left/right channels.
Micronas Dynamic Bass combines two effects:
dynamic amplification and adding harmonics.

Several parameters allow tuning the characteristics of
MDB according to the loudspeaker, the cabinet, and
personal preferences. For more detailed information
on how to set up MDB, Micronas will provide an appro-
priate Application Note.

3.9.1. Dynamic Amplification

Since the human impression of loudness depends on
the frequency, a dynamic compression of the low fre-
quencies adapts the sound to the human perception.

In order to prevent clipping and to adapt the system to
the signal amplitude which is really present at the out-
put of the device, the MDB contains a definable limit.
The output signal amplitude is monitored and if it
comes close to the limit, the gain is reduced automati-
cally. Clipping effects are avoided.

Fig. 3�4: Dynamic amplification

3.9.2. Adding Harmonics

MDB exploits the psychoacoustic phenomenon of the
`missing fundamental'. Adding harmonics of the fre-
quency components below the cutoff frequency gives
the impression of actually hearing the low frequency
fundamental. In other words: Although the loud-
speaker system is not capable of generating such low
frequencies, the listener has the impression that it
reproduces them.

Fig. 3�5: Adding harmonics

Complemen-
tary High-Pass
Filter for L/R
channel

� L/R unfiltered

� L/R high-pass-

filtered

� Subw. added

to high-pass-
filtered L/R

Subw. added
to high-pass-
filtered L/R

Level Adjust-
ment

60...+12 dB

(relative to main
volume)

0 dB

Subw. DAC

� off

� on

Table 3�4: MDB parameters

Parameter

Range

Default if
disabled

Default if
enabled

Effect
Strength

off ...max

off

medium

Harmonic
Content

0 ...100%

50%

Center
Frequency

20 ...300 Hz

90 Hz

Amplitude
Limit

32...0

dBFS

0 dBFS
(=no limit)

Subwoofer
Settings

two sets for MDB off/on available, for
parameters see Table 3�3

Table 3�3: Subwoofer parameters, continued

Parameter

Settings/
Range

Default

Frequency

MDB_LIMIT

MDB_CF

i
gna

l
Level

litu

SUBW_FREQ

(db)

Frequency

MDB_CF

i
t
ude

(db)

UAC

TA
SH

EE
T

ril 15,

2003;

51-544-1DS

i
c

r
o

nas

4. Firmware

Fig. 4�1: Signal flow in the audio processing unit controlled by the codec/headset firmware using standard OS driver

Q-Peak

Line

Mic

Mono

pha

f
f/50

�

�s

ADC

mix

USB

mix

USB

AGC

Bass/

Treble/

Comple-
mentary
High

Low

MDB

Loud-

ness

Level

Adjust

Q-Peak

Scale

S out

Scale

complete mix

S input

ADC+USBmix

USB L/R

ADC input

complete mix

ADC+USBmix

ADC input

USB L/R

S input

(downstream)

USB

(upstream)

Pass

Mic-Bias

Preamp

Sub-
woofer

Mono/

Stereo

Right

Invert

switch to Line-L only for Codec Firmware

ADC-mix only for headset firmware

Vol.

UAC 355xB

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The previous chapters describe the UAC 355xB from
the hardware point of view. The complete functionality,
however, is defined by the microcontroller firmware.
This firmware tailors the device to a specific applica-
tion.

Micronas offers two standard firmware versions
embedded in the ROM.

� UAC 3555B: Standard Codec

� UAC 3554B: Standard Headset

Note: It is possible to customize many parameters

(IDs, strings, equalizer setting etc.) by means of
an external EEPROM.

Both firmware versions are very similar. Differences
are mentioned in the following chapters.

4.1. Features

The main features of the standard firmware versions
are:

� USB playback and record with independent sample

rates

� Sample rates from 6.4 kHz to 48 kHz

� Microphone or Line input

(only mic for UAC 3554B)

� Audio baseband processing incl. dynamic bass

management and subwoofer split filter

� Basic audio control by GPIO-HID

� Suspend mode and remote wake-up support

� I

C master/slave support

� Bootloader permitting download of configuration

data, plug-ins or complete firmware (only for
UAC 3556B) after power-on

� Plug-in support (downloadable firmware extensions

from external EEPROM or WIN driver).

Most of the functions are defined in the device and
configuration descriptor. The following chapters pro-
vide all noteworthy information, which is buried in this
descriptors. It is assumed that the reader is familiar
with the basic USB notation (USB Spec 2.01/
www.usb.org).

4.2. Device Descriptor

The device descriptor contains the downloadable IDs
and the index for several strings.

Associated to the string index there are three program-
mable strings. The ROM firmware defines only two:

4.3. Configuration Descriptor
The configuration descriptor contains information on
the bus/self-powered and remote wake-up capabilities.
The UAC 355xB allows all combinations of these fea-
tures. There is also a string index, allowing to associ-
ate a string to this configuration. The default string is a
date code (time of code assembly). These items are
programmable:

The configuration descriptor also provides all informa-
tion concerning the audio flow in the Class Specific
Audio Control Interface. Fig. 3�1 on page 17 shows
the graphical representation for the codec firmware.

Table 4�1: Programmable Device Descriptor Items

Item

Default
UAC 3555B

Default
UAC 3554B

idVendor

0x074D

idProduct

0x3554

bcdDevice

0x000x

iManufacturer

0x01

iProduct

0x02

iSerialNumber 0x00

0x00

) Changes with firmware revisions

Table 4�2: Strings

String

Default
UAC 3555B

Default
UAC 3554B

Manufacturer
String

Micronas

Product String

UAC 3555B

UAC 3554B

Table 4�3: Programmable Configuration Descriptor
Items

Item

Default -
UAC 3555B

Default -
UAC 3554B

iConfig

0x01

bmAttributes

0xe0
(self-powered,
remote wake-up)

0xa0
(bus-powered,
remote wake-up)

MaxPower

0x00 (0 mA)

0x32 (100 mA)

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Micronas

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Fig. 4�2: Standard headset audio signal flow

Fig. 4�3: Standard codec audio signal flow

These are the audio structures and how they appear to
the USB host. Without any additional drivers the
Microsoft Windows operating system provides sliders
in the mixing tool to control volume setting, selectors
etc. Using a vendor specific application, however, it is
possible to extend this to the full signal routing capabil-
ities (see Section 3.1. on page 18).

Static modifications (without sliders), like

� adding a sidetone path (analog-in to analog-out) to

the codec firmware

� adding I

S I/O

can be achieved by plug-ins from external EEPROM or
Windows device driver.

The switching units SU7 and SU8 in the headset firm-
ware are dummy units and allow the operating system
to parse the descriptor correctly.

The mapping of this audio structure to the overall
audio processing in the APU is shown in Fig. 4�1 on
page 21. The dashed lines show signal paths which
cannot be activated by standard Windows drivers and
need support of vendor-specific drivers and applica-
tions (driver available from Micronas), especially for
I

S input/output.

Note: BassBoost enables a dynamic bass manage-

ment algorithm with programmable (external
EEPROM) characteristics.

Mic

ID11

Mic

ID10

ID8

Volume

Volume, mute

ID2

ID6

EP1

USB

ID12

ID9

Volume,Mute,
Bass,Treble
BassBoost
AGC

ID1

ID14

D/A

Playback

ID7

USB-Up

ID13

Record

analog

analog gain

analog+digital

Associated
Input
Terminals

"dummy selector units"

EP4

Sidetone Mixer

Line

ID10

Mic

ID11

Volume

ID3

ID2

EP1

USB

ID12

Volume,Mute,
Bass,Treble
BassBoost
AGC

ID1

ID14

D/A

Playback

ID8

Volume Mute ID5

USB-Up

ID13

Record

analog gain

EP4

UAC 355xB

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The next part of the configuration descriptor defines
the audio format for playback and record. This is not
programmable.

The UAC 355xB accepts all sample rates from 6.4 kHz
to 48 kHz independently for playback and record.

The final portion of the configuration descriptor defines
the HID functions:

The codec firmware uses the GPIO pins to connect
keys which are related to the USB HID class. The
standard configuration defines the GPIO0 to GPIO3 as
input pins for the audio control shown in Table 4�5.

Codec Firmware

GPIO[4..11] pins are not assigned to HID functions and
can be used by a vendor specific driver or plug-in.
Each pin can be configured as input or output pin with
programmable pull down resistor and weak or strong
driver strength.

GPIO[4...7] are used as media control keys:

With the use of this pins, the Windows Media Player
can be controlled directly.

The keys are polled every 1 ms by the microcontroller
and the corresponding key codes are transmitted to
the host on request when a key enters "high" state.
The hosts polling rate is 8 ms. This parameter, how-
ever, is part of the configuration set, which can be
downloaded from an external I

C EEPROM.

Headset Firmware

In addition to the basic audio control there is a local
mic-mute, controlled by GPIO[4]. A button connected
to VDD allows to toggle between mic mute and
unmute. For indication of the mute status an LED can
be connected to GPIO[11]. This LED will stay solid if
mic is NOT muted and will blink in 500ms rate if the
mic is muted. Sidetone level is also muted with this
function. However, the mute state is NOT reported to
WIN OS and therefore the mute indicator in the WIN
mixer will not change by this local mic mute. The WIN
mixer can overwrite the local sidetone mute, i.e.,
switch sidetone on again, even if the recording path is
still muted.
GPIO[5...10] are not used in the headset.

4.3.1. Audio Class Requests

The codec firmware supports all audio class requests
which are required by the audio flow shown in Fig. 4�2
and Fig. 4�3. The MIN/MAX/RES setting follow the
limits which are defined in the audio processing apart
from the main volume setting (FU1). In this case the
overall range from

114 dB to +6 dB is limited to

40 dB to +3 dB (plus mute position) in order to fit the

audible range to the volume slider in the WIN mixer.

Table 4�4: Supported audio formats

Playback

Record

16-bit Mono

8-bit Mono

16-bit Stereo

16-bit Mono

24-bit Stereo

16-bit Stereo

Table 4�5: Standard key configuration

Pin

Function

GPIO0

Volume Up

GPIO1

Volume Down

GPIO2

Mute on-off toggle

GPIO3

BassBoost on-off toggle

Table 4�6: Media control keys

Pin

Function

GPIO4

Next Track

GPIO5

Previous Track

GPIO6

Stop

GPIO7

Play/Pause

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Micronas

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4.4. Vendor-Specific Requests

These requests provide functions which extend stan-
dard controlling of the operating system. Micronas pro-
vides a driver for Windows-operating systems which
supports:

� SET MEM

This request allows writing all RAM and Register
locations on the chip.

� GET MEM

This request allows reading all memory locations on
the chip. Block read is supported.

� SET I

This vendor request allows driving the I

C-master in

the codec firmware. It allows writing to external I

devices.

� GET I

This request supports I

C master reading from

external devices.

4.4.1. Bootloader

The bootloader is a part of the firmware which allows
communication with an external I

C EEPROM. The

bootloader runs immediately after power-on. At this
time the device is not connected to the USB bus.
When the bootloader is finished, the pull-up resistor is
switched on the D+ line. If no external EEPROM,
according to the configuration shown in Table 4�8 is
found, the UAC 355xB continues with the internal
ROM code. After download of a complete firmware
(UAC 3556B only), the bootloader resets the device
and the code that was just downloaded is executed.

The UAC 355xB can have different EEPROMS con-
nected to the I

C bus. The UAC 355xB works as an

C bus master at this point in time. Depending on

EEPROM size, the EEPROM can hold different con-
tent.

Various I

C EEPROM configurations can be used by

means of bootstrap options at the pins USBDAT, USB-
CLK, and USBWSO:

Note: UAC 3554B and UAC 3555B cannot load exter-

nal firmware.

Table 4�7: Supported I

C EEPROM types

EEPROM size

Purpose

2 kbit

Configuration only

4...32 kbit

Configuration
Plug-in software

64 kbit

Configuration
On reset loadable firmware

128 kbit

Configuration
On reset loadable firmware
Plug-in software

UAC 355xB

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Table 4�8: I

C-Mode of external EEPROM

USBWSO

USBDAT

USBCLK

Address
Subaddress

Purpose

don't care

internal ROM only
I

C master disabled

don't care

0x50
1 byte subaddressing
(UAC 3554B and
UAC 3555B only )

Configuration data
Plug-in software
100 kHz I

C master

0x51
2 byte subaddressing

Configuration data
On reset loadable firmware
Plug-in software
400 kHz I

0x52
2 byte subaddressing

Configuration data
On reset loadable firmware
Plug-in software
400 kHz I

0x51
2 byte subaddressing

Configuration data
On reset loadable firmware
Plug-in software
100 kHz I

0x52
2 byte subaddressing

Configuration data
On reset loadable firmware
Plug-in software
100 kHz I

DATA SHEET

UAC 355xB

Micronas

April 15, 2003; 6251-544-1DS

5.2. Pin Connections and Short Descriptions

NC = not connected, leave vacant
LV

= if not used, leave vacant

VSS = if not used, connect to VSS
OBL = obligatory; connect as described in

circuit diagram

VDD = connect to VDD

Pin
No.

Pin Name

Type

Connection

(If not used)

Short Description

Not Connected

XTI

OBL

Quartz Oscillator Pin 1

XTO

OUT

OBL

Quartz Oscillator Pin 2

AREG1

OUT/IN

OBL

Regulator Output for analog parts except ampli-
fiers (supply voltage input for 5 V mode)

AVSS1

OBL

VSS 1 for analog parts except amplifiers

AVSS0

OBL

VSS 0 for audio output amplifiers

OUTL

OUT

Audio Output: headphone / speaker Left

OUTR

OUT

Audio Output: headphone / speaker Right

AREG0

OUT

OBL

Regulator Output for audio output amplifiers
(supply voltage input for 5 V mode)

AVDD

OBL

analog VDD

OUT

GPIO Read

STRB

OUT

GPIO Strobe

DAI

VSS

S Data Input

WSI

IN/OUT

S Word Strobe

CLI

IN/OUT

S Bit Clock

DAO

OUT

S Data Output

ADR3/GPIO 11/
PWM

IN/OUT

HID IO 11

ADR2/GPIO 10

IN/OUT

HID IO 10

ADR1/GPIO 9

IN/OUT

HID IO 9

ADR0/GPIO 8

IN/OUT

HID IO 8

GPIO 7

IN/OUT

HID IO 7

GPIO 6

IN/OUT

HID IO 6

GPIO 5

IN/OUT

HID IO 5

GPIO 4

IN/OUT

HID IO 4

GPIO 3

IN/OUT

HID IO 3

GPIO 2

IN/OUT

HID IO 2

Switchable driver (weak/strong)

UAC 355xB

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Micronas

GPIO 1

IN/OUT

HID IO 1

GPIO 0

IN/OUT

HID IO 0

SDA

IN/OUT

C Data

SCL

IN/OUT

C Clock

TRDY

OUT

Test Output Pin

VBUS

OBL

Sense USB Bus

Not Connected

VREG

OUT

OBL

Capacitor for internal supply

DMINUS

IN/OUT

OBL

USB DATA MINUS

DPLUS

IN/OUT

OBL

USB DATA PLUS

VSS

OBL

Digital VSS

VDD

OBL

Digital VDD

MCLK

OUT

S Master Clock (384 x 48 kHz)

USBCLK

IN/OUT

Direct ISO-Endpoint Output Clock

USBWSO

IN/OUT

Direct ISO-Endpoint Output Word Strobe

USBDAT

IN/OUT

Direct ISO-Endpoint Output Data

TEST

VSS

Test Enable

RES

VDD

Power On Reset, active low

SUSPEND

OUT

Low-Power Mode Indicator

SOF

OUT

1 ms Start-Of-Frame Signal

SEN

VSS

Suspend Enable

Not Connected

FOUTL

OUT

OBL

Output to left external filter

FOPL

IN/OUT

OBL

Filter Op Amp Inverting Input, left

FINL

IN/OUT

OBL

Input for FiltoutL

FOUTR

OUT

OBL

Output to right filter op amp

FOPR

IN/OUT

OBL

Right Filter op amp inverting input

FINR

IN/OUT

OBL

Input for FILTOUTR

OUTS

OUT

Analog Output Subwoofer

Switchable driver (weak/strong)

For non-USB codec applications leave D+/

vacant and connect VBUS pin to V

Pin
No.

Pin Name

Type

Connection

(If not used)

Short Description

UAC 355xB

DATA SHEET

April 15, 2003; 6251-544-1DS

Micronas

5.3. Pin Descriptions

5.3.1. Power Supply Pins

The UAC 355xB combines various analog and digital
functions which may be used in different modes. For
optimized performance, major parts have their own
power supply pins. All VSS power supply pins must be
connected.

VDD (39)
VSS (38)
The VDD and VSS power supply pair are connected
internally with all digital parts of the UAC 355xB.

AVDD (10)
AVDD is the supply pin for the voltage regulators at
AREG0 (9) and AREG1 (4).

AVSS0 (6)
AVSS0 is the ground connection for the headphone/
loudspeaker amplifier.

AVSS1 (5)
AVSS1 is the ground connection for the analog audio
processing parts, except the headphone/loudspeaker
amplifiers.

SREF (64)
Reference for analog audio signals. This pin is used as
reference for the internal op amps. This pin must be
blocked against SGND with a 3.3

�

F capacitor.

Note: The pin has a typical DC level of 1.725 V. It can

be used as reference input for external op amps
when no current load is applied.

SGND (63)
Reference ground for the internal band-gap and bias-
ing circuits. This pin should be connected to a clean
ground potential! Any external distortions on this pin
will affect the analog performance of the UAC 355xB.

AREG0 (9)
Voltage regulator output for headphone/loudspeaker
amplifiers supply. Connect an external ceramic capaci-
tor to stabilize the regulator output.

AREG1 (4)
Voltage regulator output for analog audio processing
parts supply, except the headphone/loudspeaker
amplifiers. Connect an external ceramic capacitor to
stabilize the regulator output.

5.3.2. Analog Audio Pins

FOUTL (50)
FOPL (51)
FINL (52)
FOUTR (53)
FOPR (54)
FINR (55)
FOPS (57)
Filter op amps are provided in the analog baseband
signal paths. These inverting op amps are freely
accessible for external use by these pins.

The FOUTL/R pins are connected with the buffered
output of the internal switch matrix. The FOPL/R pins
are directly connected with the inputs of the inverting
filter op amps. The FINL/R pins are connected to the
outputs of the op amps.

ADCL (60)
ADCR (59)
Line Input pins.

MICIN (62)
MICBIAS (61)
Microphone input pin and microphone power supply
pin.

OUTL (7)
OUTR (8)
OUTS (56)
These pins are connected to the internal output ampli-
fiers. OUTL/R can be used for either line-out or stereo
headphones. OUTS is the subwoofer output of line-out
type.

Caution: A short-circuit at these pins for more than a
momentary period may result in destruction of the
internal circuits.

DATA SHEET

UAC 355xB

Micronas

April 15, 2003; 6251-544-1DS

5.3.3. Interface Pins

DMINUS (36)
DPLUS (37)
Differential USB port pins. The DPLUS pin has an
internal switchable pull-up resistor. Both pins must be
connected to the USB bus via a series resistor.

VBUS (32)
Sense USB Bus.

USBCLK (41)
Direct ISO Endpoint Output Clock.

USBWSO (42)
Direct ISO Endpoint Word Strobe.

USBDAT (43)
Direct ISO Endpoint Output Data.

CLI (15)
Clock line for the I

S bus. In master mode, this line is

driven by the UAC 355xB; in slave mode, an external
I

S clock has to be supplied.

DAO (16)
Output of digital serial sound data of the UAC 355xB
on the I

S bus.

DAI (13)
Input of digital serial sound data to the UAC 355xB via
I

S bus.

WSI (14)
Word strobe line for the I

S bus. In master mode, this

line is driven by the UAC 355xB; in slave mode, an
external I

S word strobe has to be supplied.

MCLK (40)
I

S master clock pin.

SCA (29)
Via this pin, the I

C bus data is written to or read from

the UAC 355xB.

SCL(30)
Via this pin, the I

C bus clock signal has to be sup-

plied.

5.3.4. Other Pins

XTI (2)
XTO (3)
The XTI pin is connected to the input of the internal
crystal oscillator; the XTO pin to its output. Both pins
should be directly connected to the crystal and two
ground-connected capacitors (see application dia-
gram).

Note: Do not drive external clock circuits via XTI/XTO.

SEN (48)
Digital input that prevents the device from entering the
low-power mode. This pin is also used to signal remote
wake-up.

TEST (44)
Test enable. This pin is for test purposes only and
must always be connected to VSS.

VREG (35)
Voltage regulator output for USB transceiver supply.
Connect an external ceramic capacitor to stabilize the
regulator output.

RES (45)
A Low signal at this pin resets the chip.

GPIO 0...ADR/GPIO 11/PWM
(28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17)
These pins are configurable to be either input or output
and can be used to connect audio function keys or sig-
nalling LEDs.

RD (11)
GPIO read pin.

STRB (12)
GPIO strobe pin.

SUSPEND (46)
This pin indicates that the host PC sets the USB bus to
the suspend mode state.

SOF(47)
Start of Frame Signal. 1 ms signal that can be used for
external application circuits.

TRDY (31)
Test Output Pin. This pin is intended for test purposes
only and must not be connected.

UAC 355xB

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Micronas

5.4. Pin Configuration

Fig. 5�1: PMQFP64 and PQFN64 package

10 11 12 13 14 15 16

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

UAC 355xB

SEN

USBCLK1)

USBWSO1)

USBDAT1)

TEST

SUSPEND

SOF

RES

FINR

FOUTL

FOPL

FOUTR

FOPR

FINL

MCLK1)

VDD

VSS

DPLUS

VREG

DMINUS

OUTR

OUTL

AVSS0

AVSS1

XTO

XTI

AREG1

DAO1)

AREG0

AVDD

RD1)

STRB1)

WSI1)

CLI1)

DAI

OUTS

FOPS

ADCR

SGND

SREF

ADCL

MICIN

MICBIAS

GPIO 21)

VBUS

TRDY

SCL1)

GPIO 01)

GPIO 11)

SDA1)

GPIO 31)

GPIO 41)

GPIO 51)

GPIO 61)

ADR2/GPIO 101)

ADR3/GPIO 11/PWM1)

GPIO 71)

ADR1/GPIO 91)

ADR0/GPIO 81)

Switchable driver (weak/strong)

DATA SHEET

UAC 355xB

Micronas

April 15, 2003; 6251-544-1DS

5.6. Electrical Characteristics

5.6.1. Absolute Maximum Ratings

Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This
is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in
the "Recommended Operating Conditions/Characteristics" of this specification is not implied. Exposure to absolute
maximum ratings conditions for extended periods may affect device reliability.

Symbol

Parameter

Pin
Name

Min.

Max.

Unit

Ambient Operating Temperature

�

Case Operating Temperature
for PQFN64-1 package

�

Case Operating Temperature
for PMQFP64-2 package

105

�

Storage Temperature

125

�

TOT

Power Dissipation

650

SUPA

Analog Supply Voltage

AVDD

0.3

SUPA

Analog Supply Voltage

AVDD,
AREG0/1

0.3

SUPD

Digital Supply Voltage

VDD

0.3

GRND

Voltage Differences between
different Grounds

AVSS0,
AVSS1,
VSS

0.5

+0.5

Idig

Input Voltage, all digital inputs

0.3

SUPD

+ 0.3

Idig

Input Current, all digital inputs

+20

Odig

Output Current, all digital outputs

+50

Iana

Input Voltage, all analog inputs

0.3

VAREG0/1

+ 0.3

Iana

Input Current, all analog inputs

Oaudio

Output Current, audio output

3)4)

OUTL/R

0.2

AREG0

Output Current, analog regulator

AREG0

500

+20

AREG1

Output Current, analog regulator

AREG1

+20

Internal regulators used

If internal regulators are not used, connect AVDD to AREG0/1.

These pins are not short-circuit proof!

Positive value means current flowing into the circuit

UAC 355xB

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Micronas

5.6.2. Recommended Operating Conditions

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Temperature Ranges and Supply Voltages

Ambient Temperature Range

�

SUPA

Analog Audio Supply Voltage

AVDD

4.1

5.0

5.6

SUPA

Capacitor at analog supply pins to
ground

AVDD

220

SUPD

Digital Supply Voltage

VDD

4.1

5.0

5.6

SUPD

Capacitor at digital supply pin to
ground

VDD

100

SUPUSB

Capacitor at VBUS pin to ground

VBUS

Analog Reference

SREF1

Analog Reference Capacitor

SREF

3.3

�

SREF2

Ceramic Capacitor in parallel

SREF

100

Analog Audio Inputs

inAD

DC-Decoupling Capacitor at A/D
converter inputs

ADCL/R

390

inMI

DC-Decoupling Capacitor at
microphone input

MICIN

100

Analog Audio Filter Inputs and Outputs

AFLO

Analog Filter Load Output

FOUTL/R

7.5

AFLI

Analog Filter Load Input

FINL/R

5.0

7.5

FILTSUBW

Filter Capacitor for Subwoofer
output

FOPS

2.2

Analog Audio Outputs

AOL_HP

Output Load Headphone
(16

series resistor required)

OUTL/R

32
100

AOLSUBW

Line_out

Output Load Subwoofer
(if the max. capacitive load is
exceeded, a decoupling resistor
of 220

is mandatory)

DC-decoupling capacitor at sub-
woofer output

OUTS,

FINL/R

470

Please refer to Section 6. "UAC 3556/3554B Applications" on page 46

DATA SHEET

UAC 355xB

Micronas

April 15, 2003; 6251-544-1DS

Crystal Characteristics

Ambient Temperature Range

�

Load Resonance Frequency
at C

load

= 22 pF

XTI

MHz

ACLK

Clock Amplitude

XTI, XTO

0.5

REG1

0.5

F/F

Accuracy of Adjustment

500

ppm

F/F

Frequency Variation
versus Temperature

500

ppm

Equivalent Series Resistance

Shunt (parallel) Capacitance

Voltage Regulator

VREG

Voltage Regulator Capacitor
(ceramic, X5R)

VREG

330

1000

AREG0

Voltage Regulator Capacitor
(ceramic, X5R)

AREG0

330

470

600

AREG1

Voltage Regulator Capacitor
(ceramic, X5R)

AREG1

150

220

270

Transceiver

USB

Input Series Resistance

DPLUS/
DMINUS

24
(

�

5%)

For device characteristics please refer to page 40

load

should typically be 22 pF (+30% /

10%), e.g., Y5U. Refer to application circuit (see Fig. 6�3 on page 50).

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

UAC 355xB

DATA SHEET

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Micronas

5.6.3. Characteristics

At T

= 0

�

C to 70

�

C, V

SUPD

= 4.1 V to 5.6 V, V

SUPA

= 4.1 V to 5.6 V. Typical values at T

= 20

�

SUPD

= V

SUPA

= 5.0 V, quartz frequency = 12 MHz, duty cycle = 50%, bass/treble: 0 dB,

Micronas Dynamic Bass: off, AGC: off, equalizer: off (positive current flowing into the IC),
3 V Mode, reduced feature set, if not otherwise specified.

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

Digital Supply

VDD

Current Consumption

VDD

57
45

72 MHz APU clock
48 MHz APU clock

�

Suspend

Digital Input Pin

Input Leakage Current

GPIO[11:0],
SEN,
RES,
VBUS,
DAI, WSI,
CLI

�

GND

SUP

Input Low Voltage

0.4

Input High Voltage

SUPD

0.4V

Digital Output Pin

Output High Voltage

GPIO[11:0]
SUSPEND,
SOF, RD,
STRB,
WSI, CLI,
DAO,
SDA,
SCL,MCLK

SUPD

0.4

Pins set to output
I

out

=8 mA

Output Low Voltage

0.4

O_max

Max. Output Current

2)3)

output set to "weak"
output set to "strong"

Analog Supply

AVDD

Current Consumption
Analog Audio

AVDD

all analog blocks on,
Mute

120

135

�

Suspend

(external 16

series

resistor required)
Volume = 0 dB,
Input signal 1kHz at
0 dB

PSRR

Power Supply Rejection
Ratio for Analog Audio
Outputs (internal regulators
active)

AVDD,

OUTL/R/S

1 kHz sine wave at
100 mV

rms

100 kHz sine wave at

100 mV

rms

no load attached to GPIOs.

max. output current for driving LEDs is 20 mA.

the sum of these digital output pin currents must not exceed 100 mA. Higher currents might damage the device.

not tested in production.

Please consider power limitations due to USB specification.

DATA SHEET

UAC 355xB

Micronas

April 15, 2003; 6251-544-1DS

Microphone Bias

MICBIAS

Open Circuit Voltage
Microphone Bias

MICBIAS

2.9

3.0

3.1

MICBIAS

Output Current Microphone
Bias

MICBIAS

0.5

OUTMICB

Output Resistance
Microphone Bias

MICBIAS

100

180

210

PSRR

MICB

Power Supply Rejection
Ratio for Microphone Bias

AVDD,

MICBIAS

100

internal regulators
active, at maximum
load current (0.5 mA),
1 kHz sine wave at
100 mV

rms

Analog Supply Voltage Regulators

AREG

Output Voltage

AREG0/1,
AVSS0/1

3.3

3.5

3.7

Reference Frequency Generation

DCXTI

DC Voltage at Oscillator
Pins

XTI/O

0.5*
V

Areg1

Input Capacitance at
Oscillator Pin

XTI

Input Capacitance at
Oscillator Pin

XTO

XTALOUT

Voltage Swing at Oscillator
Pins (peak-peak)

XTI/O

0.6 *
V

Areg1

1.0 *
V

Areg1

OSC_rise

Oscillator Start-Up Time

after min. V

SUPA

reached

USB Transceiver

REG

Regulator Voltage

VREG

3.25

3.4

3.55

�

Driver Output Resistance
including the 24

external

serial resistor

D+/D

static, LOW or HIGH

/ t

Rise and Fall Times

D+/D

=50 pF,

driver mode

MA_TRTF

Rise/Fall Time Matching

D+/D

110

=50 pF,

driver mode

XOVER

Crossover Voltage

D+/D

1.3

1.65

2.0

=50 pF,

driver mode

CM_DREC

Differential Receiver
Common-Mode Range

D+/D

0.8

2.5

T_SREC

Single-ended Receiver
Threshold Voltage

D+/D

0.8

2.0

Switchable Pull-up Resistor

VREG, D+

1.5

USB connected

not tested in production

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

UAC 355xB

DATA SHEET

April 15, 2003; 6251-544-1DS

Micronas

Analog Audio

SREF

Signal Reference Voltage

SREF

1.6

1.725

1.8

10 M

referred to SGND

Analog Line Input Clipping
Level (at input volume 0 dB)

ADCL/R

2.4

Microphone Input Clipping
Level (at minimum input
volume, i.e., 0 dB)

MICIN

283

Analog Output Voltage AC

OUTL/R

2.4

BW = 20 Hz...22 kHz,
R

10k

, volume =

0 dB, Input 1 kHz at
0 dB

digital (I

AOS

Analog Output Voltage AC

OUTS

2.35

BW = 20 Hz...22 kHz,
R

10 k

, volume =

0 dB, Input 100 Hz at
0 dB

digital (I

S),

inAI

Analog Line Input
Resistance

ADCL/R

120

at minimum input
volume, i.e.,

3 dB

at maximum input
volume, i.e., +19.5 dB

inMI

Microphone input resistance

MICIN

137

200

at minimum input
volume, i.e.,

at maximum input
volume, i.e., +22.5 dB

inAO

Analog output resistance

OUTL/R

volume=0 dB

inSO

Analog output resistance
subwoofer

OUTS

volume=0 dB

SNR

Signal-to-noise ratio of line
input

ADCL/R

dB(A)

BW = 20 Hz...22 kHz,
A-weighted, Input
1 kHz at V

20 dB,

volume= 0 dB, digital
output (I

SNR

Signal-to-noise ratio of
microphone input

MICIN

dB(A)

BW = 20 Hz...22 kHz,
A-weighted, Input
1 kHz at V

20 dB,

volume= 0 dB, digital
output (I

THD

Total harmonic distortion of
analog inputs

ADCL/R

MICIN

BW = 20 Hz...22 kHz,
volume = 0 dB,
Input 1 kHz at

3 dB

= V

3 dB

resp., V

3 dB, digital

output (I

related to 0 dB

input level

applying a signal of 280 mV

at the Microphone input delivers a 0 dB

signal at the ADC output (volume=0 dB)

not tested in production

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

DATA SHEET

UAC 355xB

Micronas

April 15, 2003; 6251-544-1DS

XTALK

Crosstalk attenuation
left/right channel for analog
inputs

ADCR/L -
ADCL/R,
MICIN

ADCL-
MICIN

BW = 20 Hz...22 kHz,
volume = 0 dB,
Input 1 kHz at

3 dB

digital output (I

PSRR

Power Supply Rejection
Ratio

AVDD,
OUTL/R

1 kHz sine wave at
100 mV

rms

AVDD,
OUTL/R

100 kHz sine wave at

100 mV

rms

PSRR

Power supply rejection ratio
for analog audio inputs

AVDD,
ADCL/R
MICIN

1 kHz sine at
100 mV

rms

, 3 V Mode,

digital output (I

10 kHz sine at

100 mV

rms

, 3 V Mode,

digital output (I

D/A

D/A Pass Band Ripple

OUTL/R

0.1

0...20 kHz
(with 2nd-order post
filter)

D/A

D/A Stop Band Attenuation

31 kHz...164 kHz
(with 2nd-order post
filter)

THD

Total Harmonic Distortion

OUTL/R

BW = 20 Hz...22 kHz,
R

10 k

, Volume =

0 dB, Input 1 kHz at

3 dB

digital (I

THD

Total Harmonic Distortion

OUTL/R

BW = 20 Hz...22 kHz,
unweighted, R

Volume = 0 dB, Input
1 kHz at

3 dB

digital

THD

SUBW

Total Harmonic Distortion

OUTS

BW = 20 Hz...22 kHz,
R

10 k

Volume = 0 dB, Corner
Frequency set to
400Hz,
Input 100 Hz at

3 dB

digital (I

SNR

AO1

Signal-to-Noise Ratio

OUTL/R

dB (A)

BW = 20 Hz...22 kHz,
A-weighted, R

10 k

Volume = 0 dB,
Input 1 kHz at

20 dB

digital (I

SNR

AO2

Signal-to-Noise Ratio

OUTL/R

102

dB (A)

BW = 20 Hz...22 kHz,
A-weighted, R

10 k

Volume =

40 dB,

Input 1 kHz at

3 dB

digital (I

related to 0 dB

input level

applying a signal of 100 mV

rms

at the Microphone input delivers a 0 dBFS signal at the ADC output (volume=0 dB)

not tested in production

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

UAC 355xB

DATA SHEET

April 15, 2003; 6251-544-1DS

Micronas

Different Characteristics in Five-Volt Mode

Lev

Mute

Mute Level L/R

OUTL/R

110

BW = 20 Hz...22 kHz
unweighted, no digital
input signal,
Volume = Mute

INL/R

Gain from ADC Inputs to
Outputs

ADCL/R,
OUTL/R

0.5

10 k

Volume = 0 dB; I
nput =

3 dB

Output Power
(Speaker/Headphone)

OUTL/R

eff

, 16

series

resistance,
Volume = 0 dB,
Input = 0 dB

digital

Output Power in Bridge
Mode
(Mono Speaker/
Headphone)

OUTL/R

180

eff

no series

resistors, right channel
inverted and output set
to mono (Bridge Mode)
Volume = 0 dB, Input =
0 dB

digital (I

VOL

Output Volume Setting
Range

OUTL/R

dVOL

Output Volume
Step Size

OUTL/R

VOL

Output Volume Error

OUTL/R

0.5

VOL

dGA

Analog Output Volume
Step Size Error

OUTL/R

0.5

XTALK

Crosstalk
Left/Right Channel
(Headphone)

OUTL/R

3 V Mode,

Volume = 0 dB,
Input =

3 dB

digital

related to 0 dB

input level

not tested in production

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

MICBIAS

Open Circuit Voltage
Microphone Bias

MICBIAS

3.9

4.0

4.1

SREF

Signal Reference Voltage

SREF

2.25

2.3

2.35

10 M

referred to SGND

Analog Line Input Clipping
Level (at input volume

dB)

ADCL/R

3.2

Microphone Input Clipping
Level (at minimum input
volume, i.e., 0 dB)

MICIN

370

Analog Output Voltage AC

OUTL/R

3.2

BW = 20 Hz...22 kHz,
R

10 k

, volume =

0 dB, Input 1 kHz at

3 dB

digital (I

AOS

Analog Output Voltage AC

OUTS

3.1

BW = 20 Hz...22 kHz,
R

10 k

, volume =

0 dB, Input 100 Hz at
0 dB

digital (I

DATA SHEET

UAC 355xB

Micronas

April 15, 2003; 6251-544-1DS

THD

Total Harmonic Distortion

OUTL/R

BW = 20 Hz...22 kHz,
R

10k

, Volume =

0 dB, Input 1 kHz at

3 dB

digital (I

SNR

AO1

Signal-to-Noise Ratio

OUTL/R

dB(A)

BW = 20 Hz...22 kHz,
A-weighted, R

10k

Volume = 0 dB,
Input 1 kHz at

20 dB

digital (I

SNR

AO2

Signal-to-Noise Ratio

OUTL/R

109

dB(A)

BW = 20 Hz...22 kHz,
A-weighted, R

10k

Volume =

40 dB,

Input 1 kHz at

3 dB

digital (I

Output Power
(Speaker/Headphone)

OUTL/R

eff

series

resistance,
Volume = 0 dB,
Input = 0 dB

digital

Output Power in Bridge
Mode
(Mono Speaker/Headphone)

OUTL/R

320

eff

no series

resistors, right channel
inverted and output set
to mono (bridge mode)
Volume = 0 dB, Input =
0 dB

digital (I

related to 0 dB

input level

not tested in production

Different Characteristics for Full-Feature Set (see Fig. 2�1 on page 6), Three-Volt Mode

SNR

AO1

Signal-to-Noise Ratio

OUTL/R

dB(A)

BW = 20 Hz...22 kHz,
A-weighted, R

10k

Volume = 0 dB,
Input 1 kHz at

20 dB

digital (I

SNR

AO2

Signal-to-Noise Ratio

OUTL/R

100

dB(A)

BW = 20 Hz...22 kHz,
A-weighted,
R

10 k

, Volume =

40 dB,
Input 1 kHz at

3 dB

digital (I

SNR

AS1

Signal-to-Noise Ratio

Subwoofer

OUTS

BW = 20 Hz...22 kHz,
unweighted,
R

10 k

Volume = 0 dB, Corner
Frequency set to
400 Hz, Input 100 Hz at

20 dB

digital (I

SNR

AS2

Signal-to-Noise Ratio

Subwoofer

OUTS

105

BW = 20 Hz...22 kHz,
unweighted,R

10k

Volume =

40 dB,

corner frequency set to
400 Hz, Input 100 Hz at

3 dB

digital (I

Lev

Mute

Mute Level Subwoofer

OUTS

BW = 20 Hz...400 Hz
unweighted, no digital
input signal, corner
frequency set to
400 Hz, Volume = Mute

UAC 355xB

DATA SHEET

April 15, 2003; 6251-544-1DS

Micronas

5.6.4. I

S Interface Timing Characteristics

The interfaces can be used in three different modes.

Fig. 5�1: Timing: synchronous I

S input / output

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

s_I2S

S Input Setup Time

before Rising Edge of Clock

CLI
DAI
USBCLK
USBDAT

h_I2S

S Input Hold Time

after Rising Edge of Clock

d_I2S

S Output Delay Time

after Falling Edge of Clock

CLI
WSI
DAO
USBCLK
USBWSI
USBDAT

=30 pF

o_I2S

S Output Setup Time

before Rising Edge of Clock

CLI
DAO
USBCLK
USBDAT

=30 pF

Detail C

WSI as OUTPUT

1/F

CLI

=325.5 ns

s_I2S

Detail A,B

DAI - Input

DAO - Output

s_I2S

o_I2S

d_I2S

CLI - Output

Detail D

WSI as OUTPUT

1/F

CLI

=325.5 ns

d_I2S

CLI - Output

R LSB L LSB

16/32 bit right channel

L LSB R MSB

Detail C

PHILIPS format

SONY format

WSI - Input

CLI - Input

DAI - Input

Detail A

PHILIPS format

SONY format

R LSB L MSB

16/32 bit left channel

1/F

I2SWS

Detail D

h_I2S

(30 pF load)

R LSB L LSB

16/32 bit right channel

L LSB R MSB

DAO - Output

Detail B

R LSB L MSB

16/32 bit left channel

DATA SHEET

UAC 355xB

Micronas

April 15, 2003; 6251-544-1DS

Fig. 5�2: Timing asynchronous I

S input

Fig. 5�3: Timing synchronous I

S Output

Detail C

WSI as INPUT

1/F

CLI

=325.5 ns

s_I2S

CLI - Input

Detail D

WSI as OUTPUT

1/F

CLI

=325.5 ns

d_I2S

CLI - Output

R LSB L LSB

16/32 bit right channel

L LSB R MSB

Detail C

PHILIPS format

SONY format

WSI - Input

CLI - Input

DAI - Input

Detail A

PHILIPS format

SONY format

R LSB L MSB

16/32 bit left channel

Detail A

DAI - Input

s_I2S

CLI - Input

h_I2S

Detail C

USBWSO as Output

1/F

CLI

=325.5 ns

s_I2S

USBCLK - Output

Detail D

USBWSO as Output

1/F

CLI

= 325.5 ns

d_I2S

USBCLK-Output

R LSB L LSB

16/32 bit right channel

L LSB R MSB

Detail C

PHILIPS format

SONY format

USBWSO

USBCLK

USBDAT

Detail A

PHILIPS format

SONY format

R LSB L MSB

16/32 bit left channel

Detail A

USBDAT - Output

USBCLK - Output

d_I2S

Detail D

o_I2S

- Output

UAC 355xB

DATA SHEET

April 15, 2003; 6251-544-1DS

Micronas

6. UAC 355xB Applications

6.1. Recommended Low-Pass Filters for Analog

Outputs

Fig. 6�1: 2

-order low-pass filter

If the filter is not used, then FOUTL(R), FOPL(R), and
FINL(R) are to be connected (dashed line) and the
internal op-amp must be switched off.

Note: First or third-order low-pass is also possible, but

then the frequency response degrades.

6.2. External Clocking via XTI

AC-coupling of the clock signal

The input level should be in the range of 0.5 to
2.5 V

. for a load capacitance of 22 pF at XTO.

DC-coupling of the clock signal

The DC input level must be 0.5

�

AREG1

which is typ-

ically 1.75 V. The input level should not exceed 0.5 to

2.5 V

Электронный компонент: UAC355xB

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