Replacement of
UC3714/UC3715
MIK3714/MIK3715
Complementary Switch
FET Driver
February 2001- revised September 2002
Description
These two families of high speed drivers are designed to provide drive waveforms for complementary switches. Complementary switch
configurations are commonly used in synchronous rectification circuits and active clamp/reset circuits, which can provide zero voltage
switching. In order to facilitate the soft switching transitions, independently programmable delays between the two output waveforms are
provided on these drivers. The delay pins also have true zero voltage sensing capability which allows immediate activation of the
corresponding switch when zero voltage is applied. These devices require a PWM-type input to operate and can be interfaced with
commonly available PWM controllers. In the MIK3714 series, the AUX output is inverted to allow driving a p-channel MOSFET. In the
MIK3715* series the two outputs are configured in a true complementary fashion.
* The MIK3715 series are not produced yet.
Features
Single Input (PWM and TTL Compatible)
High Current Power FET Driver, 1.0A Source/2A
Sink
Auxiliary Output FET Driver, 0.5A Source/1A Sink
Time Delays Between Power and Auxiliary
Outputs Independently Programmable from 50ns
to 500 ns
Time Delay or True Zero-Voltage Operation
Independently Configurable for Each Output
Switching Frequency to 1MHz
Typical 50 ns Propagation Delays
ENBL Pin Activates 220 A Sleep Mode
Power Output is Active Low in Sleep Mode
Synchronous Rectifier Driver
Block Diagram
ENABLE
1.4V
8
5
7
6
2
4
1
3
T2
T1
INPUT
50ns-500ns
50ns-500ns
UC3714
ONLY
LOGIC
GATES
TIMER
REF
BIAS
ENBL 3V
GND
PWR
AUX
VCC
GND
ENBL
Note: Pin numbers refer to J, N and D packages
Absolute Maximum Ratings
Symbol Parameter Maximum
Units
V
CC
Supply Voltage (low impedance source)
20
V
I
OH
Power Driver continuous
peak
-200
-1
mA
A
I
OL
Power Driver continuous
peak
400
2
mA
A
I
OH
Auxiliary Driver continuous
peak
-100
-500
mA
I
OL
Auxiliary Driver continuous
peak
200
1
mA
A
INPUT, ENBL Input Voltage Range
-0.3 to 20
V
Storage Temperature Range
-65 to150
o
C
Operating Junction Temperature (Note 1)
150
o
C
Lead Temperature (Soldering 10 seconds)
300
o
C
Note 1: Unless othervise indicated, voltages are referenced to ground and currents are positive info, negative out of, the specified
terminals.
Note 2: Consult Peckaging Section of databook for thermal limitations and specifications of packages.
Connection Diagrams
1
1
2
3
4
5
6
7
8 ENBL
PWR
DIL-8, SOIC-8 (Top View)
J or N, D Packages
SOIC-16 (Top View)
DP Packages
GND
AUX
INPUT
T1
T2
N/C
N/C
N/C
N/C
N/C
AUX
PWR
GND
GND
GND
GND
T2
ENBL
T1
INPUT
V
CC
V
CC
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Page 1 of 7
Replacement of
UC3714/UC3715
MIK3714/MIK3715
Complementary Switch
FET Driver
February 2001- revised September 2002
Electrical Characteristics
(V
CC
=15V,ENBL
2V, R
T
1=100k
from T1 to GND, R
T
2=100k
from T2 to GND, and T
A
=0
C to +70
C, for the
MIK3714/5, T
A
= T
J
unless otherwise stated)
Characteristics Symbol
Test
Condition
Min
Typ
Max
Units
Overall
V
CC
V
CC
7
20
V
I
CC
, nominal
I
CC
ENBL = 2.0V
18
24
mA
I
CC
, sleep model
I
CC sleep
ENBL = 0.8V
200
300
A
Power Driver (PWR)
Pre Turn-on PWR Output, Low
V
OL
Pre Turn-on V
CC
= 0V, I
OUT
= 10mA, ENBL
0.8V
0.3
1.6
INPUT = 0.8V, I
OUT
= 40 mA
0.3
0.8
PWR Output Low, Sat. (V
PWR
) V
OL
INPUT = 0.8V, I
OUT
= 400 mA
2.1
2.8
INPUT = 2.0V, I
OUT
= -20 mA
2.1
3
PWR Output High,
Sat. (V
CC
-V
PWR
)
V
OH
INPUT = 2.0V, I
OUT
= -200 mA
2.3
3
V
Rise Time
Tr
C
L
= 2200pF
30
60
Fall Time
Tf
C
L
= 2200pF
25
60
T1 Delay, AUX to PWR
T1 delay
INPUT = rising edge, R
T
1 = 10k
(Note 4)
20 35 80
T1 Delay, AUX to PWR
T1 delay
INPUT = rising edge, R
T
1 = 100k
(Note 4)
350 500 700
PWR Prop Delay
Tpd
INPUT falling edge, 50% (Note 3)
35
100
ns
Auxiliary Driver (AUX)
V
IN
= 2.0V, I
OUT
= 20mA
0.3
0.8
AUX Output Low, Sat (V
AUX
) V
OL
V
IN
= 2.0V, I
OUT
= 200mA
1.8
2.6
V
IN
= 0.8V, I
OUT
= -10mA
2.1
3.0
AUX Output High, Sat
(V
CC
-V
AUX
)
V
OH
V
IN
= 0.8V, I
OUT
= -100mA
2.3
3.0
V
Rise Time
Tr
C
L
= 1000pF
45
60
Fall Time
Tf
C
L
= 1000pF
30
60
T2 Delay, AUX to PWR
T2 delay
INPUT = rising edge, R
T
2 = 10k
(Note 4)
20 50 80
T2 Delay, AUX to PWR
T2 delay
INPUT = rising edge, R
T
2 = 100k
(Note 4)
250 350 550
AUX Prop Delay
Tpd
INPUT falling edge, 50% (Note 3)
35
80
ns
Enable (ENBL)
Input
Threshold
Vth
0.8 1.2 2.0 V
Input Current, I
IH
I
IH
ENBL = 15V
1
10
A
Input Current, I
IL
I
IL
ENBL = 0V
-1
-10
A
T1
Current Limit
I
LIM
T1 = 0V
-1.6
-2
mA
Nominal Voltage at T1
V
T1
2.7
3
3.3
V
Minimum T1 Delay
TdZVS
T1 = 2.5V (Note 4)
40
70
ns
T2
Current Limit
I
LIM
T2 = 0V
-1.2
-2
mA
Nominal Voltage at T2
V
T2
2.7
3
3.3
V
Minimum T2 Delay
TdZVS
T2 = 2.5V (Note 4)
50
100
ns
Input (INPUT)
Input
Threshold
Vth
0.8 1.4 2.0 V
Input Current, I
IH
I
IH
INPUT = 15V
1
10
A
Input Current, I
IL
I
IL
INPUT = 0V
-5
-20
A
Note 3: Propagation delay times are measured from the 50% point of the input signal to the 10% point of the output signal's transition
with no load on outputs.
Note 4: T1 delay is defined from the 50% point of the transition edge of AUX to the 10% of the rising edge of PWR. T2 delay is defined
from the 90% of the falling edge of PWR to the 50% point of the transition edge of AUX.
Page 2 of 7
Replacement of
UC3714/UC3715
MIK3714/MIK3715
Complementary Switch
FET Driver
February 2001- revised September 2002
Pin functions
Name Description
AUX:
The AUX switches immediately at INPUT`
S
rising edge but waits through the T2 delay after
INPUT
'
S
falling edge
before switching. AUX is capable of sourcing 0.5A and sinking 1.0A of drive current. See the Time Relationships
diagram below for the difference between the MIK3714 and MIK3715 for INPUT, MAIN, and AUX. During sleep
mode, AUX is inactive with a high impedance.
ENBL:
The ENBL input switches at TTL logic levels (approximately 1.2V), and its input range is from 0V to 20V.
The ENBL input will place the device into sleep mode when it is a logical low. The current into Vcc during the sleep
mode is typically 220A.
GND:
This is the reference pin for all input voltages and the return point for all device currents. It carries the full peak
sinking current from the outputs. Any tendency for the outputs to ring below GND voltage must be damped or
clamped such that GND remains the most negative potential.
INPUT:
The input switches at TTL logic levels (approximately 1.4V) but the allowable range is from 0V to 20V,
allowingdirect connection to most common IC PWM controller outputs. The rising edge immediately switches the
AUXoutput, and initiates a timing delay, T1, before switching on the PWR output. Similarly, the INPUT falling edge
immediately turns off the PWR output and initiates a timing delay, T2, before switching the AUX output.
It should be noted that if the input signal comes from a controller with FET drive capability, this signal
providesanother option. INPUT and PWR provide a delay only at the leading edge while INPUT and AUX provide
the delay at the trailing edge.
PWR:
The PWR output waits for the T1 delay after the
INPUT`
S
rising edge before switching on, but switches off
immediately at
INPUT`
S
falling edge (neglecting propagation delays). This output is capable of sourcing 1A and
sinking 2A of peak gate drive current. PWR output includes a passive, self-biased circuit which holds this pin
active low, when ENBL
0.8V regardless of VCC's voltage.
T1:
A resistor to ground programs the time delay between AUX switch turn-off and PWR turn-on.
T2:
This pin functions in the same way as T1 but controls the time delay between PWR turn-off and activation of the
AUX switch.
T1, T2:
The resistor on each of these pins sets the charging current on internal timing capacitors to provide independent
time control. The nominal voltage level at each pin is 3V and the current is internally limited to 1mA. The total
delay from INPUT to each output includes a propagation delay in addition to the programmable timer but since the
propagation delays are approximately equal, the relative time delay between the two outputs can be assumed to
be solely a function of the programmed delays. The relationship of the time delay vs. RT is shown in the Typical
Characteristics curves.
Either or both pins can alternatively be used for voltage sensing in lieu of delay programming. This is done by
pulling the timer pins below their nominal voltage level which immediately activates the timer output.
V
CC
:
The Vcc input range is from 7V to 20V. This pin should be bypassed with a capacitor to GND consistent with peak
load current demands.
Page 3 of 7
Replacement of
UC3714/UC3715
MIK3714/MIK3715
Complementary Switch
FET Driver
February 2001- revised September 2002
Typical Characteristics
T1DELAY
INPUT
T2DELAY
MIK3714 AUX OUTPUT
MIK3715 AUX OUTPUT
PROPAGATION
DELAYS
PWR OUTPUT
Time relationships (Notes 3, 4)
500
T1 Delay, T2 Delay vs. RT
T1 vs R 1
t
400
300
200
100
0
0
10
20
30
40
50
60
70
80
90
100
RT(k )
DE
L
A
Y
(
n
s
)
18
17
16
15
0
10
20
30
40 50
60 70
80 90 100
I
(
m
A
)
C
C
RT (k )
I vs R with Opposite = 50k
CC
T
R
T
0
Switc hing Frequenc y (kHz)
16
17
18
19
20
21
I
(
m
A
)
C
C
100 200 300 400 500 600 700 800 900 1000
I vs Switching Frequency with No Load and 50%
Duty Cycle R 1 = 2 = 50k
CC
T
R
T
T1 Deadband vs. Temperature AUX to PWR
500
600
400
300
200
100
0
-75
-50
-25
0
25
50
75
100
125
D
EAD
B
A
N
D
D
E
L
AY
(
N
S
)
TEMPERATUE( C)
0
R 1 = 10K
T
R 1 = 50K
T
R 1 = 100K
T
R 1 < 6K
T
T2 Deadband vs. Temperature AUX to PWR
500
600
400
300
200
100
0
D
EAD
B
A
N
D
D
E
L
AY
(
N
S
)
TEMPERATUE( C)
0
R = 10K
T2
R = 50K
T2
R = 100K
T2
R < 6K
T2
Page 4 of 7
Replacement of
UC3714/UC3715
MIK3714/MIK3715
Complementary Switch
FET Driver
February 2001- revised September 2002
Typical Characteristics
V
CC
V
CC
V
REF
PWM
GND
Figure 1. Typical application with timed delays
Figure 2. Using the timer input for
zero-voltage sensing
GND
GND
ENBL
INPUT
T1
T1
3.0V THRESHOLD
Bypass
Cap
Main
Power
Switch
Auxiliary
ZVS
Switch
R
T1
R
T2
R
T
T2
AUX
PWR
PWR
MIK3823
3842
,
MIK
,
etc.
MIK3714/5
MIK3714/5
V
CC
Figure 3. Self-actuated sleep mode with the absence of an input PWM signal. Wake up occurs with the first
pulse while turn-off is determined by the (RTO CTO) time constant.
V
CC
V
IN
L
0
D
0
Figure 4. Using the MIK3715 as a complementary synchronous rectifier switch driver with n-channel FETs
GND
C1
C2
C0
Q1
Q2
RL
RG
GND
AUX
PWR
MIK3714/5
Page 5 of 7
Replacement of
UC3714/UC3715
MIK3714/MIK3715
Complementary Switch
FET Driver
February 2001- revised September 2002
V
CC
V
IN
L
0
D
0
GND
GND
C1
D2
D3
D1
C0
Q1
Q2
RL
C2
AUX
PWR
MIK3714/5
Figure 5. Synchronous rectifier application with a charge pump to drive the high-side n-channel buck switch.
V is limited to 10V as V will rise to approximately 2V .
IN
CC
IN
V
CC
V
CC
V
IN
GND
ENBL
ENBLE
INPUT
T1
T2
AUX
PWR
PWM
MIK3714
Q2
Q1
R
T1
R
T2
C2
C3
C0
D
2
D
3
L
0
Figure 6. Typical forward converter topology with active reset provided by the U 3714 driving an N-channel
switch (Q1) and a P-channel auxiliary switch (Q2).
C
V
CC
V
CC
V
IN
V
V
GND
CC
IN
,
or
GND
ENBL
INPUT
T1
T2
AUX
PWR
MIK3714
Q2
Q1
Q4
Q3
Z1
R1
D1
C2
C4
C3
C0
D
2
D
3
FORWARD CONVERTER
L
0
Figure 7. Using an N-channel active reset switch with a floating drive command.
Page 6 of 7
Replacement of
UC3714/UC3715
MIK3714/MIK3715
Complementary Switch
FET Driver
February 2001- revised September 2002
Pad Location MIK3714
1
2
3
3
4
5
6
7
8
Chip size: 2.92mm x 2.12 mm
Pad Location Coordinates
(the center of pads)
Coordinates m
N
X Y
1 499
270
2 1059
292,5
3 1669,5
432
3 1842
195
4 2460
284
5 2670,5
1861,5
6 495
1881,5
7 245
1881,5
8 245
1656,5
Page 7 of 7
PDF 
ZIP