Document Outline

• Contents
• Figures
• Tables
• 1.0 Pin Descriptions
  • 1.1 Pin Assignments
    • Figure 1-1. Bt8370/75/76 Pinout Diagram
    • Figure 1-2. Bt8370/75/76 Logic Diagram
    • Table 1-1. Hardware Signal Definitions (7 of 8)
• 2.0 Circuit Description
  • 2.1 Bt8370/75/76 Block Diagrams
    • Figure 2-1. Detailed Bt8370 Block Diagram
    • Figure 2-2. Detailed Bt8375 Block Diagram
    • Figure 2-3. Detailed Bt8376 Block Diagram
  • 2.2 Receive Line Interface Unit
    • Figure 2-4. RLIU Diagram
    • Figure 2-5. RLIU Waveforms�Bipolar Input Signal
    • Figure 2-6. RLIU Waveforms�P and N Rail Digital Input Signal
    • 2.2.1 Data Recovery
      • 2.2.1.1 Automatic Gain Control
      • 2.2.1.2 Variable Gain Amplifier
      • 2.2.1.3 Adaptive Equalizer
      • 2.2.1.4 Data Slicer
    • 2.2.2 Clock Recovery
      • 2.2.2.1 Phase Locked Loop
        • Figure 2-7. Receive Input Jitter Tolerance
  • 2.3 Jitter Attenuator
    • Figure 2-8. Jitter Attenuator Block Diagram
    • 2.3.1 Elastic Store
      • Figure 2-9. CLAD/JAT Input Jitter Tolerance
      • Figure 2-10. CLAD/JAT Jitter Transfer Functions
      • Table 2-1. CLAD/JAT Jitter Transfer Functions
  • 2.4 Receiver
    • Figure 2-11. RCVR Diagram
    • 2.4.1 ZCS Decoder
    • 2.4.2 In-Band Loopback Code Detection
    • 2.4.3 Error Counters
      • 2.4.3.1 Frame Bit Error Counter
      • 2.4.3.2 CRC Error Counter
      • 2.4.3.3 LCV Error Counter
      • 2.4.3.4 FEBE Counter
    • 2.4.4 Error Monitor
    • 2.4.5 Alarm Monitor
      • 2.4.5.1 Loss of Frame
      • 2.4.5.2 Loss of Signal
      • 2.4.5.3 Analog Loss of Signal
      • 2.4.5.4 Alarm Indication Signal
      • 2.4.5.5 Yellow Alarm
      • 2.4.5.6 Multiframe YEL
      • 2.4.5.7 Severely Errored Frame
      • 2.4.5.8 Change of Frame Alignment
      • 2.4.5.9 Receive Multiframe AIS
    • 2.4.6 Test Pattern Receiver
    • 2.4.7 Receive Framing
      • Table 2-2. Receive Framer Modes 
      • Table 2-3. Criteria for Loss/Recovery of Receive Framer Alignment (1 of 2)
    • 2.4.8 External Receive Data Link
      • Figure 2-12. Receive External Data Link Waveforms
    • 2.4.9 Sa-Byte Receive Buffers
    • 2.4.10 Receive Data Link
      • 2.4.10.1 Data Link Controllers
        • Table 2-4. Commonly Used Data Link Settings
        • Figure 2-13. Polled Receive Data Link Processing
        • Figure 2-14. Interrupt Driven Receive Data Link Processing
      • 2.4.10.2 RBOP Receiver
  • 2.5 Receive System Bus
    • Figure 2-15. RSB Waveforms
    • Figure 2-16. RSB 4.096 MHz Bus Mode Time Slot Interleaving
    • Figure 2-17. RSB 8.192 MHz Bus Mode Time Slot Interleaving
    • Table 2-5. RSB Interface Time Slot Mapping
    • Figure 2-18. RSB Diagram
    • 2.5.1 Timebase
    • 2.5.2 Slip Buffer
      • Figure 2-19. T1 Line to E1 System Bus Time Slot Mapping
    • 2.5.3 Signaling Buffer
    • 2.5.4 Signaling Stack
    • 2.5.5 Embedded Framing
      • Figure 2-20. G.802 Embedded Framing
  • 2.6 Clock Rate Adapter
    • Figure 2-21. Clock Rate Adapter/Jitter Attenuator Block Diagram (Bt8370 and Bt8375 Devices)
    • Figure 2-22. Clock Rate Adapter/Jitter Attenuator Block Diagram (Bt8376 Device Only)
    • Table 2-6. JCLK/CLADO Timing Reference 
    • Table 2-7. Jitter Generation Requirements
    • 2.6.1 Configuring the CLAD Registers
      • Table 2-8. CLADO Frequencies Selection 
      • Table 2-9. Common CLADI Reference Frequencies and CLAD Configuration Examples (1 of 2)
  • 2.7 Transmit System Bus
    • Figure 2-23. TSB Interface Block Diagram
    • Figure 2-24. Transmit System Bus Waveforms
    • Figure 2-25. TSB 4.096 MHz Bus Mode Time Slot Interleaving
    • Figure 2-26. TSB 8.192 MHz Bus Mode Time Slot Interleaving
    • 2.7.1 Timebase
    • 2.7.2 Slip Buffer
    • 2.7.3 Signaling Buffer
    • 2.7.4 Transmit Framing
      • Figure 2-27. Transmit Framing and Timebase Alignment Options 
    • 2.7.5 Embedded Framing
  • 2.8 Transmitter
    • Figure 2-28. XMTR Diagram
    • 2.8.1 External Transmit Data Link
      • Figure 2-29. External Transmit Data Link Waveforms
    • 2.8.2 Transmit Data Links
      • 2.8.2.1 Data Link Controllers
        • Table 2-10. Commonly Used Data Link Settings
        • Figure 2-30. Polled Transmit Data Link Processing
        • Figure 2-31. Interrupt-Driven Transmit Data Link Processing
      • 2.8.2.2 PRM Generator
    • 2.8.3 Sa-Byte Overwrite Buffer
    • 2.8.4 Overhead Pattern Generator
      • 2.8.4.1 Framing Pattern Generation
      • 2.8.4.2 Alarm Generator
        • Table 2-11. Yellow Alarm Generation
        • Table 2-12. Yellow Alarm Register Bits
        • Table 2-13. Multiframe Yellow Alarm Generation
        • Table 2-14. Multiframe Yellow Alarm Register Bits
      • 2.8.4.3 CRC Generation
      • 2.8.4.4 Far-End Block Error Generation
    • 2.8.5 Test Pattern Generator
    • 2.8.6 Transmit Error Insertion
    • 2.8.7 In-Band Loopback Code Generator
    • 2.8.8 ZCS Encoder
      • Figure 2-32. Zero Code Substitution Formats
  • 2.9 Transmit Line Interface Unit
    • Figure 2-33. TLIU Diagram
    • Figure 2-34. TLIU Waveform
    • 2.9.1 Pulse Shape
      • Figure 2-35. Standard DS1 Pulse Template
      • Figure 2-36. T1 Pulse Template Test Circuit
      • Figure 2-37. Standard E1 (G.703) Pulse Template
      • Figure 2-38. E1 (G.703) Pulse Template Test Circuit
      • Table 2-15. ANSI T1.102, 1993�DS1 Pulse Template Corner Points, Maximum Curve 
      • Table 2-16. ANSI T1.102, 1993�DS1 Pulse Template Corner Points, Minimum Curve 
      • Table 2-17. ANSI T1.403, 1995�DS1 Pulse Template Corner Points, Maximum Curve
      • Table 2-18. ANSI T1.403, 1995�DS1 Pulse Template Corner Points, Minimum Curve
      • Table 2-19. G.703, 1988�DS1 Pulse Template Corner Points, Maximum Curve
      • Table 2-20. G.703, 1988�DS1 Pulse Template Corner Points, Minimum Curve
      • Table 2-21. G.703, 1988�Pulse Template Corner Points, Maximum Curve
      • Table 2-22. G.703, 1988�Pulse Template Corner Points, Minimum Curve
      • Figure 2-39. Digitized AMI Pulse Shape
    • 2.9.2 Transmit Phase Lock Loop
      • 2.9.2.1 Clock Reference
        • Figure 2-40. TPLL Input Clock Jitter Tolerance
      • 2.9.2.2 Output Jitter
    • 2.9.3 Line Build Out
      • Figure 2-41. 0 dB LBO Isolated Pulse Template
      • Figure 2-42. 7.5 dB LBO Isolated Pulse Template
      • Figure 2-43. 15.0 dB LBO Isolated Pulse Template
      • Figure 2-44. 22.5 dB LBO Isolated Pulse Template
    • 2.9.4 Line Driver
      • 2.9.4.1 Termination Impedance
        • Figure 2-45. External Termination Resistor Placement
      • 2.9.4.2 Return Loss
        • Figure 2-46. Nominal Return Loss
        • Figure 2-47. Output Pulse Height versus Transmit Termination Impedance
      • 2.9.4.3 Output Enable
    • 2.9.5 Pulse Imbalance
  • 2.10 Microprocessor Interface
    • Figure 2-48. Microprocessor Interface Block Diagram
    • 2.10.1 Address/Data Bus
    • 2.10.2 Bus Control Signals
      • Table 2-23. Microprocessor Interface Operating Modes
    • 2.10.3 Interrupt Requests
    • 2.10.4 Device Reset
      • 2.10.4.1 Power-On Reset (POR)
      • 2.10.4.2 Hardware Reset
      • 2.10.4.3 Software Reset
  • 2.11 Loopbacks
    • 2.11.1 Remote Line Loopback
    • 2.11.2 Remote Payload Loopback
    • 2.11.3 Remote Per-Channel Loopback
    • 2.11.4 Local Analog Loopback
    • 2.11.5 Local Framer Loopback
    • 2.11.6 Local Per-Channel Loopback
  • 2.12 Joint Test Access Group
    • Figure 2-49. JTAG Diagram
    • 2.12.1 Instructions
      • Table 2-24. JTAG Instructions
    • 2.12.2 Device Identification Register
      • Table 2-25. Bt8370/75/76 Device Identification JTAG Register
      • Table 2-26. Bt8375 Device Identification JTAG Register
      • Table 2-27. Bt8376 Device Identification JTAG Register
• 3.0 Registers
  • 3.1 Address Map
    • Table 3-1. Address Map (8 of 8)
  • 3.2 Global Control and Status Registers
    • Table 3-2. Receive Framer Modes
  • 3.3 Interrupt Control Register
  • 3.4 Interrupt Status Registers
    • Table 3-3. Interrupt Status Register Summary 
  • 3.5 Interrupt Enable Registers
    • Table 3-4. Counter Overflow Behavior
  • 3.6 Primary Control and Status Registers
    • Table 3-5. Maximum Average Reframe Time (MART) and Framer Time-out
    • Table 3-6. System Bus Synchronization Mode Summary 
    • Table 3-7. Common TFSYNC and TMSYNC Configurations
    • Table 3-8. Common RFSYNC and RMSYNC Configurations
  • 3.7 Receive LIU Registers
    • Table 3-9. Receive Sensitivity versus Application
    • Table 3-10. VGA Maximum Settings for Receive Sensitivity
    • Figure 3-1. Receive Equalizer Eye Pattern Output
  • 3.8 Receiver Registers
    • Table 3-11. Receive PRBS Test Pattern
    • Table 3-12. Receive Yellow Alarm
    • Table 3-13. Receive Yellow Alarm Set/Clear Criteria
  • 3.9 Performance Monitoring Registers
  • 3.10 Receive Sa-Byte Buffers
  • 3.11 Transmit LIU Registers
    • Table 3-14. Return Loss Values 
  • 3.12 Transmitter Registers
    • Table 3-15. E1 Transmit Framer Modes (T1/E1N = 0)
    • Table 3-16. T1 Transmit Framer Modes (T1/E1N = 1)
    • Table 3-17. Criteria for E1 Loss/Recovery of Transmit Frame Alignment 
    • Table 3-18. Criteria for T1 Loss/Recovery of Transmit Frame Alignment 
    • Table 3-19. Transmit Framer Position
    • Table 3-20. Transmit Zero Code Suppression 
    • Table 3-21. Transmit PRBS Test Pattern
  • 3.13 Transmit Sa-Byte Buffers
  • 3.14 Clock Rate Adapter Registers
  • 3.15 Bit-Oriented Protocol Registers
    • Table 3-22. Datalink Configuration Register Description
  • 3.16 Data Link Registers
  • 3.17 System Bus Registers
    • Table 3-23. Remote DS0 Channel Loopback
  • 3.18 Register Summary
    • Table 3-24. Global Control and Status Registers
    • Table 3-25. Interrupt Request Register
    • Table 3-26. Interrupt Status Registers
    • Table 3-27. Interrupt Enable Registers
    • Table 3-28. Primary Control and Status Registers
    • Table 3-29. Receive LIU Registers
    • Table 3-30. Receiver Registers
    • Table 3-31. Performance Monitoring Registers
    • Table 3-32. Receive Sa-Byte Buffers
    • Table 3-33. Transmit LIU Registers 
    • Table 3-34. Transmitter Registers 
    • Table 3-35. Transmit Sa-Byte Buffers
    • Table 3-36. CLAD Registers
    • Table 3-37. Bit-Oriented Protocol Registers
    • Table 3-38. Data Link Registers (2 of 2)
    • Table 3-39. System Bus Registers (2 of 2)
• 4.0 Applications
  • 4.1 External Component Specifications
    • Table 4-1. Transformer Specifications 
    • Table 4-2. REFCKI (10 MHz) Crystal Oscillator Specifications
    • Figure 4-1. Option A: Long Haul Application with Ground Reference on the Line Side (1 of 2)
    • Figure 4-2. Option B: Long Haul with No Ground Reference (1 of 2)
    • Figure 4-3. Option C: Long Haul Application with No Ground Reference on the Line (1 of 2)
    • Figure 4-4. Option D: Short Haul Application (1 of 2)
• 5.0 Electrical/Mechanical Specifications
  • 5.1 Absolute Maximum Ratings
    • Table 5-1. Absolute Maximum Ratings
  • 5.2 Recommended Operating Conditions
    • Table 5-2. Recommended Operating Conditions
  • 5.3 Electrical Characteristics
    • Table 5-3. DC Characteristics 
    • Table 5-4. Line Interface Unit (RLIU, TLIU) Performance Characteristics 
  • 5.4 AC Characteristics
    • Table 5-5. Input Clock Timing
    • Figure 5-1. Minimum Clock Pulse Widths
    • Table 5-6. Input Data Setup and Hold Timing 
    • Table 5-7. Output Data Delay Timing
    • Table 5-8. One-Second Input/Output Timing
    • Figure 5-2. Input Data Setup/Hold Timing
    • Figure 5-3. Output Data Delay Timing
    • Figure 5-4. 1-Second Input/Output Timing
    • Figure 5-5. SBI Timing: Setup and Hold Time for RFSYNC/RMSYNC and TFSYNC/TMSYNC Input Signals
  • 5.5 MPU Interface Timing
    • Figure 5-6. Motorola Asynchronous Read Cycle
    • Table 5-9. Motorola Asynchronous Read Cycle
    • Figure 5-7. Motorola Asynchronous Write Cycle
    • Table 5-10. Motorola Asynchronous Write Cycle
    • Figure 5-8. Intel Asynchronous Read Cycle
    • Table 5-11. Intel Asynchronous Read Cycle
    • Figure 5-9. Intel Asynchronous Write Cycle
    • Table 5-12. Intel Asynchronous Write Cycle
    • Figure 5-10. Motorola Synchronous Read Cycle
    • Table 5-13. Motorola Synchronous Read Cycle
    • Figure 5-11. Motorola Synchronous Write Cycle
    • Table 5-14. Motorola Synchronous Write Cycle
    • Figure 5-12. Intel Synchronous Read Timing
    • Table 5-15. Intel Synchronous Read Cycle (MOTO* = 1, SYNCMD = 1, CLKMD = 1)
    • Figure 5-13. Intel Synchronous Write Timing
    • Table 5-16. Intel Synchronous Write Cycle (MOTO* = 1, SYNCMD = 1, CLKMD = 1)
  • 5.6 System Bus Interface (SBI) Timing
    • Figure 5-14. SBI Timing�1536K Mode
    • Figure 5-15. SBI Timing�1544K Mode
    • Figure 5-16. SBI Timing�2048K Mode
    • Figure 5-17. SBI Timing�4096K Mode
    • Figure 5-18. SBI Timing�8192K Mode
    • Figure 5-19. SBI Timing�Eight Clock Edge Combinations (Applicable to Any SBI Mode)
  • 5.7 JTAG Interface Timing
    • Table 5-17. Test and Diagnostic Interface Timing Requirements
    • Table 5-18. Test and Diagnostic Interface Switching Characteristics
    • Figure 5-20. JTAG Interface Timing
  • 5.8 Mechanical Specifications
    • Figure 5-21. 80-Pin Metric Quad Flat Pack (MQFP)
• Appendix A: T1, E1 Framing Format
  • A.1 Superframe Format (SF)
    • Figure A-1. T1 Superframe PCM Format
    • Table A-1. Superframe Format
  • A.2 T1DM Format
    • Table A-2. T1DM Frame Format
  • A.3 SLC 96 Format (SLC)
    • Table A-3. SLC-96 Fs Bit Contents
  • A.4 Extended Superframe Format (ESF)
    • Figure A-2. T1 Extended Superframe PCM Format
    • Table A-4. Extended Superframe Format
    • Table A-5. Performance Report Message Structure
  • A.5 E1 Frame Format
    • Figure A-3. E1 Format
    • Table A-6. ITU�T CEPT Frame Format Time Slot 0-Bit Allocations
  • A.6 IRSM CEPT Frame Format
    • Table A-7. IRSM CEPT Frame Format Time Slot 0-Bit Allocations
    • Table A-8. CEPT (ITU�T and IRSM) Frame Format Time Slot 16-Bit Allocations
• Appendix B: Applicable Standards
  • B.1 Applicable Standards
    • Table B-1. Applicable Standards (3 of 3)
• Appendix C: System Bus Compatibility
  • C.1 System Bus Compatibility
    • C.1.1 AT&T Concentration Highway Interface (CHI)
    • C.1.2 CHI Programming Options
• Appendix D: Receive Line Interface Software Driver
  • D.1 Receive Line Interface Unit Software Enhancement Description
  • D.2 RLIU Software Driver
    • Figure D-1. Initialize Bt8370
    • Figure D-2. VGA Processing
    • Figure D-3. The Short Haul and Long Haul State for Twisted Pair Interface
    • Figure D-4. The Short Haul and Long Haul State for E1-75 Interface
  • D.3 The RLIU Software Driver Routine
  • D.4 Short Haul Software Coefficient Table
    • D.4.1 Coefficient Table for Short Haul Twisted Pair T1/E1 120/100 W Interface
    • D.4.2 Coefficient Table for Short Haul Coax 75 W Interface
  • D.5 Long Haul Coefficients Table
    • D.5.1 Default Long Haul Coefficients
    • D.5.2 RLIU State Machine
    • D.5.3 VGA Processing Routine
    • D.5.4 Short Haul State
    • D.5.5 Long Haul State
    • D.5.6 Writing Coefficient from Short Haul Coefficient Table
    • D.5.7 Monitoring PRE Equalizer
  • D.6 Bt8370 Type-defined Device Structure
• Appendix E: Basic Configurations for the Bt8370
  • E.1 Basic E1 Configurations
    • Table E-1. E1-FAS (4 of 4)
    • Table E-2. E1-FAS+CRC (4 of 4)
    • Table E-3. E1-FAS_CAS (4 of 4)
    • Table E-4. E1-FAS_CAS_CRC4 (4 of 4)
  • E.2 Basic T1 Configurations
    • Table E-5. T1-ESF (4 of 4)
    • Table E-6. T1-SF (4 of 4)
    • Table E-7. T1-ESF_1536M_Sys_Bus (4 of 4)
• Appendix F: Notation and Acronyms
  • F.1 Notation and Acronyms
    • F.1.1 Arithmetic Notation
  • F.2 Acronyms and Abbreviations