Data Sheet
28237-DSH-001-B
March 2000
CN8237
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
The CN8237 Service Segmentation and Reassembly (ServiceSAR) Controller integrates ATM
terminal functions, PCI Bus Master and Slave controllers, and a UTOPIA 1 or 2 interface with
service-specific functions in a single package for AAL0 and AAL5 operations. The ServiceSAR
Controller generates and terminates ATM traffic and automatically schedules cells for
transmission. The CN8237 is targeted at 622 Mbps throughput systems where the number of
VCCs is relatively large, or the performance of the overall system is critical. Networking
equipment it supports ranges from routers and Ethernet switches to ATM Edge switches and
Frame Relay switches.
Service-Specific Performance Accelerators
The CN8237 incorporates numerous service-specific features designed to accelerate and
enhance system performance. For instance, the CN8237 implements Echo Suppression of
LAN traffic via LECID filtering and supports Frame Relay DE to CLP interworking.
Advanced xBR Traffic Management
The xBR Traffic Manager in the CN8237 supports multiple ATM service categories. Categories
include CBR, VBR (both single and dual leaky bucket), UBR, GFR (Guaranteed Frame Rate),
and ABR (explicit rate, relative rate, or EFCI marking). The CN8237 manages each VCC
independently. It dynamically schedules segmentation traffic to comply with up to 16+ CBR
user-configured scheduling priorities for the various traffic classes. Scheduling control is
based on a user-specified time reference. ABR channels are managed in hardware according
to user-programmable ABR templates. These templates tune the performance of the
CN8237's ABR algorithms to a specific system's or network's requirements (user-defined
granularity).
Continued
Functional Block Diagram
Multi-client
PCI Bus
Timer
Counters
RSM Local
Memory Bus
SEG Local
Memory Bus
PCI
Master/
Slave
DMA
Co-
Proc'r
Local RSM
Memory Interface
Local SEG
Memory Interface
Reassembly
Coprocessor
Segmentation
Coprocessor
CBR, VBR, ABR,
UBR, GFR
Traffic Manager
PHY Interface
RX/TX
UTOPIA
Master/
Slave
Control/
Status
CN8237
CX29704
PHY
Device
Cell
FIFO
LIU
LIU
LIU
LIU
Patent Nos. 5,949,781
5,768,275
5,889,779
Distinguishing Features
Service-Specific Performance
Accelerators
LECID filtering and echo
suppression
Dual leaky bucket based on
CLP (frame relay)
Frame relay DE interworking
Internal SNMP MIB counters
IP over ATM; supports both
CLP0+1 and ABR shaping
Flexible Architectures
Multi-peer host
Direct switch attachment via
reverse UTOPIA
ATM terminal
Host control
Local bus control
Continued
28237-DSH-001-B
Mindspeed Technologies
TM
07/17
/02 5:00 PM
19992003,
Mindspeed TechnologiesTM, a Conexant business
All Rights Reserved.
Information in this document is provided in connection with Mindspeed Technologies ("Mindspeed") products. These materials are
provided by Mindspeed as a service to its customers and may be used for informational purposes only. Mindspeed assumes no
responsibility for errors or omissions in these materials. Mindspeed may make changes to specifications and product descriptions at
any time, without notice. Mindspeed makes no commitment to update the information and shall have no responsibility whatsoever for
conflicts or incompatibilities arising from future changes to its specifications and product descriptions.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as
provided in Mindspeed's Terms and Conditions of Sale for such products, Mindspeed assumes no liability whatsoever.
THESE MATERIALS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, RELATING
TO SALE AND/OR USE OF MINDSPEED PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A
PARTICULAR PURPOSE, CONSEQUENTIAL OR INCIDENTAL DAMAGES, MERCHANTABILITY, OR INFRINGEMENT OF ANY
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MATERIALS. MINDSPEED SHALL NOT BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL
DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS, WHICH MAY RESULT FROM THE USE
OF THESE MATERIALS.
Mindspeed products are not intended for use in medical, lifesaving or life sustaining applications. Mindspeed customers using or
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damages resulting from such improper use or sale.
The following are trademarks of Conexant Systems, Inc.: Mindspeed TechnologiesTM, the MindspeedTM logo, and "Build It First"TM.
Product names or services listed in this publication are for identification purposes only, and may be trademarks of third parties.
Third-party brands and names are the property of their respective owners.
For additional disclaimer information, please consult Mindspeed Technologies Legal Information posted at
www.mindspeed.com
which is incorporated by reference.
Ordering Information
Document Revision History
Model Number
Manufacturing
Part Number
Product
Revision
Package
Operating Temperature
CN8237EBGB
28237-12
B
456-pin BGA
40 C to 85 C
Revision
Level
Date
Description
100454A
Advanced
April 1999
Created
100454B
Advanced
March 2000
Revisions made.
100454C
Advanced
February 2001
Revisions made.
500376A
Advanced
July 2002
Revisions made. Changed format from Conexant to
Mindspeed.
28237-DSH-001-B
Advanced
May 2003
Revisions made denoted by change bars.
28237-DSH-001-B
Mindspeed Technologies
TM
Continued from Front
Multi-Queue Segmentation Processing
The CN8237's segmentation coprocessor generates ATM cells for up to 64 K VCCs at a line rate of up to 600 Mbps for
simplex connections. The segmentation coprocessor formats cells on each channel according to segmentation VCC
tables, utilizing up to 32 independent transmit queues and reporting segmentation status on a parallel set of up to 32
segmentation status queues. The segmentation coprocessor gathers client data from the host, formats ATM cells while
generating and appending protocol overhead, and forwards these to the UTOPIA port. The segmentation coprocessor
operates as a slave to the xBR Traffic Manager which schedules VCCs for transmission.
Multi-Queue Reassembly Processing
The CN8237's reassembly coprocessor stores the payload data from the cell stream received by the UTOPIA port into
host data buffers. Using a dynamic lookup method which supports NNI or UNI addressing, the reassembly coprocessor
processes up to 64 K VCCs simultaneously at a line rate up to 600 Mbps. The host supplies free buffers on up to 32
independent free buffer queues. The reassembly coprocessor performs all CPCS protocol checks and reports the
results of these checks and other status data on one of 32 independent reassembly status queues.
High Performance Host Architecture with Buffer Isolation
The CN8237 host interface architecture maximizes performance and system flexibility. The device's control and status
queues enable host/SAR communication via write operations alone. This "write only" architecture lowers latency and
PCI bus occupancy. Flexibility is achieved by supporting a scalable peer-to-peer architecture. Multiple host clients can
be addressed by the segmentation and reassembly (SAR) as separate physical or logical PCI peers. Segmentation and
reassembly data buffers on the host system are identified by buffer descriptors in SAR-local (or host) memory which
contain pointers to buffers. The use of buffer descriptors in this way allows isolation of data buffers from the
mechanisms that handle buffer allocation and linking. This provides a layer of indirection in buffer assignment and
management that maximizes system architecture flexibility.
Designer Toolkit
Mindspeed supplies a toolkit designers can use to establish an evaluation environment for the CN8237. The toolkit,
(CN8237EVM) includes a working reference design, an example of a software driver, and facilities for generating and
terminating all service categories of ATM traffic. In addition, because the CN8237 buffer management and control
architecture is based on Mindspeed's 155 Mbps ServiceSAR family (Bt8233, RS8234, RS8235, and CN8236), it allows
for straight-forward migration of preexisting software. Together the toolkit and architecture enable rapid prototyping
and accelerate ATM system development.
28237-DSH-001-B
Mindspeed Technologies
TM
Continued Distinguishing Features
New Features
3.3 V, 456 BGA lowers power and
eases PCB assembly
64-bit/66 MHz PCI 2.1, including
support for serial EEPROM
Enhancements to xBR Traffic
Manager
fewer ABR templates
improved CBR tunneling
Reduced memory size for VCC
lookup tables
Increased addressing flexibility
Additional byte lane swappers for
increased system flexibility
Programmable size routing tags up
to 64 B cells
Selectable single/separate UTOPIA
clocks
Updated PM-OAM processing per
i.610
SECBC calculated per GR-1248
Compact PCI Hot Swap capabilities
Master PCI write over read arbitration
control
Multi-PHY UTOPIA Level 2
Head of line blocking protection for
multi-PHY operation
xBR Traffic Management
TM4.1 Service Classes
CBR
VBR (single, dual and CLP-based
leaky buckets)
Real time VBR
ABR (ER, RR, EFCI)
UBR
GFC (controlled and uncontrolled
flows)
Guaranteed Frame Rate (GFR)
(guaranteed MCR on UBR VCCs)
16 levels of priorities (16 + CBR)
Dynamic per-VCC scheduling
Multiple programmable ABR
templates (supplied by Mindspeed
or user)
Scheduler driven by selectable clock
Local system clock
External reference clock
Internal RM OAM cell feedback path
Virtual FIFO buffer rate matching
(Source Rate Matching)
Per-VCC MCR and ICR
Tunneling
VP tunnels (VCI interleaving on
PDU boundaries)
CBR tunnels (cells interleaved as
UBR, VBR, or ABR with an
aggregate CBR limit)
Multi-Queue Segmentation Processing
32 transmit queues with optional
priority levels
64 K VCCs maximum
AAL5 CPCS generation
AAL0 Null CPCS (optional use of PTI
for PDU demarcation)
ATM cell header generation
Raw cell mode (52 octet)
800 Mbps half duplex
622 Mbps full duplex (w/ 2-cell
PDUs)
Variable length transmit FIFO buffer -
CDV - host latency matching (1 to 9
cells)
Symmetric Tx and Rx architecture
buffer descriptors
queues
User defined field circulates back to
the host (32 bits)
Distributed host or SAR-shared
memory segmentation
Simultaneous segmentation and
reassembly
Per-PDU control of CLP/PTI (UBR)
Per-PDU control of AAL5 UU field
Message and streaming status
modes
Virtual Tx FIFO buffer (PCI host)
Multi-Queue Reassembly Processing
32 reassembly queues
64 K VCCs maximum
AAL5 CPCS checking
AAL0
PTI termination
Cell count termination
Early Packet Discard, based on:
Receive buffer underflow
Receive status overflow
CLP with priority threshold
AAL5 max PDU length
Rx FIFO buffer full
Frame relay DE with priority
threshold
LECID filtering and echo
suppression
Per-VCC firewalls
Dynamic channel lookup (NNI or UNI
addressing)
Supports full address space
Deterministic
Flexible VCI count per VPI
Optimized for signalling address
assignment
Message and streaming status
modes
Raw cell mode (52 octet)
800 Mbps half duplex
622 Mbps full duplex (with 2-cell
PDUs)
Distributed host or SAR-shared
memory reassembly
8 programmable reassembly
hardware time-outs (per-VCC
assignable)
Global max PDU length for AAL5
Per-VCC buffer firewall (memory
usage limit)
Simultaneous reassembly and
segmentation
Idle cell filtering
64 K duplex VCCs
High Performance Host Architecture
with Buffer Isolation
Write-only control and status
Read multiple command for data
transfer
Up to 32 host clients control and
status queues
Physical or logical clients
Enables peer-to-peer architecture
Descriptor-based buffer chaining
Scatter/gather DMA
Endian neutral (allows data word and
control word byte swapping, for both
big and little endian systems)
Non-word (byte) aligned host buffer
addresses
Automatically detects presence of Tx
data or Rx free buffers
Virtual FIFO buffers (PCI bursts
treated as a single address)
Hardware indication of BOM
Allows isolation of system resources
Status queue interrupt delay
Designer Toolkit
Evaluation hardware and software
Reference schematics
Hardware Programming
Interface-RS823xHPI reference
source code (C)
Generous Implementation of OAM-PM
Protocols
Detection of all F4/F5 OAM flows
Internal PM monitoring and
generation for up to 128 VCCs
Optional global OAM Rx/Tx queues
In-line OAM insertion and generation
Continued
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