Data Sheet

Advance Information

N8380DSA

April 26, 1999

Advance Information

This document contains information on a product under development. The parametric information
contains target parameters that are subject to change.

CN8380

Quad T1/E1 Line Interface

The CN8380 is a fully integrated quad line interface unit for both 1.544 Mbps (T1) and
2.048 Mbps (E1) applications. It is designed to complement T1/E1 framers or operate as
a stand-alone line interface to synchronous or plesiochronous mappers and
multiplexers. The device can be controlled through a host mode serial port or by
hardware mode operation, where device control and status are obtained through
non-multiplexed dedicated pins. Many of these pins are also dedicated to individual
channels for maximum flexibility and for use in redundant systems. Integrated in the
CN8380 device is a clock rate adapter (CLAD), which provides various low-jitter
programmable system clock outputs. The receive section of the CN8380 is designed to
recover encoded signals from lines having up to 12 dB of attenuation. The transmit
section consists of a programmable, precision pulse shaper.

Functional Block Diagram

RPOSO[1]

RCKO[1]

TCLK[1]

TPOSI[1]

TNEGI[1]

RNEGO[1]

XTIP[1]

XRING[1]

RTIP[1]

RRING[1]

LIU #1

LIU #2

LIU #3

LIU #4

Clock Rate Adapter

Control

JTAG

Test Port

Pulse

Shaping

Driver

Jitter

Attenuator

ZCS

Decode

Local Analog Loopback

Re-
ceiver

TAIS

Clock

and

Data

Recovery

RLOS

Detect

Remote Line Loopback

Local Digital Loopback

ZCS

Decode

JTAG

Test

Signals

Control and

Alarm Signals

Host

Serial

Port

10 MHz

Fixed

Reference

Variable

Reference

1.544

MHz

2.048

MHz

32.768

MHz

8 kHz32 MHz

Selectable

8380_001

Distinguishing Features

Four T1/E1 short haul line interfaces
in a single chip

On-chip CLAD /system synchronizer

Digital (crystal-less) jitter attenuators
selectable for transmitter/receiver on
each line interface

Meets AT&T pub 62411 jitter specs

Meets ITU G.703, ETS 300 011
(PSTNX) Connections

AMI/B8ZS/HDB3 line codes

Host serial port or hardware only
control modes

On-chip receive clock recovery

Common transformers for 120/75

E1 and 100

Low-power 3.3 V power supply

Transmitter performance monitor

Compatible with latest ANSI, ITU-T,
and ETSI standards

128-pin MQFP package

Remote and local loopbacks

Applications

SONET/SDH multiplexers

T3 and E3/E4 (PDH) multiplexers

ATM multiplexers

Voice compression and voice
processing equipment

WAN routers and bridges

Digital loop carrier terminals (DLC)

HDSL terminal units

Remote concentrators

Central office equipment

PBXs and rural switches

PCM/voice channel banks

Digital access and cross-connect
systems (DACS)

N8380DSA

Conexant

Advance Information

Information provided by Conexant Systems, Inc. (Conexant) is believed to be accurate and reliable. However, no responsibility is
assumed by Conexant for its use, nor any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent rights of Conexant other than for circuitry embodied in Conexant
products. Conexant reserves the right to change circuitry at any time without notice. This document is subject to change without
notice.

Conexant and "What's Next in Communications Technologies" are trademarks of Conexant Systems, Inc.

Product names or services listed in this publication are for identification purposes only, and may be trademarks or registered
trademarks of their respective companies. All other marks mentioned herein are the property of their respective holders.

Reader Response: To improve the quality of our publications, we welcome your feedback. Please send comments or
suggestions via e-mail to

Conexant Reader Response@conexant.com

. Sorry, we can't answer your technical

questions at this address. Please contact your local Conexant

sales office

or local field applications engineer if you

have technical questions.

Ordering Information

Revision History

Model Number

Package

Operating Temperature

CN8380EPF

128-pin MQFP

40 °C to +85 °C

CN8398EVM

BT00D660001

Revision

Level

Date

Description

Advance

April 26, 1999

Created

N8380DSA

Conexant

Advance Information

Detailed Feature Summary

Interface Compatibility

T1.1021993

G.703 at 1.544 or 2.048 Mbps

ITU-T Recommendation I.431

Receive Line Interface

External Termination

Equalizer compensation for 20 dB
bridged monitor levels

+ 3 dB to 12 dB receiver sensitivity

Transmit Line Interface

Pulse shapes for 0655 ft., in 133 ft.
steps (T1 DSX1)

External termination for improved
return loss

Line driver enable/disable for
protection switching

Output short circuit protection (for
BABT applications)

Jitter Attenuator Elastic Store

Receive or transmit direction

8-, 16-, 32-, 64-, or 128-bit depth

Automatic and manual centering

Line Codes

Bipolar alternate mark inversion line
coding

Optional zero code suppression:
Independent transmit and receive
T1: B8ZS
E1: HDB3

Loopbacks

Remote loopback towards line
With or without JAT
Retains BPV transparency

Local loopback towards system
Analog line loopback
Local digital loopback

Simultaneous local and remote line
loopbacks

Clock Rate Adapter

Outputs jitter attenuated line rate
clock
CLK1544 = 1544 k (T1)
CLK2048 = 2048 k (E1)

CLAD output supports 14 output
clock frequencies: 8 kHz to
32,768 kHz

Programmable input timing
reference:
Receive recovered clock from any

channel

Internal clock (REFCKI)
CLADI

Subrate CLADI timing reference:
Line rate

, N = 0 to 7

References as low as 8 kHz

Host Serial Interface

Compatible with existing framers

Compatible with microprocessor
serial ports

Bit rates up to 8 Mbps

In-Service Performance Monitoring

Transmit alarm detectors:
Loss of Transmit Clock (TLOC)
Transmit Short Circuit (TSHORT)

Receive alarm detectors:
Loss of Signal (RLOS)
Loss of Analog Input (RALOS)
Bipolar/Line Code Violations

Automatic and on-demand transmit
alarms:
AIS following TLOC
Automatic AIS clock switching

CN8398EVM Octal T1/E1 Evaluation Module

Contact a Conexant representative for EVM availability and price.

CN8380 Quad T1/E1 LIU

CN8398 Octal T1/E1 Framer

Local PCM Highway (i.e., 2 @ 8192 kbps)

Microprocessor

Control

Eight RJ48C T1 or E1 Line Connections

8380_002

N8380DSA

Conexant

Advance Information

Table of Contents

List of Figures

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix

List of Tables

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x i

1.0 Pin Descriptions

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

2.0 Circuit Description

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.1 Overview

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.2 Configuration and Control

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.2.1 Hardware Mode

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.2.2 Host Mode

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.2.3 Host Serial Control Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.2.4 Reset

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.2.4.1 Power-on Reset

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.2.4.2 Hard Reset

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.2.4.3 Soft Reset

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.3 Receiver

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.3.1 Data Recovery

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.3.1.1 Raw Receive Mode

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.3.1.2 Sensitivity

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.3.1.3 Bridge Mode

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.3.1.4 Loss Of Signal Detector

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.3.2 Clock Recovery

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.3.2.1 Phase Lock Loop

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.3.2.2 Jitter Tolerance

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.3.3 Receive Jitter Attenuator

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.3.4 RZCS Decoder

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.3.5 Receive Digital Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.3.5.1 Bipolar Mode

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.3.5.2 Unipolar Mode

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

Table of Contents

CN8380

Quad T1/E1 Line Interface

Conexant

N8380DSA

Advance Information

2.4

Transmitter

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.4.1

Transmit Digital Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.4.1.1

Bipolar Mode

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.4.1.2

Unipolar Mode

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2.4.2

TZCS Encoder

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2.4.3

Transmit Jitter Attenuator

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2.4.4

All 1s AIS Generator

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2.4.5

Pulse Shaper

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2.4.6

Driver

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2.4.6.1

Transmit Termination Options

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2.4.6.2

Output Disable

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

2.4.7

Transmitter Output Monitoring

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2.4.7.1

Short Circuit Detect

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2.4.7.2

Driver Performance Monitor

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2.5

Loopbacks

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.5.1

Local Analog Loopback

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.5.2

Local Digital Loopback

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.5.3

Remote Line Loopback

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

2.6

Jitter Attenuator

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

2.7

Clock Rate Adapter

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25

2.7.1

Inputs

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26

2.7.2

Outputs

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26

2.7.3

Configuration Options

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26

2.8

Test Access Port (JTAG)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29

2.8.1

Instructions

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29

2.8.2

Device Identification Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29

3.0

Registers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1

Address Map

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.2

Global Control and Status Registers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

00--Device Identification (DID)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

01--Global Configuration (GCR)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

02--CLAD Configuration (CLAD_CR)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

03--CLAD Frequency Select (CSEL)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

04--CLAD Phase Detector Scale Factor (CPHASE)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

05--CLAD Test (CTEST)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

06--CLAD Status (CSTAT)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

07--(FREG)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

08--(TESTA1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

09--(TESTA2)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

0A--(FUSE_CH1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

0B--(FUSE_CH2)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

0C--(FUSE_CH3)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

0D--(FUSE_CH4)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

0E--(FUSE_RES)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

0F--(TESTD)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

CN8380

Table of Contents

Quad T1/E1 Line Interface

N8380DSA

Conexant

vii

Advance Information

3.3

Per Channel Registers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

10, 20, 30, 40--Jitter Attenuator Configuration (JAT_CR)

. . . . . . . . . . . . . . . . . . . . . . . 3-10

11, 21, 31, 41--Receiver Configuration (RLIU_CR)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

12, 22, 32, 42 --Transmitter Configuration (TLIU_CR)

. . . . . . . . . . . . . . . . . . . . . . . . . 3-12

13, 23, 33, 43--LIU Control (LIU_CTL)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

15, 25, 35, 45--Alarm Status (ALARM)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15

16, 26, 36, 46--Interrupt Status Register (ISR)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

17, 27, 37, 47--Interrupt Enable Register (IER)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

3.4

Transmitter Shape Registers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17

18 - 1F--Transmit PULSE Shape CONFIGURATION (SHAPE1)

. . . . . . . . . . . . . . . . . . . . 3-17

28 - 2F--Transmit PULSE Shape CONFIGURATION (SHAPE2)

. . . . . . . . . . . . . . . . . . . . 3-17

38 - 3F--Transmit PULSE Shape CONFIGURATION (SHAPE3)

. . . . . . . . . . . . . . . . . . . . 3-17

48 - 4F--Transmit PULSE Shape CONFIGURATION (SHAPE4)

. . . . . . . . . . . . . . . . . . . . 3-17

50--(TESTA3)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17

51--(TESTA4)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

4.0

Electrical/Mechanical Specifications

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1

Absolute Maximum Ratings

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.2

Recommended Operating Conditions

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

4.3

DC Characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.4

Performance Characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.5

AC Characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

4.6

Packaging

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13

Appendix A: Applicable Standards

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

Appendix B: External Component Specifications

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

Appendix C: Acronym List

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1

CN8380

List of Figures

Quad T1/E1 Line Interface

N8380DSA

Conexant ix

Advance Information

List of Figures

Figure 1-1. CN8380 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Figure 1-2. CN8380 Logic Diagram (Host Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

Figure 1-3. CN8380 Logic Diagram (Hardware Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

Figure 2-1. Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Figure 2-2. Host Serial Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

Figure 2-3. Receiver Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Figure 2-4. Raw Mode Receiver Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

Figure 2-5. Transmitter Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Figure 2-6. Transmit Pulse Shape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

Figure 2-7. Transmit Termination Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

Figure 2-8. Receiver Input Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
Figure 2-9. Typical JAT Transfer Characteristics with Various JAT Sizes . . . . . . . . . . . . . . . . . . . . . . 2-24

Figure 2-10. CLAD Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25

Figure 4-1. XOE Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Figure 4-2. RESET Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

Figure 4-3. CLAD Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

Figure 4-4. Receiver Signals Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Figure 4-5. Transmitter Signals Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

Figure 4-6. Host Serial Port Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10

Figure 4-7. Host Serial Port Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Figure 4-8. Host Serial Port Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11

Figure 4-9. JTAG Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

Figure 4-10. 128-Pin MQFP Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Figure B-1. Minimum Hardware Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2

CN8380

List of Tables

Quad T1/E1 Line Interface

N8380DSA

Conexant

Advance Information

List of Tables

Table 1-1. Hardware Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Table 2-1. Line Compatible Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

Table 2-2. Transmitter Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

Table 2-3. Transmit Pulse Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
Table 2-4. Transmit Termination Option A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

Table 2-5. Transmit Termination Option B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

Table 2-6. Transmit Termination Option C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Table 2-7. Transmit Termination Option D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

Table 2-8. Transmit Termination Option E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

Table 2-9. Loopback Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

Table 2-10. CLAD Outputs and Frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
Table 2-11. CLAD Reference Frequencies and Configuration Examples . . . . . . . . . . . . . . . . . . . . . . . . . 2-27

Table 2-12. Sample Alternate Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28

Table 2-13. JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
Table 2-14. Device Identification JTAG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29

Table 3-1. Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Table 3-2. Transmitter Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Table 4-1. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

Table 4-2. Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

Table 4-3. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Table 4-4. Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

Table 4-5. XOE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

Table 4-6. RESET Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Table 4-7. CLAD Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

Table 4-8. Receiver Signals Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

Table 4-9. Transmitter Signals Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Table 4-10. Host Serial Port Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10

Table 4-11. JTAG Interface Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

Table A-1. Applicable Standards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
Table B-1. Transformer Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

Table B-2. REFCKI (10 MHz) Crystal Oscillator Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

1.0 Pin Descriptions

CN8380

Quad T1/E1 Line Interface

1-2

Conexant

N8380DSA

Advance Information

Figure 1-1. CN8380 Pinout Diagram

CN8380

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

100

101

102

104

103

128-Pin MQFP

RTIP [1]

RRING [1]

XTIP [1]

XOE [1]

XRING [1]

GNDT [1]

VAAT [1]

RAWMD [1]

XOE [2]

XTIP [2]

XRING [2]

GNDT [2]

VAAT [2]

RTIP [2]

RRING [2]

RAWMD [2]

XOE [3]

XTIP [3]

XRING [3]

GNDT [3]

VAAT [3]

RTIP [3]

RAWMD [3]

RRING [3]

XOE [4]

XTIP [4]

XRING [4]

GNDT [4]

VAAT [4]

RTIP [4]

RAWMD [4]

RRING [4]

VAAR

GNDR

GND

VAA

TRST

CLADO

CLADI

VAACL

GNDCL

REFCKI

VSS

VDD

CLK32

CLK1544
CLK2048

VSS

VDD

RNEGO/BPV [1]

RPOSO/RDATO [1]

RCKO [1]

TNEGI [1]

TPOSI/TDATI [1]

TCLK [1]

RNEGO/BPV [2]

RPOSO/RDATO [2]

RCKO [2]

TNEGI [2]

TPOSI/TDATI [2]

TCLK [2]

RNEGO/BPV [3]

RPOSO/RDATO [3]

RCKO [3]

TNEGI [3]

TPOSI/TDATI [3]

TCLK [3]

RNEGO/BPV [4]

RPOSO/RDATO [4]

RCKO [4]

TNEGI [4]

TPOSI/TDATI [4]

TCLK [4]

VDD

VSS

TDO

TDI

TMS

TCK

VGG

RLOS [1]

RLOS [2]

RLOS [3]

RLOS [4]

VSS

VDD

UNIPOLAR

TAIS [1]

TAIS [2]

TAIS [3]

TAIS [4]

LLOOP [1]

LLOOP [2]

LLOOP [3]

LLOOP [4]

RLOOP [1]

RLOOP [2]

RLOOP [3]

RLOOP [4]

EACKI

TACKI

JATERR [4]

JATERR [3]

JATERR [2]

JATERR [1] / SDO

JDIR / SCLK

JSEL(2) / SDI

JSEL(1) / CS

JSEL(0)

IRQ

RESET

HTERM

ZCS

VDD

VSS

CLK_POL

N.C.

PTS(2)

PTS(1)

PTS(0)

8380_003

LEGEND:

[#] - Port Number
(#) - Bit Number

CN8380

1.0 Pin Descriptions

Quad T1/E1 Line Interface

N8380DSA

Conexant

1-3

Advance Information

Figure 1-2. CN8380 Logic Diagram (Host Mode)

H M

C S

RLOOP[1:4]

LLOOP[1:4]

I R Q

Interrupt Request

Hardware/Host Mode

R e m o t e L o o p b a c k

Local Loopback

Serial Chip Select

R E S E T

Hardware Reset

Hardware

Control

Interface

SDI

Serial Clock In

S C L K

S D O

Serial Data Out

Serial Port

Interface

(SERIO)

TCLK[1:4]

TPOSI[1:4]

TNEGI[1:4]

1544 KHz All Ones Clock

2048 KHz All Ones Clock

Transmit Clock

Transmit Positive Rail

Transmit Negative Rail

R N E G O [ 1 : 4 ]

Receive Negative Rail

RCKO[1:4]

Receive Clock

R P O S O [ 1 : 4 ]

Receive Positive Rail

Transmitter

(XMTR)

Receiver

(RCVR)

C L A D I

Clock Rate

Adapter (CLAD)

CLAD Input

C L K 3 2

32.768 MHz Clock Out

C L K 1 5 4 4

C L K 2 0 4 8

E1 Line Rate Clock Out

C L A D O

CLAD Output

T D O

Test Data Out

T C K

Test Clock In

T M S

TDI

T R S T

Test Mode Select

Test Data In

Test Reset In

I = Input, O = Output

PIO = Programmable I/O

Boundary Scan

(JTAG)

Receive Tip

Receive Ring

XRING[1:4]

Transmit Ring

XTIP[1:4]

Transmit Tip

RTIP[1:4]

RRING[1:4]

T1 Line Rate Clock Out

T A C K I

E A C K I

Transmit Output Enable

Transmit All Ones

TAIS[1:4]

R E F C K I

Reference Clock

RLOS[1:4]

Receive Loss of Signal Status

Serial Data In

XOE[1:4]

Host Mode

PIO

RLOOP[1:4]

LLOOP[1:4]

IRQ

Interrupt Request

Hardware/Host Mode

Remote Loopback

Local Loopback

Serial Chip Select

RESET

Hardware Reset

Hardware

Control

Interface

SDI

Serial Clock In

SCLK

SDO

Serial Port

Interface

(SERIO)

TCLK[1:4]

TPOSI[1:4]
TNEGI[1:4]

1544 kHz All 1s Clock
2048 kHz All 1s Clock

Transmit Clock

Transmit Positive Rail

Transmit Negative Rail

RNEGO[1:4]

Receive Negative Rail

RCKO[1:4]

RPOSO[1:4]

Receive Positive Rail

Transmitter

(XMTR)

Receiver

(RCVR)

CLADI

Clock Rate

Adapter (CLAD)

CLAD Input

CLK32

32.768 MHz Clock Out

CLK1544

CLK2048

E1 Line Rate Clock Out

CLADO

CLAD Output

TDO

Test Data Out

TCK

Test Clock In

TMS

TDI

TRST

Test Mode Select

Test Data In

Test Reset In

I = Input, O = Output

PIO = Programmable I/O

Boundary Scan

(JTAG)

Receive Tip

Receive Ring

XRING[1:4]

Transmit Ring

XTIP[1:4]

RTIP[1:4]

RRING[1:4]

T1 Line Rate Clock Out

TACKI

EACKI

Transmit Output Enable

Transmit All 1s

REFCKI

Reference Clock

RLOS[1:4]

Receive Loss of Signal Status

Serial Data In

XOE[1:4]

Host Mode

PIO

TAIS[1:4]

Serial Data Out

Receive Clock

Transmit Tip

8380_004

1.0 Pin Descriptions

CN8380

Quad T1/E1 Line Interface

1-4

Conexant

N8380DSA

Advance Information

Figure 1-3. CN8380 Logic Diagram (Hardware Mode)

JSEL(2:0)

CLK_POL

UNIPOLAR

JDIR

RLOOP[1:4]

LLOOP[1:4]

IRQ

JATERR[1:4]

Interrupt Request

Jitter Attenuator Error Status

Jitter Attenuator Size

Hardware/Host Mode

Unipolar/Bipolar

Clock Polarity

Jitter Attenuator Path

Remote Loopback

Zero Code Suppression

Local Loopback

RESET

Hardware Reset

RAWMD[1:4]

Raw Mode Select

Hardware

Control

Interface

TCLK[1:4]

TPOSI[1:4]
TNEGI[1:4]

1544 kHz All 1s Clock

2048 kHz All 1s Clock

Transmit Clock

Transmit Positive Rail

Transmit Negative Rail

RNEGO[1:4]

Receive Negative Rail

Receive Clock

RPOSO[1:4]

Receive Positive Rail

Transmitter

(XMTR)

Receiver

(RCVR)

CLADI

Clock Rate

Adapter (CLAD)

CLAD Input

CLK32

32.768 MHz Clock Out

CLK1544

CLK2048

E1 Line Rate Clock Out

CLADO

8 KHz Clock Out

TDO

Test Data Out

TCK

Test Clock In

TMS

TDI

TRST

Test Mode Select

Test Data In

Test Reset In

I = Input, O = Output

PIO = Programmable I/O

Boundary Scan

(JTAG)

HTERM

Transmitter Termination

Receive Tip

Receive Ring

XRING[1:4]

Transmit Ring

Transmit Tip

RTIP[1:4]

RRING[1:4]

T1 Line Rate Clock Out

TACKI

EACKI

Transmit Output Enable

Transmit All 1s

REFCKI

Reference Clock

RLOS[1:4]

Receive Loss of Signal Status

Transmit Pulse Template

ZCS

XOE[1:4]

Hardware Mode

VDD

PTS(2:0)

TAIS[1:4]

RCKO[1:4]

XTIP[1:4]

8380_005

CN8380

1.0 Pin Descriptions

Quad T1/E1 Line Interface

N8380DSA

Conexant

1-5

Advance Information

Table 1-1. Hardware Signal Definitions (1 of 5)

Pin Label

Signal Name

I/O

Definition

Receiver

RPOSO[1:4]

RDATO[1:4]

RX Positive Rail
(Bipolar Mode)

RX Data (Unipolar
Mode)

Line rate data output on the rising or falling edge of RCKO. The clock edge
is determined by the CLK_POL pin in Hardware Mode or the CLK_POL
register bit [RLIU_CR; addr n1] in Host Mode. In bipolar mode, a high
signal indicates receipt of a positive AMI pulse on RTIP/RRING inputs. In
unipolar mode, RPOSO is redefined as RDATO and a high signal indicates
either a positive or negative AMI pulse on RTIP/RRING inputs.
RPOSO/RDATO is three-stated during device reset.

RNEGO[1:4]

BPV[1:4]

RX Negative Rail
(Bipolar Mode)

Bipolar Violation
(Unipolar Mode)

Line rate data output on rising or falling edge of RCKO. The clock edge is
determined by the CLK_POL pin in Hardware Mode or the CLK_POL
register bit [RLIU_CR; addr n1] in Host Mode. In bipolar mode, a high
signal indicates receipt of a negative AMI pulse on RTIP/RRING inputs. In
unipolar mode, RNEGO is redefined as BPV, and a high signal indicates the
reception of a BPV which is not part of a ZCS code (B8ZS or HDB3).
RNEGO/BPV is three-stated during device reset.

RCKO[1:4]

RX Clock Output

Receive clock output. RCKO is the RPLL recovered line rate clock or jitter
attenuated clock output, based on the programmed jitter attenuator
selection. RCKO is three-stated during device reset.

RTIP[1:4]

RRING[1:4]

Receive Tip

Receive Ring

Differential AMI data inputs for direct connection to receive transformer.

Transmitter

TPOSI[1:4]

TDATI[1:4]

Tx Positive Rail
(Bipolar Mode)

Tx Data (Unipolar
Mode)

Positive rail, line rate data source for transmitted XTIP/XRING output
pulses. Data is sampled on the falling edge of TCLK. In bipolar mode, a
high on TPOSI causes a positive output pulse on XTIP/XRING; and a high
on TNEGI causes a negative output pulse. In unipolar mode, TPOSI is
redefined as TDATI and accepts single-rail NRZ data. TNEGI is not used in
unipolar mode.

TNEGI[1:4]

Tx Negative Rail
Input

Negative rail, line rate data input on TCLK falling edge. Refer to TPOSI
signal definition.

TCLK[1:4]

TX Clock Input

I/O

Transmit line rate clock. TCLK is the transmit clock for TPOSI and TNEGI
data inputs and for transmitter timing. Normally, TCLK is an input and
samples TPOSI/TNEGI on the falling edge. In Host Mode, TCLK can be
configured as an output to supply a line rate transmit clock from the
CLAD. The timing reference for the TCLK output (and CLAD) can be
selected from six sources.

TACKI

EACKI

T1 AIS Clock

E1 AIS Clock

Alternate T1 and E1 transmit clock used to transmit AIS (all 1s alarm
signal) when the primary transmit clock source, TCLK, fails. TACKI (T1) or
EACKI (E1) is either manually or automatically switched to replace TCLK
[LIU_CTL; addr n3]. Systems without an AIS clock should connect TACKI
and EACKI to ground.

XOE[1:4]

Transmit Output
Enable

A low signal enables XTIP and XRING output drivers. Otherwise outputs
are high impedance.

TAIS[1:4]

Transmit AIS
Alarm

In Hardware Mode, a low signal causes AIS (unframed all 1s)
transmission on XTIP/XRING outputs. In Host Mode, these pins can be
enabled or disabled [LIU_CTL; addr n3]. If disabled, they are not used and
may be left unconnected.

1.0 Pin Descriptions

CN8380

Quad T1/E1 Line Interface

1-6

Conexant

N8380DSA

Advance Information

XTIP[1:4]

XRING[1:4]

Transmit Tip

Transmit Ring

Complementary AMI transmitter line outputs for direct connection to
transmit transformer. Optionally, both outputs are three-stated when XOE
is high.

Clock Rate Adapter (CLAD)

CLADI

CLAD Input

CLAD input timing reference used to phase/frequency lock the CLAD
outputs to an input clock frequency selected in the range of 8 kHz to
32,768 kHz [CLAD_CR; addr 02]. Systems which do not use CLADI should
connect CLADI to ground. In Hardware Mode, the CLAD timing reference
automatically switches to internal free-run operation if clock edges are not
detected on CLADI pin.

REFCKI

Reference Clock

System must apply a 10 MHz ± 50 ppm (E1) or + 32 ppm (T1) clock signal
to act as the frequency reference for the internal numerically controlled
oscillator (NCO). REFCKI determines the frequency accuracy and stability
of the CLAD output clocks when operating in free-run mode [CLAD_CR;
addr 02]. REFCKI is the baseband reference for all CLAD/JAT functions
and is used internally to generate clocks of various frequency locked to a
selected receive or external clock.

Note: REFCKI is always required.

CLK32

32 MHz Clock
Output

Fixed rate 32.768 MHz clock output provided by the CLAD. May be used
by framers, such as the CN8398 octal T1/E1 framer, to provide system
timing reference.

CLK1544

T1 Clock Output

Fixed rate 1.544 MHz T1 line rate clock output provided by the CLAD. May
be used for TCLK or TACKI clock sources. This clock is locked to the
selected CLAD timing reference.

CLK2048

E1 Clock Output

Fixed rate 2.048 MHz E1 line rate clock output provided by the CLAD. May
be used for TCLK or EACKI clock sources. This clock is locked to the
selected CLAD timing reference.

CLADO

CLAD Output

In Hardware Mode, CLADO is a fixed rate 8 kHz clock output provided by
the CLAD. In Host Mode, CLADO may be configured to operate at one of
14 different clock frequencies [CSEL; addr 03] that include T1 or E1 line
rates. CLADO is typically programmed to supply system clocks that are
phase-locked to the selected receive or CLAD timing reference [CLAD_CR;
addr 02].

Hardware Control Signals

HM Hardware

Mode

A high on HM places the device in Hardware Mode, enabling all hardware
control pin functions. A low on HM places the device in Host Mode,
disabling some hardware-mode-only pin functions and enabling the serial
port signals on the dual function pins listed below. The serial port signals
allow serial host access to the device registers. Refer to the Host Serial
Control Signals section of this table.

JSEL(1) / CS JSEL(2) / SDI
JDIR / SCLK JATERR(1) / SDO

RAWMD[1:4]

Raw Mode

Low selects receiver Raw mode. Applicable only in Hardware Mode. In
Raw mode, RPOSO and RNEGO represent the data slicer outputs and
RCKO is the logical OR of RPOSO and RNEGO.

Table 1-1. Hardware Signal Definitions (2 of 5)

Pin Label

Signal Name

I/O

Definition

CN8380

1.0 Pin Descriptions

Quad T1/E1 Line Interface

N8380DSA

Conexant

1-7

Advance Information

RESET

Hardware Reset

Active low asynchronous hardware reset. A falling edge forces registers to
their default, power-up state. Output pins are forced to the high impedance
state while RESET is asserted. RESET is not mandatory at power-up
because an internal power-on reset circuit performs an identical function.

UNIPOLAR Unipolar

Mode

Select

Applicable only in Hardware Mode. A high signal on UNIPOLAR configures
all RPOSO outputs and TPOSI inputs to operate with unipolar, NRZ-
formatted data. In this mode, RNEGO reports non-ZCS BPVs and TNEGI is
not used. A low signal on UNIPOLAR configures all channels'
RPOSO/RNEGO and TPOSI/TNEGI interfaces to operate with bipolar,
dual-rail, NRZ formatted data.

ZCS

Zero Code
Suppression
Select

Applicable only in Hardware Mode. A high signal on ZCS enables the
transmit ZCS encoder and the receive ZCS decoder if unipolar mode is
enabled (UNIPOLAR = 1). In Bipolar Mode (UNIPOLAR = 0), the ZCS
encoder and decoder are disabled and ZCS is ignored.

CLK_POL

Rx Clock Polarity
Select

Applicable only in Hardware Mode. High sets RPOSO/RNEGO to be output
on the falling edge of RCKO. Low sets RPOSO/RNEGO to be output on the
rising edge of RCKO

PTS(2:0)

Transmit Pulse
Template Select

Applicable only in Hardware Mode. The PTS(2:0) control bus selects the
transmit pulse template and the line rate (T1 or E1) globally for all
channels. Refer to the description of HTERM in this table and to the
transmit pulse configurations in

Table 2-3

HTERM

Transmitter
Hardware
Termination

Applicable only in Hardware Mode. If an external transmit termination
resistor is used to meet return loss specifications; a transformer with a 1:2
turns ratio is used, and HTERM is set high to allow the transmitter to
compensate for the increased load. Refer to the Transmitter section of this
table and

Tables 2-4

through

2-8

for transmitter termination configuration

options.

IRQ

Interrupt Request

Active low, open drain output. In Host Mode, IRQ indicates one or more
pending interrupt requests ([ISR; addr n6] and [CSTAT; addr 06]). In
Hardware Mode, IRQ is the logical NOR of the four internal transmitter
driver performance monitor outputs.

JSEL(2:0)

Jitter Attenuator
Select

Applicable only in Hardware Mode. The JSEL and JDIR pins determine the
JAT configuration. JSEL(2:0) enables and selects the JAT depth as shown
in the table below. SDI/JSEL(2) and CS /JSEL(1) are dual function pins.

JSEL(2:0)

JAT Mode

000

8 bits

001

16 bits

010

32 bits

011

64 bits

100

128 bits

111

Disable JAT

JDIR

Jitter Attenuator
Direction

Applicable only in Hardware Mode. JDIR determines the path in which the
JAT is inserted. If JDIR is low, the JAT (if enabled) is placed in the receive
path; if high, the JAT (if enabled) is placed in the transmit path. Refer to
the description for JSEL(2:0). SCLK/JDIR is a dual function pin.

JATERR[1:4]

Jitter Attenuator
Error

Applicable only in Hardware Mode. A high on JATERR indicates an
overflow or underflow error in the jitter attenuator elastic store.
JATERR(1) / SDO is a dual function pin.

Table 1-1. Hardware Signal Definitions (3 of 5)

Pin Label

Signal Name

I/O

Definition

1.0 Pin Descriptions

CN8380

Quad T1/E1 Line Interface

1-8

Conexant

N8380DSA

Advance Information

RLOS [1:4]

Receive Loss of
Signal

RLOS is asserted low when 100 (T1) or 32 (E1) consecutive 0s (no
pulses) are received at the line interface or when the received signal level
is approximately 18 dB below nominal for at least 1 ms.

LLOOP [1:4]

RLOOP [1:4]

Local Loop

Remote Loop

These pins are always enabled in Hardware Mode and may be enabled or
disabled in Host Mode [LIU_CTL; addr n3]. A low on LLOOP initiates Local
Analog Loopback and a low on RLOOP initiates Remote Line Loopback.
Local Digital Loopback is initiated if both signals are asserted together.

Boundary Scan Signals (JTAG)

TDO

Test Data Output

Test data output per IEEE Std. 1149.1-1990. Three-state output used for
reading all serial configuration and test data from internal test logic.
Updated on the falling edge of TCK.

TDI

Test Data Input

Test data input per IEEE Std. 1149.1-1990. Used for loading all serial
instructions and data into internal test logic. Sampled on the rising edge of
TCK. TDI may be left unconnected if not used.

TMS

Test Mode Select

Active-low test mode select input per IEEE Std 1149.1-1990. Internally
pulled-up input signal used to control the test logic state machine.
Sampled on the rising edge of TCK. TMS may be left unconnected if not
used.

TCK

Test Clock

Test clock input per IEEE Std. 1149.1-1990. Used for all test interface and
internal test-logic operations. If not used, TCK should be pulled low.

TRST

Reset

Active low reset. TRST is pulled up internally and may be left unconnected
if not used.

Host Serial Control Signals

Chip Select

In Host Mode, CS is an active low input used to enable read/write access
with the host serial control port. CS /JSEL(1) is a dual function pin.

SDI

Serial Data In

In Host Mode, SDI is the serial data input for the host serial control port.
SDI/JSEL(2) is a dual function pin.

SDO

Serial Data Out

In Host Mode, SDO is the serial data output for the host serial control port.
SDO/JATERR[1] is a dual function pin.

SCLK

Serial Clock

In Host Mode, SCLK is the serial clock input for the host serial control
port. SCLK/JDIR is a dual function pin.

Power Supply Pins and No-Connect Pins

VAA

GND

Analog Supply

Ground

+3.3 V + 5%. Power supply pair for the analog circuitry.

VAAT[1:4]

GNDT[1:4]

Tx Driver Supply

Ground

+3.3 V + 5%. Power supply pairs for the transmitter driver circuitry. These
pin pairs should each be bypassed with a tantalum capacitor value of at
least 10

VAAR

GNDR

Rx Analog Supply

Ground

+ 3.3 V + 5%. Power supply pair for the analog receiver circuitry.

Table 1-1. Hardware Signal Definitions (4 of 5)

Pin Label

Signal Name

I/O

Definition

N8380DSA

Conexant

2-1

Advance Information

2.0 Circuit Description

2.1 Overview

The CN8380 includes four identical T1/E1 transceiver channels and a common
CLAD packaged in a 128-pin MQFP carrier. It is designed to interface T1/E1
framers, or to operate as a stand-alone line interface for synchronous or
plesiochronous mappers and multiplexers. The CN8380 is ideal for high line
density, short-haul applications that require low power (3.3 V supply) operation.
The configurable T1/E1 operation and common line interface design allows
support for single-board T1 and E1 designs.

Customer premise applications are supported by an on-chip JAT which

conforms to AT&T PUB 62411 and a selectable transmit pulse shape which
conforms to FCC Part 68, Pulse Option A. Selectable unipolar or bipolar interface
options and internal ZCS encoding and decoding are useful in many multiplexer
and mapper applications.

In the most simple configuration, Hardware Mode, the device is controlled

using dedicated hardware control pins. In this mode, the four channels are
configured globally to identical operating modes (T1, E1, transmit termination,
jitter attenuators, and so on). Each channel has device pins dedicated for channel
control and status, such as loopback controls, bipolar/unipolar interface modes,
and loss of signal indicators. Hardware Mode is selected by pulling the HM pin
high.

Host Mode allows control of the device through a 4-line serial port. In this

mode, all control and status functions can be accessed using internal registers.
Several additional features are also available in Host Mode, such as individual
channel operating mode configuration (T1/E1, transmit termination, jitter
attenuators, etc.) and programmable CLAD output frequencies. Host Mode is
selected by grounding the HM pin.

The CN8380 incorporates printed circuit board testability circuits in

compliance with IEEE Std P1149.1a1993, IEEE Standard Test Access Port and
BoundaryScan Architecture, commonly known as JTAG (Joint Test Action
Group). A detailed block diagram is displayed in

Figure 2-1

CN8380

2.0 Circuit Description

Quad T1/E1 Line Interface

2.2 Configuration and Control

N8380DSA

Conexant

2-3

Advance Information

2.2 Configuration and Control

2.2.1 Hardware Mode

In Hardware Mode, the device is controlled using dedicated hardware control
pins. In this mode, the four channels are configured globally to identical
operating modes (T1, E1, transmit termination, jitter attenuators, and so on). Each
channel has device pins dedicated for channel control and status, such as
loopback controls, bipolar/unipolar interface modes, and loss of signal indicators.
Refer to

Table 1-1, Hardware Signal Definitions

, for a description of all hardware

pins. Hardware Mode is selected by pulling the HM pin high.

2.2.2 Host Mode

In Host Mode, control of the device is through a four-line serial port. In this
mode, all control and status functions can be accessed using internal registers.
Refer to

Chapter 3.0, Registers

, for a description of each register. Host Mode is

selected by grounding the HM pin.

2.2.3 Host Serial Control Interface

The CN8380 serial interface is a four-wire, slave interface which allows a host
processor or framer with a compatible master serial port to communicate with the
LIU. This interface allows the host to control and query the CN8380 status by
writing and reading internal registers. One 8-bit register in the LIU can be written
via the SDI pin or read from the SDO pin at the clock rate determined by SCLK.
The serial port is enabled by pulling the chip select pin,

, active (low) during

the read and write cycles. Refer to

Figure 2-2

for host serial port signals.

The serial interface uses a 16-bit process for each write or read operation.

During a write or read operation, an 8-bit control word, consisting of a read/write
control bit (R/W) and a 7-bit LIU register address (A[6:0]) is transmitted to the
LIU using the SDI pin. If the operation is a write operation (R/W = 0), an 8-bit
register data (D[7:0]) byte follows the address on the SDI pin. This data is
received by the CN8380 and stored in the addressed register. If the operation is a
read operation (R/W = 1), the CN8380 outputs the addressed register contents on
the SDO pin. The signal input on SDI is sampled on the SCLK falling edge, and
data output on SDO changes on the SCLK rising edge.

2.0 Circuit Description

CN8380

2.2 Configuration and Control

Quad T1/E1 Line Interface

2-4

Conexant

N8380DSA

Advance Information

2.2.4 Reset

The CN8380 supports three reset methods: power-on reset, hard reset initiated by
the

RESET

pin, and soft reset initiated by the RESET bit in the Global

Configuration Register [GCR; addr 01]. In Host Mode, all three reset methods
produce the same results as listed below. In Hardware Mode, power-on reset and
hard reset produce the same results as shown; and soft reset is not applicable.
After RESET is complete, the following is true:

Figure 2-2. Host Serial Port Signals

SCLK

Read Timing

Write Timing

SDI

SDO

R/W

SCLK

SDI

SDO

R/W

Address/Control Byte

8380_007

Hardware Mode

Host Mode

Digital receiver outputs
(RPOSO[1:4] and RNEGO[1:4],
RCKO[1:4]) are enabled.

Digital receiver outputs (RPOSO[1:4]
and RNEGO[1:4], RCKO[1:4]) are
three-stated.

Transmitter line outputs (XTIP[1:4]
and XRING[1:4]) are enabled
(controlled by

XOE

Transmitter line outputs (XTIP[1:4]
and XRING[1:4]) are three-stated.

CN8380

2.0 Circuit Description

Quad T1/E1 Line Interface

2.2 Configuration and Control

N8380DSA

Conexant

2-5

Advance Information

2.2.4.1 Power-on Reset

An internal power-on reset process is initiated during power-up. When VDD has
reached approximately 2.6 V, the internal reset process begins and continues for
300 ms maximum if REFCLK is applied. If REFCLK is not present, the CN8380
remains in the reset state.

2.2.4.2 Hard Reset

Hard reset is initiated by bringing the

RESET

pin active (low). Once initiated, the

internal reset process completes in 5

s maximum. If the

RESET

pin is held active

continuously, the clock and data outputs and the

IRQ

pin remain three-stated. The

following output pins are forced to high impedance while

RESET

is held active:

2.2.4.3 Soft Reset

In Host Mode, soft reset is initiated by writing a one to the RESET bit in the
Global Configuration register [addr 01]. The RESET bit is self-clearing. Once
initiated, the internal reset process completes in 5

s maximum and the device

enters normal operation.

CLK1544, CLK2048, and CLADO
clock outputs are enabled.

CLK1544, CLK2048, and CLADO
clock outputs are three-stated.

Transmitter clocks, TCLK[1:4], are
configured as inputs.

The

IRQ

pin is enabled (controlled

by DPM).

The

IRQ

pin is three-stated.

All interrupt sources are disabled.

All configuration registers are set to
default values as listed in

Section 3.1,

Address Map

Hardware Mode

Host Mode

RPOSO[1:4]

CLADO

RNEGO[1:4]

TCLK[1:4]

RCKO[1:4]

IRQ

XTIP[1:4]

RLOS[1:4]

XRING[1:4:]

JATERR[1:4]

CLK1544

SDO

CLK2048

TDO

2.0 Circuit Description

CN8380

2.3 Receiver

Quad T1/E1 Line Interface

2-6

Conexant

N8380DSA

Advance Information

2.3 Receiver

Bipolar AMI pulses are input on the receiver input pins, RTIP[n] and RRING[n].
The receiver recovers clock and data from the AMI signal which has been
attenuated and distorted due to the line characteristics. The AMI pulses are
converted into bipolar or unipolar, NRZ data and output on RPOSO[n] and
RNEGO[n], along with the recovered clock on RCKO[n].

Figure 2-3

illustrates

the relationship between the AMI received signal, the recovered clock, and the
data outputs. This section discusses each receiver block from the line input to the
digital outputs.

2.3.1 Data Recovery

The receiver recovers data by normalizing the input signal with an automatic gain
control (AGC) circuit, removing distortion with an equalizer, and extracting the
data using a data slicer. The transfer function of the equalizer is adjusted based on
the average peak value of the input signal. The AGC maintains the equalizer's
average peak output level to a constant value. The data slicer compares the
equalizer output to a threshold value equal to 50% of the average peak equalizer
output level and produces both positive and negative pulse detect signals. The
data slicer outputs are re-timed using the recovered clock and routed to the RZCS
decoder (or to the JAT).

Figure 2-3. Receiver Signals

Internal

Equalized

Received

Signal

RCKO

Data Slicer Level
(50% of Peak)

RDATO

(Unipolar)

BPV

(Unipolar)

RPOSO

(Bipolar)

RNEGO

(Bipolar)

BPV

8380_008

CN8380

2.0 Circuit Description

Quad T1/E1 Line Interface

2.3 Receiver

N8380DSA

Conexant

2-7

Advance Information

2.3.1.1 Raw Receive

Mode

Optionally, the data slicer outputs, before re-timing, can be routed directly to the
RPOSO and RNEGO digital output pins. This option (raw receive mode) is
selected by asserting the

RAWMD

[n] pin in Hardware Mode or by asserting the

RAWMD register bit [RLIU_CR; addr n1] in Host Mode. In raw receive mode,
RCKO is replaced by the logical OR of the RPOSO and RNEGO output signals.

This mode is useful in applications which provide external clock and data

recovery.

Figure 2-4

illustrates the raw mode receiver signals.

2.3.1.2 Sensitivity

The receiver is capable of recovering signals with cable attenuation in the range of
+3 to 12 dB in E1 and T1 modes. The receiver is configured by setting register
bits appropriately in Host Mode or by setting configuration pins in Hardware
Mode. See

Table 2-1

for line compatible modes.

2.3.1.3 Bridge Mode

In Host Mode, the receiver allows interfacing to network test (MON) points
which are resistively attenuated with resisters in series with transmit and receive
Tip and Ring signals. The Bridge Monitor Level is 20 dB. Bridge operation is
enabled by setting register bit ATTEN [addr n1] to 1. In this mode, RALOS
detection and squelch operation are disabled.

Figure 2-4. Raw Mode Receiver Signals

Internal

Equalized

Received

Signal

Data Slicer Level
(50% of Peak)

RCKO

(RAW Mode)

RPOSO

(RAW Mode)

RNEGO

(RAW Mode)

BPV

8380_009

Table 2-1. Line Compatible Modes

Mode

Receiver Sensitivity

RALOS

Threshold

Squelch

Threshold

RLOS

Detect

+3 dB to 12 dB

18 dB

100 zeros

T1/E1 20 dB
Bridge

17 dB to 26 dB

100 zeros

+3 dB to 12 dB

18 dB

32 zeros

2.0 Circuit Description

CN8380

2.3 Receiver

Quad T1/E1 Line Interface

2-8

Conexant

N8380DSA

Advance Information

2.3.1.4 Loss Of Signal

Detector

The Receive Loss of Signal (RLOS) Detector monitors both consecutive 0s and
signal level. Receive Analog Loss Of Signal (RALOS) is declared when
RTIP/RRING input signal amplitude is a certain level (RALOS level) below the
nominal receive level for at least 1 ms (2 ms maximum). RALOS status is cleared
as soon as pulses above the RALOS level are detected.

In Host Mode, the received data can be replaced with all 0s (squelched) if the

receive level is also below the SQUELCH level. Squelch is enabled in register
RLIU_CR [addr n1]. In Host Mode, RALOS real time status is reported in the
ALARM [addr n5] register; and an interrupt status bit is available in the ISR [addr
n6] register. Also, RALOS is indicated on the

RLOS

[n] pin, which is the logical

NOR of the RLOS[n] status and RALOS[n] status.

RLOS is declared when 100 (T1) or 32 (E1) consecutive bits with no pulses

are detected. RLOS status is cleared when pulses are received with at least 12.5%
pulse density (during a period of 192 bits starting with the receipt of a pulse) and
where no occurrences of 100 or 32 consecutive bits with no pulses are detected.
In Host Mode, RLOS real time status is reported in the ALARM register [addr
n5]; and an interrupt status bit is available in the ISR register [addr n6]. Also,
RLOS is indicated by a 0 level on the

RLOS

[n] pin, which is the logical NOR of

the RLOS[n] status and RALOS[n] status.

2.3.2 Clock Recovery

2.3.2.1 Phase Lock Loop

The Receive Phase Lock Loop (RPLL) recovers the line rate clock from the data
slicer dual-rail outputs. The RPLL generates a recovered clock that tracks jitter in
the data and sustains the data-to-clock phase relationship in the absence of
incoming pulses. The RPLL is a digital PLL which adjusts its output phase in
1/16 unit interval (UI) steps. Consequently, the RPLL adds approximately 0.12 UI
peak-to-peak jitter to the recovered receive clock.

During loss of signal (RLOS or RALOS), the RPLL maintains an output clock

signal and smoothly transitions to a nominal line rate frequency determined by
the CLAD input reference (selected by CMUX [GCR; addr 01] or FREE
[CLAD_CR; addr 02]). If the CLAD reference is the recovered received clock
from a channel which has detected RLOS, the CLAD outputs and the recovered
received clock enter a "hold-over" state to maintain the average frequency that
was present just before the RLOS was detected.

2.3.2.2 Jitter Tolerance

Figure 2-8, Receiver Input Jitter Tolerance

, illustrates the receiver's jitter

tolerance for all jitter attenuator (JAT) configurations: JAT disabled and JAT
enabled in the receive path with each JAT elastic store size. The jitter tolerance of
the clock and data recovery circuit alone (not including the JAT) is illustrated by
the curve labeled with "JAT Disabled." The receiver meets jitter tolerance
specifications TR62411, G.823, and G.824. In addition, the receiver meets jitter
tolerance tests defined in ETS300 011: ISDN; Primary Rate User-Network
Interface Layer 1 Specification and Test Principles.

2.3.3 Receive Jitter Attenuator

The data slicer outputs can be routed to the JAT before going to the RZCS
decoder. The JAT attenuates clock and data jitter introduced by the line or added
by the clock recovery circuit. The JAT can be placed in the receive path or
transmit path, but not in both simultaneously. If the JAT is placed in the receive

CN8380

2.0 Circuit Description

Quad T1/E1 Line Interface

2.3 Receiver

N8380DSA

Conexant

2-9

Advance Information

path, RCKO is replaced with the jitter attenuated clock. The JAT performance is
discussed in

Section 2.6, Jitter Attenuator

In Host Mode, the JAT is configured for each channel independently and is

put in the receive path by setting JEN and JDIR register bits to 1 [JAT_CR; addr
n0]. In Hardware Mode, the JAT is configured for all channels globally using the
JSEL(2:0) and JDIR pins. Refer to

Chapter 1.0, Pin Descriptions

for details.

2.3.4 RZCS Decoder

The RZCS decoder decodes the dual-rail data from the data slicer or from the JAT.
In T1 mode, the RZCS decoder replaces received B8ZS codes with eight 0s. In E1
mode, HDB3 codes are replaced with four 0s. The B8ZS code is 000VB0VB and
the HDB3 code is X00V; where B is a normal AMI pulse, V is a bipolar violation,
and X is a don't-care.

ZCS decoding (and encoding) can be enabled only if the digital interface

mode is unipolar. In Host Mode, RZCS decoding (and TZCS encoding) is enabled
for each channel by setting the ZCS [RLIU_CR; addr n1] register bit to 1. In
Hardware Mode, ZCS encoding/decoding is controlled globally for all channels
by pulling the ZCS pin high. For the Hardware Mode pin definition, see

Table 1-1

2.3.5 Receive Digital Interface

The digital receiver outputs are provided on the RPOSO[n], RNEGO[n], and
RCKO[n] pins, where [n] is channel number 1 to 4. The receiver outputs can be
configured to operate in two modes: Bipolar NRZ format or unipolar NRZ
format. In both modes, RPOSO[n] and RNEGO[n] outputs are clocked by
RCKO[n], the recovered line rate clock, or the jitter attenuated clock if the JAT is
enabled in the receive path. RCKO[n] polarity is configurable by the CLK_POL
pin in Hardware Mode or register bit CLK_POL [RLIU_CR; addr n1] in Host
Mode. RPOSO[n], RNEGO[n], and RCKO[n] are three-stated during device
reset.

2.3.5.1 Bipolar Mode

In bipolar mode, RPOSO/RNEGO signals output received data in bipolar
dual-rail format, where a high level on RPOSO indicates receipt of a positive
AMI pulse, and a high level on RNEGO indicates receipt of a negative AMI pulse
on RTIP/RING inputs. In bipolar mode, the RZCS decoder is not available. In
Hardware Mode, bipolar operation is enabled globally for all channels by pulling
the UNIPOLAR pin low. In Host Mode, bipolar operation is enabled per channel
by writing a 0 to register bit UNIPOLAR [RLIU_CR; addr n1].

2.3.5.2 Unipolar Mode

In unipolar mode, RPOSO/RNEGO signals are replaced by RDATO/BPV signals.
AMI encoded received data is decoded and output on RDATO in NRZ format,
and BPV indicates that the currently received bit is a bipolar violation. If the
RZCS decoder is enabled, the BPV pin indicates only bipolar violations which are
not part of a ZCS code (B8ZS or HDB3). In Hardware Mode, unipolar operation
is enabled by pulling the UNIPOLAR pin high. In Host Mode, unipolar operation
is enabled by writing a 1 to register bit UNIPOLAR [RLIU_CR; addr n1].

2.0 Circuit Description

CN8380

2.4 Transmitter

Quad T1/E1 Line Interface

2-10

Conexant

N8380DSA

Advance Information

2.4 Transmitter

Bipolar or unipolar, NRZ digital transmit data are input on TPOSI and TNEGI
using the transmit clock TCLK. Data are converted into AMI pulses, shaped
according to required standards, and transmitted to the line.

Figure 2-5

illustrates

the relationship between the AMI transmitted signal, the transmit clock, and the
data inputs. This section discusses each transmitter block, from the digital inputs
to the line output.

2.4.1 Transmit Digital Interface

The digital transmitter inputs, TPOSI[n] and TNEGI[n], accept bipolar or
unipolar NRZ formatted data for transmission and are sampled by the falling edge
of TCLK[n], where [n] is channel number 1 to 4. TCLK[n] is the line rate
transmit clock and is normally supplied externally from a line rate source, but can
also be sourced internally (only in Host Mode) from the CLAD. If sourced
internally, TCLK[n] is configured as an output to provide the line rate clock to
external circuitry. TCLK[n] direction is configured globally for all channels by
writing to register bit TCLK_I/O [GCR; addr 01].

2.4.1.1 Bipolar Mode

In bipolar mode, TPOSI/TNEGI inputs accept bipolar dual-rail transmit data
where a high on TPOSI causes a positive output pulse and a high on TNEGI
causes a negative output pulse on XTIP/XRING. In this mode, the TZCS encoder
is not available. In Hardware Mode, bipolar operation is enabled globally for all
channels by pulling the UNIPOLAR pin low. In Host Mode, bipolar operation is

Figure 2-5. Transmitter Signals

TCLK

TDATI

(Unipolar)

TPOSI

(Bipolar)

TNEGI

(Bipolar)

XTIP,

XRING

Throughput
Delay

8380_010

CN8380

2.0 Circuit Description

Quad T1/E1 Line Interface

2.4 Transmitter

N8380DSA

Conexant

2-11

Advance Information

enabled per channel by writing a 0 to register bit UNIPOLAR [RLIU_CR;
addr n1].

2.4.1.2 Unipolar Mode

In unipolar mode, TPOSI is replaced with TDATI and accepts unipolar NRZ-
formatted transmit data. TNEGI is not used in this mode. A high on TDATI
causes an AMI pulse to be transmitted to the line. In this mode, the TZCS encoder
can be enabled to provide B8ZS or HDB3 zero code suppression. In Hardware
Mode, unipolar operation is enabled globally for all channels by pulling the
UNIPOLAR pin high. In Host Mode, unipolar operation is enabled per channel
by writing a 1 to register bit UNIPOLAR [RLIU_CR; addr n1].

2.4.2 TZCS Encoder

If enabled, the TZCS encoder encodes unipolar transmit data on TDATI with
B8ZS (T1) or HDB3 (E1) line coding. In T1 mode, eight consecutive 0s are
replaced with 000VB0VB; and in E1 mode, four consecutive 0s are replaced with
X00V; where B is a normal AMI pulse, V is a bipolar violation, and X is a Don't
Care. These are standard T1 and E1 line code options.

ZCS encoding (and decoding) can be enabled only if the digital interface

mode is unipolar. In Host Mode, TZCS encoding (and RZCS decoding) is enabled
for each channel by setting the ZCS [RLIU_CR; addr n1] register bit to 1. In
Hardware Mode, ZCS encoding/decoding is controlled globally for all channels
by pulling the ZCS pin high. For the Hardware Mode pin definition, refer to

Table 1-1

2.4.3 Transmit Jitter Attenuator

Transmit data from the TZCS encoder can be routed to the JAT before going to
the AIS Generator. The JAT attenuates clock and data jitter from the transmit
inputs or from the receiver if Remote Line Loopback (RLL) is active. The JAT
can be placed in the receive path or transmit path, but not both simultaneously. If
the JAT is placed in the transmit path, the jitter attenuated clock becomes the
transmit clock for downstream circuits.

In Host Mode, the JAT is configured for each channel independently and is

put in the transmit path by setting the JEN register bit to 1 and the JDIR register
bit to 0 [JAT_CR; addr n0]. In Hardware Mode, the JAT is configured for all
channels globally using the JSEL(2:0) and JDIR pins. For pin definitions, refer to

Chapter 1.0, Pin Descriptions

; for JAT transfer characteristics, refer to

Figure 2-9

;

and for more information on loopbacks, refer to

Section 2.5, Loopbacks

2.4.4 All 1s AIS Generator

The transmit data can be replaced with unframed all 1s for transmitting the alarm
indication signal (AIS). This includes replacing data supplied from
TPOSI[n]/TNEGI[n] pins and from the receiver during RLL. AIS transmission
does not affect transmit data that is looped back to the receiver during Local
Digital Loopback (LDL). This allows LDL to be active simultaneously with the
transmission of AIS. AIS is used to maintain a valid signal on the line and to
inform downstream equipment that the transmit data source has been lost. AIS
transmission can be done manually or automatically when loss of transmit clock
is detected. A clock monitor circuit allows manual or automatic switching of the
transmit clock to an alternate AIS clock.

2.0 Circuit Description

CN8380

2.4 Transmitter

Quad T1/E1 Line Interface

2-12

Conexant

N8380DSA

Advance Information

In Hardware Mode, AIS can be controlled only manually by pulling the

TAIS

[n] hardware pin low. If TCLK[n] is present, then it is used to transmit AIS.

If TCLK[n] is not present (for two clock periods), the alternate AIS clock on
either TACKI (T1 Mode) or EACKI (E1 Mode) is used. The AIS transmit clock
switches back to TCLK[n] when the TCLK[n] signal returns.

In Host Mode, AIS can be transmitted using the

TAIS

[n] hardware pins or the

TAIS register bit, or automatically by enabling the AUTO_AIS register bit. AIS
clock switching can be enabled by using the AISCLK register bit. Setting
AISCLK to 1 forces the use of the alternate AIS clock on either TACKI (T1
Mode) or EACKI (E1 Mode) pins when transmitting AIS. If AUTO_AIS is set
to 1, AIS is automatically transmitted when the clock monitor detects loss of
clock on TCLK[n]. When using automatic AIS transmission, the user should also
enable the AISCLK bit and provide an alternate clock source to insure that AIS
will be transmitted. CLAD output clocks CLK2048 and CLK1544 can be
connected externally to EACKI and TACKI alternate AIS clock inputs for this
purpose. Setting register bit TAIS_PE to 1 disables the TAIS register bit and
allows manual transmission of AIS using the

TAIS

[n] hardware pins. Refer to

LIU_CTL [addr n3] in

Chapter 3.0, Registers

, and to

Table 1-1, Hardware Signal

Definitions

If TAIS is activated when Remote Line Loopback is active, AIS is transmitted

using the received clock (or JCLK if the JAT is enabled in the receive direction).

Table 2-2

lists transmitter operating modes resulting from various configuration

settings and input conditions.

Table 2-2. Transmitter Operating Modes

Configuration and Input Status

Transmitter Mode

RLOOP

(W/LLOOP=0)

TLOC

TAIS

AUTO_AIS

AISCLK

Transmit

Data

Transmit

Clock

Tx Data

TCLK

AIS

TCLK

AIS

TACKI/EACKI

Tx Data

TCLK

AIS TCLK

AIS TACKI/EACKI

Rx Data

RCLK

AIS

RCLK

NOTE(S):

X is don't-care.

CN8380

2.0 Circuit Description

Quad T1/E1 Line Interface

2.4 Transmitter

N8380DSA

Conexant

2-13

Advance Information

2.4.5 Pulse Shaper

All transmit pulse shaping to meet E1 and T1 transmission standards is done
internally, eliminating the need for external shaping circuitry. The pulse shape
block receives bipolar NRZ transmit data, produces a set of eight 5-bit values
which define the pulse shape, and converts the shape values into an analog pulse
using a DAC.

Table 2-3

lists the transmit pulse template selections and

applications.

In Hardware Mode, standard pulse templates are selected globally for all

channels using hardware pins PTS(2:0). Refer to the

Chapter 1.0, Pin

Descriptions

, and

Table 1-1, Hardware Signal Definitions

Table 2-3. Transmit Pulse Configurations

Application

Line Rate

Line Length

Hardware Mode

Configuration

PTS(2:0)

Host Mode Configuration

[TLIU_CR; addr n2]

PULSE(2:0)

DSX-1
T1.102
CB119
100

Twisted Pair

0133 ft.

000

133266 ft.

001

266399 ft.

010

399533 ft.

011

533655 ft.

100

ITUT G.703
75

Coaxial Cable

101

ITUT G.703
120

Twisted Pair

110

FCC Part 68 Opt A
I.431
100

Twisted Pair

111

2.0 Circuit Description

CN8380

2.4 Transmitter

Quad T1/E1 Line Interface

2-14

Conexant

N8380DSA

Advance Information

In Host Mode, standard pulse templates are selected per channel by writing to

register bits PULSE(2:0) [TLIU_CR; addr n2]. If desired, custom pulse shapes
can be programmed for each channel using the SHAPEn [addr n8 nF] registers
and the PPT [TLIU_CR; addr n2] register bit. The data written into the SHAPEn
registers is 5-bit magnitude only. The first four code values of the pulse define the
first half of the symbol, and the last four values define the last half of the symbol.
The last half symbol polarity is always forced to be opposite from the first half
polarity.

Figure 2-6

illustrates the shaped transmit signals.

2.4.6 Driver

The transmit DAC converts digitally shaped AMI pulses into analog bipolar
signals. The line driver provides a high impedance, current drive for the transmit
DAC and outputs transmit signals to the XTIP[n] and XRING[n] output pins. The
high impedance driver allows line impedance matching using external parallel
resistors to meet return loss requirements. In applications which require surge
protection, pulse amplitude compensation is provided if protection resistors are
needed in series with XTIP[n] and XRING[n]. When a shorted line is detected,
transmit monitor and protection circuits reduce the output current level to less
than 50 mA peak. The standard transmit transformer for the CN8380 has a turns
ratio of 1:2 (chip-side: line-side). To minimize power consumption, an alternate
1:1.36 turns ratio transformer can be used in an unterminated configuration.

2.4.6.1 Transmit

Termination Options

Various transmitter termination options are available to meet almost any interface
requirement.

Figure 2-7

illustrates the location of the transmit termination

components. In this figure, Ct is a smoothing capacitor across XTIP and XRING.
The recommended value for Ct is 150 pF. If other components are also connected
to XTIP/XRING, such as surge protection diodes, Ct's value should be adjusted to
maintain a total parallel capacitance of approximately 150 pF.

Rt is a parallel termination resistor selected to provide the required transmitter

return loss, typically 18 dB. If an application does not have a return loss
requirement, Rt can be omitted in order to reduce total power consumption.

Figure 2-6. Transmit Pulse Shape

TCLK

8 x TCLK

Digitized

AMI Pulses

Shape Data
Magnitude
(0x000x1F)

Positive Pulse

Negative Pulse

8380_011

CN8380

2.0 Circuit Description

Quad T1/E1 Line Interface

2.4 Transmitter

N8380DSA

Conexant

2-15

Advance Information

The standard transformer recommended has a turns ratio of 1:2. This turns

ratio is required if parallel termination (Rt) or series resistors (Rs) are desired.
The alternate transformer has a turns ratio of 1:1.36. This transformer can be used
only if all of the following are true:

Parallel termination (Rt) is not used.

Series resistors (Rs) are not used.

T1 DSX-1 transmit pulse is not used.

Refer to Option E in

Table 2-7

below. Transmitter power consumption is

reduced by approximately 30%, compared to the unterminated, standard
transformer configuration.

Resistors (Rs) in series with Tx TIP and Tx RING line connections are

sometimes used with surge protection circuits. Without compensation, the
addition of these resistors decreases the transmit pulse amplitude. The CN8380
provides an option in Host Mode to boost the output level if resistors are installed.
Compensation is optimized for the use of 5.6

Rs values. In Hardware Mode,

these resistors are required.

Tables 2-4

through

2-8

provide recommended termination component values

and CN8380 configuration information for all termination options supported. The
resulting return loss value is also listed. All five options are supported in Host
Mode, whereas only options C and D are supported in Hardware Mode.

Before selecting a termination option, refer to

Table 2-3, Transmit Pulse

Configurations

, to select an application mode. Then refer to the Transmit

Termination tables below to select a termination option.

Figure 2-7. Transmit Termination Components

CN8380

Tx TIP

Tx RING

XTIP

XRING

1:N

Transformer

8380_012

2.0 Circuit Description

CN8380

2.4 Transmitter

Quad T1/E1 Line Interface

2-16

Conexant

N8380DSA

Advance Information

Option A

Option A uses the standard 1:2 transformer, no series protection resistors (Rs),
and no parallel termination (Rt) for T1 applications. In E1 applications, Rt is
included because it is usually required to provide a minimal level of line
impedance matching.

Option B

Option B uses the standard 1:2 transformer and no series protection resistors (Rs).
A common parallel termination (Rt) for both T1 and E1 applications is included
to provide line impedance matching.

Table 2-4. Transmit Termination Option A

Application

Series Resistors

(Rs)

Parallel Termination

(Rt,

)

Return Loss

(dB)

T1--DSX-1

None

E1--75

None

126.4

E1--120

None

204.4

T1-- I.431

None

NOTE(S):

1. Standard Transformer (1:2 turns ratio)
2. Hardware Mode: HTERM=0
3. Host Mode: ALT_TR = 0, TERM = 0, T_BOOST = 0 [TLIU_CR; addr n2]

Table 2-5. Transmit Termination Option B

Application

Series Resistors

(Rs)

Parallel Termination

(Rt,

)

Return Loss

(dB)

T1--DSX-1

None

23.7

E1--75

None

23.7

E1--120

None

23.7

T1-- I.431

None

23.7

NOTE(S):

1. Standard Transformer (1:2 turns ratio)
2. Hardware Mode: Not applicable
3. Host Mode: ALT_TR = 0, TERM = 1, T_BOOST = 0 [TLIU_CR; addr n2]

CN8380

2.0 Circuit Description

Quad T1/E1 Line Interface

2.4 Transmitter

N8380DSA

Conexant

2-17

Advance Information

Option C

Option C uses the standard 1:2 transformer and no parallel termination (Rt) for
T1 applications. In E1 applications, Rt is included because it is usually required to
provide a minimal level of line impedance matching. Series protection resistors
(Rs) are included. Option C is available only in Host Mode.

Option D

Option D uses the standard 1:2 transformer. A common parallel termination (Rt)
for both T1 and E1 applications is included to provide line impedance matching.
Series protection resistors (Rs) are also included. Option D is available in both
Host Mode and Hardware Mode.

Table 2-6. Transmit Termination Option C

Application

Series Resistors

(Rs)

Parallel Termination

(Rt,

)

Return Loss

(dB)

T1--DSX-1

2 × 5.6

None

E1--75

2 × 5.6

114.8

E1--120

2 ×5.6

190.0

T1--I.431

2 × 5.6

None

NOTE(S):

1. Standard Transformer (1:2 turns ratio)
2. Hardware Mode: HTERM = 0
3. Host Mode: ALT_TR = 0, TERM = 0, T_BOOST = 1 [TLIU_CR; addr n2]

Table 2-7. Transmit Termination Option D

Application

Series Resistors

(Rs)

Parallel Termination

(Rt,

)

Return Loss

(dB)

T1--DSX-1

2 × 5.6

E1--75

2 × 5.6

E1--120

2 × 5.6

T1--I.431

2 × 5.6

NOTE(S):

1. Standard Transformer (1:2 turns ratio)
2. Hardware Mode: HTERM = 1
3. Host Mode: ALT_TR = 0, TERM = 1, T_BOOST = 1 [TLIU_CR; addr n2]

2.0 Circuit Description

CN8380

2.4 Transmitter

Quad T1/E1 Line Interface

2-18

Conexant

N8380DSA

Advance Information

Option E

Option E uses the alternate 1:1.36 transformer, no series protection resistors (Rs),
and no parallel termination (Rt) for T1 applications. In E1 applications, Rt is
included because it is usually required to provide a minimal level of line
impedance matching. Option E is available only in Host Mode and cannot be used
with DSX-1 applications.

2.4.6.2 Output Disable

The transmitter analog outputs, XTIP[n] and XRING[n], are enabled per channel
by pulling the

XOE

[n] pins low and are three-stated by pulling the

XOE

[n] pins

high. In Host Mode, the PDN [TLIU_CR; addr n2] register bit also controls the
XTIP[n] and XRING[n] outputs. A device RESET sets the PDN bits, thereby
disabling XTIP[n] and XRING[n]. User software must clear PDN to enable the
transmitter outputs.

In Hardware Mode, the transmitter outputs are disabled while

RESET

is held

active (low). When

RESET

is deactivated,

XOE

[n] controls the transmitter outputs.

If the transmit driver is disabled (

XOE

[n] = 1), the driver performance monitor

(DPM) is available for monitoring a transmit signal from an external source.
Refer to

Section 2.4.7.2, Driver Performance Monitor

Table 2-8. Transmit Termination Option E

Application

Series Resistors

(Rs)

Parallel Termination

(Rt,

)

Return Loss

(dB)

E1--75

None

68.1

E1--120

None

107.0

T1--I.431

None

NOTE(S):

1. Alternate transformer (1:1.36 turns ratio)
2. Hardware Mode: Not Applicable
3. Host Mode: ALT_TR = 1, TERM = 0, T_BOOST = 0 [TLIU_CR; addr n2]

CN8380

2.0 Circuit Description

Quad T1/E1 Line Interface

2.4 Transmitter

N8380DSA

Conexant

2-19

Advance Information

2.4.7 Transmitter Output Monitoring

2.4.7.1 Short Circuit

Detect

The transmitter output pulse is monitored and a short circuit is detected when the
amplitude falls below an internally determined threshold for approximately 64-bit
times. The short circuit state deactivates when the amplitude rises above a second
threshold for 64-bit times.

When a short is detected, the line driver current is reduced to approximately

50 mA peak, as measured on the line side of the transformer. Typically, this is
caused by a transmit cable short circuit or by a transmission line transient current
surge. In Host Mode, short circuit activation sets the TSHORT bit in the Alarm
Status register [ALARM; addr n5] and in the Interrupt Status Register [ISR; addr
n6]. No indication of short circuit is available in Hardware Mode.

2.4.7.2 Driver

Performance Monitor

The DPM monitors the line driver output signal for valid signaling activity. The
output signal is monitored for pulse level, invalid AMI coding, pulse density, and
stuck signals. In Host Mode, a DPM fault condition sets the TLOS bit in the
Alarm Status register [ALARM; addr n5] and in the Interrupt Status Register
[ISR; addr n6]. In Hardware Mode, the four internal DPM status indicators are
combined (logical NOR) and output on the

IRQ

pin.

If the transmit driver is disabled (

XOE

= 1), the DPM is available for

monitoring a transmit signal from an external source. In this mode, XTIP[n] and
XRING[n] are used as inputs and can be connected to the transmit outputs of
another CN8380 channel or device.

2.0 Circuit Description

CN8380

2.5 Loopbacks

Quad T1/E1 Line Interface

2-20

Conexant

N8380DSA

Advance Information

2.5 Loopbacks

Three per-channel loopbacks are provided for system diagnostic testing: Local
Analog Loopback, Local Digital Loopback, and Remote Line Loopback.
Loopbacks can be controlled by either hardware pins or internal register bits. For
hardware control, two dedicated pins--

LLOOP

and

RLOOP

--are provided. If

configured in Host Mode, register bits are provided for loopback control. In
addition, the

LLOOP

and

RLOOP

pins can be enabled by register bits so that

loopbacks can be controlled by the hardware pins even in Host Mode. Loopback
controls are detailed in

Table 2-9

. Refer also to register LIU_CTL [addr n3] in

Chapter 3.0, Registers

2.5.1 Local Analog Loopback

Local Analog Loopback (LAL) causes the transmit data and clock inputs
(TPOSI/TNEGI and TCLK) to be looped back to the receiver outputs
(RPOSO/RNEGO and RCKO). This loopback connects an internal copy of the
analog transmit signal (XTIP and XRING outputs) to the receiver input, so that
virtually all of the device circuitry can be tested. While LAL is active, transmit
data continues to be transmitted on XTIP and XRING, but RTIP and RRING
inputs are ignored. Applying a high on the

XOE

pin when Local Analog Loopback

is active disables the transmitter outputs and causes an RLOS.

2.5.2 Local Digital Loopback

Local Digital Loopback (LDL) causes the transmit data and clock inputs
(TPOSI/TNEGI and TCLK) to be looped back to the receiver outputs
(RPOSO/RNEGO and RCKO). This loopback includes the JAT (if enabled) but
does not include the line transmit and receive circuitry. Consequently, XTIP and
XRING transmitter outputs are unaffected, and receiver RTIP and RRING inputs
remain connected to the line to monitor for RLOS. Also, the AIS (all 1s)
generator is not included in the loopback path so that AIS can be transmitted
toward the line while simultaneously providing a local loopback.

Table 2-9. Loopback Control Pins

LLOOP

RLOOP

Loopback

None

Remote Line Loop

Local Analog Loop

Local Digital Loop

2.0 Circuit Description

CN8380

2.6 Jitter Attenuator

Quad T1/E1 Line Interface

2-22

Conexant

N8380DSA

Advance Information

2.6 Jitter Attenuator

The jitter attenuator (JAT) attenuates jitter in the receive or transmit path, but not
both simultaneously. The JAT path configuration and elastic store depth is
controlled by the JDIR and JSEL(2:0) pins in Hardware Mode or by the JEN,
JDIR, JCENTER, and JSIZE[2:0] bits in the Jitter Attenuator Configuration
register [JAT_CR; addr n0] in Host Mode. The JAT can also be completely
disabled.

The elastic store is configurable using the JSEL(2:0) pins or the JSIZE[2:0]

bits in the JAT_CR register. The elastic store sizes available are 8, 16, 32, 64, and
128 bits. The 32-bit elastic store depth is sufficient to meet jitter tolerance
requirements in all cases where the JAT cutoff frequency is 6 Hz or below, and
when the selected clock reference is frequency-locked. The larger elastic store
depths allow greater accumulated phase offsets. For example, the 128-bit depth
can tolerate up to

64 bits of accumulated phase offset. Because the elastic store

is a fixed size, it can overflow and under-run. If either of these conditions occurs,
a Jitter Attenuator Elastic Store Limit Error (JATERR) is reported. In Hardware
Mode, JATERR[n] pins are provided, and in Host Mode, the JERR bit in the
Interrupt Status Register [ISR; addr n6] is set.

The elastic store is a circular buffer with independent read and write pointers.

These pointers can be initialized manually using JCENTER in the JAT_CR
register. JCENTER resets the write pointer and forces the elastic store read
pointer to one half of the programmed JSIZE. Centering is automatic as a result of
a JATERR condition, so manually centering is not required.

The dejittered receiver recovered clock is output on the RCKO[n] pin if the

JAT is configured in the receive path. The receiver input clock and data jitter
tolerance and jitter transfer meet TR 62411-1990.

Figures 2-8

and

2-9

illustrate

jitter tolerance and JAT transfer characteristics.

CN8380

2.0 Circuit Description

Quad T1/E1 Line Interface

2.7 Clock Rate Adapter

N8380DSA

Conexant

2-25

Advance Information

2.7 Clock Rate Adapter

The CLAD uses an input clock reference at a particular frequency (8 kHz to
16,384 kHz) to synthesize output clocks at a different frequency (8 kHz to 16,384
kHz). The CLAD outputs are frequency-locked to the selected timing reference.
The CLAD can operate with input reference frequencies at multiples and
submultiples of T1 or E1 line rates. The CLAD block diagram is illustrated in

Figure 2-10

Figure 2-10. CLAD Block Diagram

Phase

Detector

NCO

[FREE]

÷ [VSCALE] Factor

÷ [RSCALE] Factor

CLADV

RCKO[1]

10 MHz

Loop
Filter

[LFGAIN]

Divider Chain

[VSEL]

[OSEL]

CLADO

CLK1544

CLK2048

CLK32

REFCKI

CLADI

RCKO[2]

RCKO[3]

RCKO[4]

[CMUX]

[CLK_OE]

Refer to the following registers:
Global Configuration; addr 01
CLAD Configuration; addr 02
CLAD Frequency Select; addr 03
CLAD Phase Detector Scale Factor; addr 04
CLAD Status; addr 06

Labels in brackets [ ] refer
to register bits.

32.768 MHz

2.048 MHz

1.544 MHz

Clock Rate Adapter (CLAD)

CLAD Control/

Status

[G_T1/E1N]

[CPD_IE]

[CPDERR]

[CPD_INT]

CLADR

Device I/O Pin

Clock

Monitor

8380_015

2.0 Circuit Description

CN8380

2.7 Clock Rate Adapter

Quad T1/E1 Line Interface

2-26

Conexant

N8380DSA

Advance Information

2.7.1 Inputs

In Hardware Mode, the CLAD input timing reference is normally taken from a
line rate (1,544 kHz--T1 or 2,048 kHz--E1) clock on the CLADI pin. The line
rate is determined globally for all channels by settings on the PTS(2:0) pins. The
CLAD can be set in free-run mode by removing the clock from CLADI (pull high
or low). If clock edges are not present on CLADI, an internal clock monitor
automatically switches the timing reference to use the 10 MHz, REFCKI
reference. When clock edges are sensed on CLADI, the reference is switched
back to CLADI.

In Host Mode, the CLAD input timing reference can be selected from six

sources. The source can be the received recovered clock (or jitter attenuated
clock) output (RCKO[n]) from any of the four channels, the CLADI input pin, or
the 10 MHz, REFCKI input (free-run mode). The CLAD reference is configured
by writing to the CMUX[2:0] bits in the Global Control Register [GCR; addr 01].
Free-run mode is selected by writing 1 to the FREE bit in the CLAD
Configuration Register [CLAD_CR; addr 02].

2.7.2 Outputs

Four CLAD output pins are provided: CLADO, CLK32, CLK1544, and
CLK2048. In Hardware Mode, the CLADO output provides only a fixed 8 kHz
clock. In Host Mode, the CLADO frequency is programmable.

Table 2-10

lists

the CLAD outputs and frequencies. For pin definitions, refer to

Table 1-1

2.7.3 Configuration Options

CLAD modes are selected using the CLAD Configuration Register [CLAD_CR;
addr 02]; the CLAD Frequency Select [CSEL; addr 03]; and the CLAD Phase
Detector Scale Factor [CPHASE; addr 04]. The CLAD reference can be any of 41
possible frequencies, as listed in

Table 2-11

Table 2-10. CLAD Outputs and Frequencies

CLAD Output

Frequency

CLADO

Host Mode--Programmable to various frequencies in the range of

8 kHz to 32,768 kHz.

Hardware Mode--Fixed 8 kHz.

CLK32

Fixed 32,768 kHz

CLK1544

Fixed 1,544 kHz

CLK2048

Fixed 2,048 kHz

CN8380

2.0 Circuit Description

Quad T1/E1 Line Interface

2.7 Clock Rate Adapter

N8380DSA

Conexant

2-27

Advance Information

Table 2-11. CLAD Reference Frequencies and Configuration Examples (1 of 2)

CLAD

Reference

(kHz)

RSCALE

Phase

Compare

Frequency

(kHz)

VSCALE

CLADV

(kHz)

VSEL

000

111

1024

0001

000

110

1024

0001

000

101

1024

0001

000

100

1024

0001

128

000

128

011

1024

0001

256

000

256

010

1024

0001

512

000

512

001

1024

0001

1024

000

1024

000

1024

0001

2048

000

2048

000

2048

0010

4096

000

4096

000

4096

0011

8192

000

8192

000

8192

0100

16,384

000

16,384

000

16,384

0101

32,768

000

32,768

000

32,768

0110

12.0625

000

12.0625

111

1544

0111

24.125

000

24.125

110

1544

0111

48.25

000

48.25

101

1544

0111

96.5

000

96.5

100

1544

0111

193

000

193

011

1544

0111

386

000

386

010

1544

0111

772

000

772

001

1544

0111

1544

000

1544

000

1544

0111

3088

000

3088

000

3088

1000

6176

000

6176

000

6176

1001

12,352

000

12,352

000

12,352

1010

24,704

000

24,704

000

24,704

1011

000

111

1536

1101

000

110

1536

1101

000

101

1536

1101

000

100

1536

1101

192

000

192

011

1536

1101

2.0 Circuit Description

CN8380

2.7 Clock Rate Adapter

Quad T1/E1 Line Interface

2-28

Conexant

N8380DSA

Advance Information

To configure the CLAD:

Choose a CLADO output frequency. Refer to the CLAD Frequency Select
register [CSEL; addr 03] for a list of all possible CLADO output
frequencies.

Configure OSEL to select the CLADO output frequency.

Select the desired CLAD timing reference frequency from

Table 2-11

Configure RSCALE, VSCALE, VSEL from

Table 2-11

Many RSCALE and VSCALE values other than those shown in

Table 2-11

are

applicable. For instance, an alternate configuration for an input reference
frequency of 2048 kHz is displayed in

Table 2-12

Table 2-12. Sample Alternate Configuration

RSCALE is a programmable frequency divider which scales the CLAD

reference clock frequency before it is applied to the CLAD's phase detector.
Similarly, VSCALE scales the CLAD's internal feedback clock, CLADV. These
two clocks must have the same frequency at the phase detector's inputs for the
CLAD's loop to properly lock. So the rule is:

(CLAD reference freq.) ÷ (RSCALE factor) = (CLADV freq.) ÷ (VSCALE factor)

384

000

384

010

1536

1101

768

000

768

001

1536

1101

1536

000

1536

000

1536

1101

000

111

2560

1100

000

110

2560

1100

000

101

2560

1100

160

000

160

100

2560

1100

320

000

320

011

2560

1100

640

000

640

010

2560

1100

1280

000

1280

001

2560

1100

2560

000

2560

000

2560

1100

CLAD

Reference

(kHz)

RSCALE

Phase

Compare

Frequency

(kHz)

VSCALE

CLADV

(kHz)

VSEL

2048

001

1024

011

8192

0100

Table 2-11. CLAD Reference Frequencies and Configuration Examples (2 of 2)

CLAD

Reference

(kHz)

RSCALE

Phase

Compare

Frequency

(kHz)

VSCALE

CLADV

(kHz)

VSEL

CN8380

2.0 Circuit Description

Quad T1/E1 Line Interface

2.8 Test Access Port (JTAG)

N8380DSA

Conexant

2-29

Advance Information

2.8 Test Access Port (JTAG)

The CN8380 incorporates printed circuit board testability circuits in compliance
with IEEE Std P1149.1a1993, IEEE Standard Test Access Port and
BoundaryScan Architecture, commonly known as JTAG (Joint Test Action
Group).

The JTAG includes a test access port (TAP) and several data registers. The

TAP provides a standard interface through which instructions and test data are
communicated. A Boundary Scan Description Language (BSDL) file for the
CN8380 is available from the factory upon request.

The test access port consists of the

TRST

, TDI, TCK, TMS, and TDO pins. An

internal power on reset circuit or the

TRST

resets the JTAG port.

2.8.1 Instructions

In addition to the required BYPASS, SAMPLE/PRELOAD, and EXTEST
instructions, IDCODE instruction is supported. There are also two private
instructions.

Table 2-13

lists the JTAG instructions and their codes.

2.8.2 Device Identification Register

The JTAG ID register consists of a 4-bit version, a 16-bit part number, and an
11-bit manufacturer number as listed in

Table 2-14

Table 2-13. JTAG Instructions

Instructions

Code

BYPASS

1111

SAMPLE/PRELOAD

0001

EXTEST

0000

IDCODE

0010

Table 2-14. Device Identification JTAG Register

Version

Part Number

Manufacturer ID

1 1

0x0

0x8380

0x0D6

4 Bits

16 Bits

11 Bits

3.0 Registers

CN8380

3.1 Address Map

Quad T1/E1 Line Interface

3-2

Conexant

N8380DSA

Advance Information

4/21/99

SHAPE2

R/W