Document Outline

• Contents
• Figures
• Tables
• 1.0 Product Description
  • 1.1 Overview
    • 1.1.1 DS3 Mode
    • 1.1.2 E3 Mode
  • 1.2 Pin Descriptions (CX28342/3/4)
    • Figure 1-1. CX28342 Pin Assignments
    • Figure 1-2. CX28343 Pin Assignments
    • Figure 1-3. CX28344 Pin Assignments
    • Table 1-1. Pin Type Definitions
    • Table 1-2. CX28342/3/4 Pins 
    • Table 1-3. Transmitter Section Line Side 
    • Table 1-4. Transmitter Section System Side (1 of 2)
    • Table 1-5. Receiver Section Line Side (1 of 2)
    • Table 1-6. Receiver Section System Side (1 of 2)
    • Table 1-7. Microprocessor Interface 
    • Table 1-8. JTAG Interface
  • 1.3 Pin Descriptions (CX28346/8)
    • Figure 1-4. CX28346/8 Pin Assignments (Top View)
    • Table 1-9. Framer Distribution
    • Table 1-10. Pin Distribution
    • Table 1-11. CX28346 and CX28348 General Pins (1 of 2)
    • Table 1-12. Transmitter Section Line Side (1 of 2)
    • Table 1-13. Transmitter Section System Side (1 of 4)
    • Table 1-14. Receiver Section Line Side (1 of 3)
    • Table 1-15. Reciever Section System Side (1 of 3)
    • Table 1-16. Microprocessor Interface (1 of 2)
    • Table 1-17. JTAG Interface
• 2.0 Functional Description
  • Figure 2-1. Functional Block Diagram of a Channel
  • 2.1 Transmitter Operation
    • Figure 2-2. Transmitter Line Side Outputs
    • Figure 2-3. Tx System Side External Overhead Insertion (DS3 FEBE-only example)
    • Figure 2-4. DS3 System Side Transmission when TXSY is Externally Provided
    • Figure 2-5. DS3 System Side Transmission Unit when TXSY is Used as an Overhead Indication Bit
    • Figure 2-6. DS3 System Side Transmit when TXSY is Input Signal (Frame Start)
    • Figure 2-7. E3-G.751 Transmit Mode when TXSY is Frame Start Sync Output Signal
    • Figure 2-8. E3-G.751 Transmit Mode where TXSY is an Overhead Indicator Output Signal
    • Figure 2-9. E3-G751 Mode where TXSY is an Input Signal
    • Figure 2-10. E3-G.832 Mode where TXSY is an Output Signal Indicating Frame Start Sync
    • Figure 2-11. TXSY Transmitter System Side Signal (E3-G.832)
    • Figure 2-12. TXSY Transmitter System Side Signal (E3-G.832)
    • 2.1.1 Transmitter Overhead Bit Generation
      • Table 2-1. Overhead Sourcing Methods (1 of 2)
      • 2.1.1.1 DS3 Mode
        • Table 2-2. Overhead Options
      • 2.1.1.2 E3�G.751 Mode
      • 2.1.1.3 E3�G.832 Mode
    • 2.1.2 Alarm Signal Generation
      • 2.1.2.1 Loss of Signal Generation
      • 2.1.2.2 DS3 Mode
        • Table 2-3. DS3 Mode Alarm Signal Setting
      • 2.1.2.3 E3-G.751 Mode
      • 2.1.2.4 E3-G.832 Mode
    • 2.1.3 Terminal Data Link Transmission
      • 2.1.3.1 HDLC/LAPD Formatting Circuitry
      • 2.1.3.2 FIFO Control Circuitry
      • 2.1.3.3 Initial Setup of Transmit Data Link
      • 2.1.3.4 Sending Message Using the FIFO�Normal Operation
      • 2.1.3.5 FIFO Special Events
    • 2.1.4 FEAC Channel Transmission
      • 2.1.4.1 Single Code-Word Mode
      • 2.1.4.2 Repetitive Code-Word Mode
    • 2.1.5 Test Equipment�Error Insertion
      • 2.1.5.1 DS3 Mode
        • Table 2-4. Setting the Error Insertion1 Control Register in DS3 Mode (1 of 2)
      • 2.1.5.2 E3-G.751 Mode
        • Table 2-5. Setting the Error Insertion1 Control Register in E3-G.751 Mode
      • 2.1.5.3 E3-G.832 Mode
        • Table 2-6. Setting the Error Insertion1 Control Register in E3-G.832 Mode
      • 2.1.5.4 Line Coding Errors
        • Figure 2-13. Line Coding Error Insertion
  • 2.2 Receiver Operation
    • 2.2.1 LineSide Interface
      • Table 2-7. Line-side Interface Modes
      • Figure 2-14. Receiver Line Side Inputs
    • 2.2.2 SystemSide Interface
      • Figure 2-15. Receiver System Side Outputs [RXGAPCK]
      • Figure 2-16. Receiver System Side Outputs [REXTCK]
      • Figure 2-17. Receiver System Side Outputs
    • 2.2.3 Clock Dejitter FIFO
      • Figure 2-18. VCO Output Signal Timing
    • 2.2.4 Overhead Bit Recovery
      • 2.2.4.1 Processing of Overhead Bits
      • 2.2.4.2 Internal Processing of Overhead Bits
    • 2.2.5 Performance Monitoring
      • 2.2.5.1 Bipolar Violation (BPV), Excessive Zeros (EXZ), and Line Code Violation (LCV)
      • 2.2.5.2 Loss of Signal (LOS)
      • 2.2.5.3 Framing Bit Error (FBE)
      • 2.2.5.4 Out of Frame (OOF)
      • 2.2.5.5 Severely Errored Frame (SEF)
      • 2.2.5.6 Alarm Indication Signal (AIS)
      • 2.2.5.7 Idle Signal (IDLE)
      • 2.2.5.8 Parity Error (PER) and P-Bit Disagreement (PBD)
      • 2.2.5.9 Path Parity Error (PPER)
      • 2.2.5.10 Remote Alarm/Defect Indication (RAI/RDI), X-bit disagreement (XBD)
      • 2.2.5.11 Far-End Block Error/Remote Error Indication (FEBE/REI)
    • 2.2.6 OneSecond Counter Latching
    • 2.2.7 Terminal Data Link Reception
      • Table 2-8. Status Byte Description
      • 2.2.7.1 Initial Setup
      • 2.2.7.2 Writing Messages into the FIFO
      • 2.2.7.3 Reading Messages from the FIFO
    • 2.2.8 FarEnd Alarm and Control Channel Reception
      • 2.2.8.1 Writing into the FEAC Stack
      • 2.2.8.2 Reading from the FEAC Stack
  • 2.3 Microprocessor Interface
    • 2.3.1 Address/Data Bus
    • 2.3.2 Control Signals
    • 2.3.3 Interrupt Requests
    • 2.3.4 Hardware Reset
    • 2.3.5 Software Reset
    • 2.3.6 Initialization Guidelines
  • 2.4 Loopbacks
    • Figure 2-19. Loopback Types
    • 2.4.1 Shallow Line Loopback
    • 2.4.2 Remote Line Loopback
    • 2.4.3 Payload Loopback
    • 2.4.4 Source Loopback
  • 2.5 Joint Test Access Group (JTAG) Interface
    • 2.5.1 Instructions
      • Table 2-9. JTAG Instruction Codes
• 3.0 Registers
  • 3.1 Register Address Map
  • 3.2 Register Address Map
    • Table 3-1. General Registers 
    • Table 3-2. Channel (i) Registers (1 of 2)
  • 3.3 Control Registers
    • General Control Registers
      • General1 Control Register (GCR00)
      • General2 Control Register (GCR01)
    • Channel Control Registers
      • Mode Control Register (CR00i)
      • Counter Interrupt Control Register (CR01i)
    • Dual-Edge Interrupt Control Registers
      • Alarm Start Interrupt Control Register (CR02i)
      • Alarm End Interrupt Control Register (CR03i)
  • 3.4 Feature Control Registers
    • Feature1 Control Register (CR04i)
    • Feature2 Control Register (CR05i)
    • Feature3 Control Register (CR06i)
    • Feature4 Control Register (CR07i)
    • Feature5 Control Register (CR08i)
    • Transmit Overhead Insertion Control Registers
      • Transmit Overhead Insertion1 Control Register (CR09i)
        • Table 3-3. DS3-C Bit Parity/E3-G.751 Mode Field Interpretation
      • DS3-C Bit Parity
        • Table 3-4. E3-G.832 Mode Field Interpretation 
      • REXTCK Control Register (CR11i)
      • Receive Overhead Control Register (CR12i)
      • Transmit Data Link Control Register (CR13i)
      • Transmit Data Link Threshold Control Register (CR14i)
      • Transmit Data Link Message Byte (CR15i)
      • Receive Data Link Control Register (CR16i)
      • Receive Data Link Threshold Control Register (CR17i)
      • Transmit FEAC Channel Byte (CR18i)
    • Error Insertion Control Registers
      • Error Insertion1 Control Register (CR19i)
      • Error Insertion2 Control Register (CR20i)
  • 3.5 Status Registers
    • General Status Registers
      • Source Channel Status Register (GSR00)
      • Part Number/Hardware Version Register (GSR01)
    • Channel Status Registers
      • DS3/E3 Maintenance Status Register (SR00i)
      • Interrupt Source Status Register (SR01i)
      • Counter Interrupt Status Register (SR02i)
    • Dual-Edge Interrupt Status Registers
      • Alarm Start Interrupt Status Register (SR03i)
      • Alarm End Interrupt Status Register (SR04i)
    • E3-832 MA Fields Registers
      • E3-G.832 MA Fields Status Register (SR06i)
      • E3-G.832 SSM Field Status Register (SR07i)
      • Transmit Data Link FEAC Status Register (SR08i)
      • Receive Data Link Status Register (SR11i)
      • Receive Data Link Message Byte (SR12i)
      • Receive FEAC Status Register (SR17i)
      • Receive AIC Byte (SR18i)
  • 3.6 Counters
    • DS3/E3 Parity Error Counter (Ctr00i)
    • DS3 Parity Disagreement Counter (Ctr01i)
    • DS3 X Disagreement Counter (Ctr02i)
    • DS3/E3 Frame Error Counter (Ctr03i)
    • DS3 Path Parity Error Counter (Ctr04i)
    • DS3/E3 FEBE Event Counter (Ctr05i)
    • DS3/E3 Excessive Zeros Counter (Ctr06i)
    • DS3/E3 LCV Counter (Ctr07i)
  • 3.7 General Counters
    • One-Second Timer (GCtr00)
• 4.0 Electrical and Mechanical Specifications
  • 4.1 Environmental Conditions
    • 4.1.1 Power Requirements and Temperature Range
      • Table 4-1. Absolute Maximum Ratings
      • 4.1.1.1 Recommended Operating Conditions
        • Table 4-2. Recommended Operating Conditions
      • 4.1.1.2 Power Ramp Sequence of VDDx and VDDOx
        • Figure 4-1. Power Ramp Sequence of VDDx and VDDOx
    • 4.1.2 Electrical Characteristics
      • 4.1.2.1 DC Characteristics
        • Table 4-3. DC Characteristics
  • 4.2 AC Characteristics
    • 4.2.1 Input Clock Timing
      • Figure 4-2. Input Clock Timing
      • Table 4-4. Input Clock Timing
    • 4.2.2 Signal Timing and Clock Output Timings
      • Figure 4-3. Line Side Receiver Input Data Setup/Hold Timing (1 = tsu [setup time]; 2 = thld [hold...
      • Figure 4-4. Line Side Transmitter Output Data Timing (1 = tpd [propogation delay])
      • Figure 4-5. System-Side Transmitter Interface Timing
      • Figure 4-6. System-Side Receiver Interface Timing
      • Table 4-5. Output Signal Timing 
      • Table 4-6. Input Signal Timing
  • 4.3 Microprocessor Interface Timing
    • Figure 4-7. Intel Asynchronous Read Cycle (MOTO* = 1)
    • Table 4-7. Intel Asynchronous Read Cycle (MOTO* = 1)
    • Figure 4-8. Intel Asynchronous Write Cycle (MOTO* = 1)
    • Table 4-8. Intel Asynchronous Write Cycle (MOTO* = 1)
    • Figure 4-9. Motorola Asynchronous Read Cycle (MOTO* = 0)
    • Table 4-9. Motorola Asynchronous Read Cycle (MOTO* = 0)
    • Figure 4-10. Motorola Asynchronous Write Cycle (MOTO* = 0)
    • Table 4-10. Motorola Asynchronous Write Cycle (MOTO* = 0)
    • 4.3.1 Additional Restrictions
  • 4.4 JTAG Interface Timing
    • Figure 4-11. JTAG Interface Timing
    • Table 4-11. Test and Diagonstic Interface Timing Requirements
    • Table 4-12. Test and Diagnostic Interface Switching Characteristics
  • 4.5 Mechanical Specifications
    • 4.5.1 Package Types
      • Figure 4-12. Mechanical Specification for 144-pin ETQFP
      • Figure 4-13. Mechanical Specification for 27x27 mm 318-Ball PBGA
  • 4.6 Applicable Standards
• Appendix A: Dejitter Circuit Analysis
  • Figure A-1. CS2834x Dejitter Circuitry
  • Figure A-2. Dejitter Control Loop
  • Figure A-3. Components of System Gain
  • Figure A-4. Bode Diagram of the System
  • Figure A-5. Jitter Transfer with FIFO Enabled
  • Figure A-6. Jitter Tolerance with FIFO Enabled
  • Figure A-7. Jitter Transfer with FIFO Disabled
  • Figure A-8. Jitter Tolerance with FIFO Disabled
• Appendix B: Frame Structure Summary
  • Table B-1. Overhead Bits in DS3 Mode
  • Table B-2. Overhead Bits in E3G751 Mode
  • Table B-3. Overhead Bytes in E3G832
• Appendix C: B3ZS/HDB3 Encoding
• Appendix D: Acronyms