HPFC-6600/6640 Tachyon QE4
PMC-2060420, Issue 2
Copyright PMC-Sierra, Inc. 2006
All rights reserved. Proprietary and Confidential to PMC-Sierra, Inc. and for its customers' internal use.
High Performance Fibre Channel Controller
PRODUCT OVERVIEW
The Tachyon QE4 device (HPFC-66xx Series) is a high-performance 4-
port 4 Gbit/s Fibre Channel controller. It features an 8-lane, native PCI
Express bus, enabling full-duplex operation. QE4 is an integrated single
chip solution ideal for a variety of high-performance I/O applications.
The Tachyon proven State-Machine architecture scales directly with
system CPU performance and is not limited by the constraints of an
embedded microprocessor. QE4 supports up to 4 processors per FC
link using 4 independent register and API queue structures. This
feature allows systems to scale to required performance as necessary
while maintaining compatibility with the Tachyon programming model
at the register level, and with the Tachyon Software Development Kit
(TSDK) API tools.
QE4 supports the T-10 Standard Protection Information via Advanced
Data Integrity Field (ADIF) which ensures end to end data
checking/integrity across the storage domain. ADIF provides robust
CRC-based data protection with mechanisms to initiate, extend, verify
and replace, or terminate a protection domain.
QE4 offers additional performance by providing advanced frame-
handling functions that are normally handled by the host processor.
These additional enhancements make it possible for the system to
utilize intelligent frame handling while reducing CPU utilization.
APPLICATIONS
Enterprise Storage Systems
Embedded subsystems
Disk Arrays
Multi-protocol Bridges/Routers
Intelligent Switches
Virtualization Devices
FEATURES
4-port 4/2/1 Gbit/s Fibre Channel controller
TWI control and presence detect for optical transceivers
Multi DMA for cache mirroring
CRC offload engine for enabling non-DIF compliant solutions
Enhanced TRE for higher performance on small transfers (IOPS)
ERQ/SCSI LL priority control for additional Quality of Service control
Support for up to 4 v processors per FC Link
Fibre Channel auto-speed negotiation
PCI Express 8-lane 2.5 GHz Host Interface
Supports 10Km distance per link at 4G link rate with internal
memory
Full duplex operation for each port
Advanced Data Integrity Field protection (ADIF)
Virtualization support with H/W assisted FC Frame Steering
Pin compatible with Tachyon predecessor QX4 64xx series
SCSI BiDi command assist
Industry-leading technical support and documentation
Software development API tools for Linux, and Windows.
Standard and RoHS compliant packages
DATA INTEGRITY FEATURES
Variable block size support: 512/520 bytes
SEST-based DIF
CRC Offload Engine (COE)
DIF per L/A (DPL)
Preliminary
Product Brief
BLOCK DIAGRAM
Tachyon Expressway
PCI Express Core
Port 1
Port 4
Port 3
Port 2
4GB FC
4GB FC
4GB FC
4GB FC
PCI Express x8 Interface
1
8
2
HPFC-6600/6640 Tachyon QE4 High Performance IC
Corporate Head Office:
PMC-Sierra, Inc.
Mission Towers One
3975 Freedom Circle
Santa Clara, CA, 95054, U.S.A.
Tel: 1.408.239.8000
Fax: 1.408. 492.1157
PMC-2060420 P2 Copyright PMC-Sierra, Inc. 2006. All rights
reserved. For a complete list of PMC-Sierra's trademarks , visit
www.pmc-sierra.com/legal/. Other product and company names
mentioned herein may be the trademarks of their respective owners.
For corporate information, send email to: info@pmc-sierra.com.
All product documentation is available on our web site at:
www.pmc-sierra.com.
Operations Head Office:
PMC-Sierra, Inc.
100-2700 Production Way
Burnaby, BC V5A 4X1 Canada
Tel: 1.604.415.6000
Fax: 1.604.415.6200
TACHYON EXPRESSWAY ARCHITECTURE
Provides an interface from the Fibre Channel core to PCI Express
Allows simultaneous operation on each of the four 4 Gbit ports
AER and Error ECN support
MSI-X
4K PCIe TLP
PRELIMINARY SPECIFICATIONS
Package Type: FC PBGA, 1mm ball pitch
Power Dissipation: 5 Watts (Typical)
Thermal Specification: 0 - 110C, Junction Temp
Voltage Margin: 5%
MAINTAIN TACHYON FIBRE CHANNEL FAMILY
PROGRAMMING MODEL (SIMILAR TO THE QX4
HPFC-64XX DEVICE)
Registers memory mapped
Backward compatible offsets for Fibre Channel core registers
STANDARD TACHYON FIBRE CHANNEL CORE
FEATURE SET
Performance scalable State Machine-based architecture
Independent, concurrent inbound/outbound transaction processing
Multiple outbound context support
Support for SCSI initiator, target and initiator/target modes
Complete sequence segmentation and reassembly done in
hardware
Up to 2048-byte frame payloads
Fully assisted FC-FS Class 2 and Class 3 support
ACK0/ACK1 model assists in hardware
Interrupt avoidance mechanisms
Standard Tachyon Fibre Channel Core Feature Set
FURTHER RESOURCES
www.pmc-sierra.com/storage
www.pmc-sierra.com/tachyon
4G SAN-ATTACHED FIBRE CHANNEL STORAGE SYSTEM APPLICATION
Link Card B
4G FC
E Port
4G FC
E Port
3G SAS
3G SAS
Link Card A
FC
Disk 6
FC
Disk 6
FATA
Disk 1
FATA
Disk 1
FC
Disk 12
FC
Disk 12
Controller Card B
4G FC
E Port
RAID
X86 / PPC
Processors
4G FC
E Port
RAID
X86 / PPC
Processors
Controller Card A
FC
Disk 6
FC
Disk 6
FC
Disk 1
FC
Disk 1
FC
Disk 12
FC
Disk 12
FC
FC
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