F
EATURES
D
ESCRIPTION
C
ONNECTIONS
T
OP
L
EVEL
D
IAGRAM
A
PPLICATIONS
O
RDERING
I
NFORMATION
MC2045-3
Postamplifier for Applications to 200Mbps
PAGE -1-
q
SDH/SONET/ATM
q
Fast Ethernet
q
FDDI
q
ESCON
MC2045-3_C
PRELIMINARY INFORMATION
The MC2045-3 is an integrated, high gain limiting
amplifier intended for fibre optic communication to
200Mbps. Normally placed following the photodetector
& transimpedance amplifier, the post-amplifier pro-
vides the necessary gain to give PECL compatible
logic outputs.
The MC2045-3 also includes a programmable signal-
level detector, allowing the user to set thresholds at
which the logic outputs are enabled. The signal de-
tect function has typically 2.25dB (optical) of hyster-
esis which prevents chatter at low input levels.
A squelch function, which turns off the output when
no signal is present, is provided by externally con-
necting the ST output to the JAM input.
q
Low-cost IC, fabricated in advanced sub-micron
BiCMOS process
q
1.5mV input sensitivity
q
Wide range programmable input-signal level
detect
q
Fully differential design
q
Supports 3.3V and 5V supplies
q
Available in TSSOP20, SOIC16 and QSOP16
package as well as die form
q
Complimentary PECL data & signal detect logic
outputs
D
IN
D
OUT
D
OUT
GndE
GndE
V
CC
E
V
CC
E
V
REF
V
SET2
C
AZ
-
C
AZ
+
V
CC
A
GndA
ST
JAM
V
SET
C
F
Level
Detector
GndA
V
CC
A
ST
D
IN
Microcosm
MC2045-3
Date Code
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
C
A Z
-
C
A Z
+
G n d A
D
IN
V
CC
A
C
F
JAM
D
IN
V
S E T
V
R E F
V
CC
E
D
OUT
GndE
ST
ST
D
OUT
SOIC16, QSOP16 Package
Microcosm
MC2045-3
Date Code
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
C
A Z
-
C
A Z
+
NC
G n d A
D
IN
D
IN
V
CC
A
C
F
NC
V
S E T
V
R E F
V
CC
E
V
CC
E
D
OUT
D
OUT
GndE
GndE
ST
ST
JAM
TSSOP20 Package
Part
Pin-Package
MC2045-3DIEWP
Waffle pack
MC2045-3WAFER
Expanded Whole 8"on a 10" Grip
Ring
MC2045-3S16
SOIC16
MC2045-3Q16
QSOP16
MC2045-3T20
TSSOP20
MC2045-3
Postamplifier for Applications to 200Mbps
MC2045-3_C
PRELIMINARY INFORMATION
P
IN
D
ESCRIPTION
PAGE -2-
Pin Name
16 SOIC
Pin No.
20 TSSOP
Pin No.
Function
C
AZ
-
1
1
Auto-zero capacitor pin.
C
AZ
+
2
2
Auto-zero capacitor pin.
GNDA
3
4
Analogue section ground pin. Connect to most negative supply.
Must be at same potential as GNDE Pin.
D
IN
4
5
Differential data input.
D
IN
5
6
Inverse differential data input.
V
CC
A
6
7
Analogue section power pin. Connect to most positive supply.
Must be at the same potential as V
CC
E pin.
C
F
7
8
Level-detect filter capacitor pin. Connect the capacitor
between this pin and V
CCA
.
JAM
8
11
PECL compatible input controlling output buffers (D
OUT
and
D
OUT
pins). On chip pull-down defaults to low. Can be driven
from CMOS.
ST
9
12
Logical inverse of ST Pin. May be connected to JAM Pin to
enable automatic squelch function to operate. PECL output.
ST
10
13
Input signal-level status. This PECL output is LOW when the
input signal is below the threshold set by the uses.
GNDE
11
14, 15
Digital section ground pin. Connect to the most negative
supply. Must be at the same potential as GNDA Pin.
D
OUT
12
16
Logical inverse of D
OUT
Pin. JAM high forces D
OUT
high. In
phase with D
IN
.
D
OUT
13
17
PECL compatible diffential Data Output. JAM high forces D
OUT
low. In phase with D
IN
.
V
CC
E
14
18,19
Digital output section power pin. Connect to the most positive
supply must be at same potential as V
CC
A pin.
V
REF
15
20
Connect to
positive supply via resistor. Sets value of internal
reference current.
V
SET
16
10
Input threshold-level setting circuit. Connect to V
CC
via a
resistor.
MC2045-3
Postamplifier for Applications to 200Mbps
MC2045-3_C
PRELIMINARY INFORMATION
AC C
HARACTERISTICS
PAGE -3-
A
BSOLUTE
M
AXIMUM
R
ATINGS
DC C
HARACTERISTICS
These are the absolute maximum ratings at or beyond which the IC can be expected to fail or be damaged.
Reliable operation at these extremes for any length of time is not implied.
Symbol
Parameter
Rating
Units
V
CC
Power supply (V
CC
-Gnd)
6
V
T
A
Operating ambient
-40 to +85
C
T
STG
Storage temperature
-65 to +150
C
Symbol
Parameter
Min.
Typ.
Max.
Units
BW
Bandwidth: Gain >60dB
100
-
-
MHz
R
IN
Input resistance
-
10
-
k
C
IN
Input capacitance
-
-
2
pF
t
PWD
Pulse width distortion
-
-
0.4
ns
t
R
, t
F
ECL out rise / falltimes (20-80% points)
-
1.0
2.0
ns
(1) 50
to V
CC
-2V
(2) 0 to +80C
(3) -40C
Symbol
Parameter
Min.
Typ.
Max.
Units
V
IN
Input signal voltage Single-ended:
Differential:
0.5
1
-
400
800
mVpp
V
OS
Effective input offset voltage
-
-
50
V
V
N
Input RMS noise in 100MHz
-
-
85
V
V
TH
Input level detect programmability
2
-
100
mVpp
V
HYS
Level detect hysteresis (optical)
1.85
2.25
3.00
dB
I
INJ
JAM input current HIGH
-10
-
10
A
I
CC
Supply current (no ECL loads)
-
-
35
mA
V
OH
PECL
(1)
output HIGH
(2)
-1.025
(3)
-1.075
-
-
-0.88
-0.88
V
V
OL
PECL
(1)
output LOW
(2)
-1.81
(3)
-1.86
-
-
-1.62
-1.62
V
MC2045-3
Postamplifier for Applications to 200Mbps
MC2045-3_C
PRELIMINARY INFORMATION
T
YPICAL
P
ERFORMANCE
C
URVES
PAGE -4-
Signal Detect Assert Range (5V)
(over process and temperature)
0
20
40
60
80
100
120
140
160
180
200
2
6
10
14
18
22
26
30
Rset (k)
Differential Input (mVpp)
min (5v)
max (5v)
Differential Input (
mVpp
)
Rset (K
)
Signal Detect Assert Range (3.3V)
(over process and temperature)
0
20
40
60
80
100
120
140
160
180
200
2
6
10
14
18
22
2 6
30
Rset (k)
Differential Input (Vpp)
min (3.3v)
max (3.3v)
Differential Input (
mVpp
)
Rset (K
)
Signal Detect Detail (5V)
Typical Signal Detect (3.3V)
Signal Detect Detail (3.3V)
Typical Signal Detect (5V)
Note: For all of these graphs R
REF
= 2k
0
50
100
150
200
250
0
5
10
15
20
25
30
35
40
R
SET
(k
)
Differential Input (mVpp)
5.0V Assert
5.0V De-assert
0
5
10
15
20
25
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
RSET (kW)
Differential Input (mVpp)
3.3V Assert
3.3V De-assert
0
50
100
150
200
250
0
5
10
15
20
25
30
35
40
R
SET
(k
)
Differential Input (mVpp)
3.3V Assert
3.3V De-assert
0
5
10
15
20
25
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
R
SET
( k
)
Differential Input (mVpp)
5V Assert
5V De-assert
MC2045-3
Postamplifier for Applications to 200Mbps
MC2045-3_C
PRELIMINARY INFORMATION
PAGE -5-
F
UNCTIONAL
B
LOCK
D
IAGRAM
F
UNCTIONAL
D
ESCRIPTION
Input
The Data Input pins are internally DC biased at ap-
proximately V
CC
-1V. The MC2045-3 signals are AC
coupled, using capacitors. These capacitors must
be large enough to pass the lowest frequencies of
interest (consecutive `1's or `0's) considering the in-
put resistance.
For example, at 155Mbps SONET, there is a maxi-
mum of 72 consecutive `1' s, which is is 465ns. To
acheive the maximum allowed data dependant jitter,
the low frequency cut-off needs to be lower by a fac-
tor of 10. However, it is better to set it at least one
decade lower, due to the interaction of the time con-
stants for the input stage and the DC restore circuitry,
giving an input capacitor value of 2.2nF.
DC Offset Compensation
An autozero circuit is included to remove the effects
of DC offset. An external capacitor smoothes the
feed back, acting with the internal 10k
circuit re-
sistance to pass the lowest frequencies of interest.
At data rates between 125Mbps and 155 Mbps, this
is normally set to 180pF.
Level detector
The input data is first amplified, with the level of am-
plification set by the ratio of R
SET
/R
REF
. This amplifi-
cation level sets the level of input at which the status
D
IN
1st Stage
2nd Stage
Output
Amp
Level
Detector
V
CC
A
C
F
V
CC
E
ST
ST
JAM
D
OUT
D
OUT
C
AZ
+
C
AZ
-
V
CC
E
V
SET
V
REF
GndE
GndA
D
IN
10k
10k
10k
10k
thresholds operate. The data is then rectified and
low-pass filtered before being compared with a ref-
erence voltage. The low-pass filter is controlled by
C
F
, and 10nF will provide a nominal 2S time con-
stant, thus avoiding false triggering due to variation
in edge density of data.
The comparator has the equivalent of 2.25dB (typ.)
of optical hysteresis.
Squelch Function
The MC2045-3 provides for programmable input-sig-
nal level detection, and this may be used to auto-
matically force the data outputs to a known state if
the input signal falls below threshold using the JAM
input. This is normally used to allow data to propa-
gate only when the signal is above the users' Bit-
Error-Rate (BER) requirement. It therefore stops the
data outputs toggling due to noise when no signal is
present.
In order to implement this function, ST should be
connected to the JAM, thus forcing the data outputs
to logical zero when the signal falls below threshold.
Note that R
SET
and R
REF
must be connected, even if
the Level-Detect function is not required.
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