1
SY88883V
Micrel
M9999-031804
hbwhelp@micrel.com or (408) 955-1690
DESCRIPTION
s
Multi-rate up to 3.2Gbps operation
s
Wide gain-bandwidth product
38dB differential gain
2.2GHz 3dB bandwidth
s
Low noise 50
CML data outputs
800mV
pp
output swing
60ps edge rates
5ps
rms
typ. random jitter
15ps
pp
typ. deterministic jitter
s
Chatter-free Signal Detect (SD) output
4.6dB electrical hysteresis
OC-TTL output with internal 5k
pull-up resistor
s
Programmable SD sensitivity using single external
resistor
s
Internal 50
data input termination
s
Wide operating range
Single 3.3V
10% or 5V
10% power supply
40
C to +85
C industrial temperature range
s
Available in a tiny 10-pin MSOP (3mm
3mm)
package
FEATURES
3.3V/5V 3.2Gbps CML LOW-POWER
LIMITING POST AMPLIFIER w/TTL SD
SY88883V
APPLICATIONS
s
1.25Gbps and 2.5Gbps Gigabit Ethernet
s
1.062Gbps and 2.125Gbps Fibre Channel
s
155Mbps, 622Mbps, 1.25Gbps and 2.5Gbps
SONET/SDH
s
Gigabit interface converter (GBIC)
s
Small form factor (SFF) and small form factor
pluggable (SFP) transceivers
s
Parallel 10G Ethernet
s
High-gain line driver and line receiver
Rev.: A
Amendment: /0
Issue Date:
March 2004
The SY88883V low-power, limiting post amplifier is
designed for use in fiber optic receivers. The device connects
to typical transimpedance amplifiers (TIAs). The linear signal
output from TIAs can contain significant amounts of noise
and may vary in amplitude over time. The SY88883V
quantizes these signals and outputs typically 800mV
pp
voltage-limited waveforms.
The SY88883V operates from a single +3.3V
10% or
+5V
10% power supply, over the industrial temperature
range of 40
C to +85
C. With its wide bandwidth and high-
gain, signals with data rates up to 3.2Gbps and as small as
10mV
pp
can be amplified to drive devices with CML inputs
or AC-coupled PECL inputs.
The SY88883V generates a signal detect (SD) open-
collector TTL output with internal 5k
pull-up resistor. A
programmable signal detect level set pin (SD
LVL
) sets the
sensitivity of the input amplitude detection. SD asserts high
if the input amplitude rises above the threshold set by SD
LVL
and de-asserts low otherwise. Typically 4.6dB SD hysteresis
is provided to prevent chattering.
All support documentation can be found on Micrel's web
site at www.micrel.com.
TYPICAL PERFORMANCE
FUNCTIONAL BLOCK DIAGRAM
Limiting
Amplifer
CML
Buffer
GND
2.8k
50
Level
Detect
SD
D
IN
/D
IN
V
CC
V
CC
SD
LVL
D
OUT
/D
OUT
5k
OC-TTL
Buffer
V
CC
1.3V
3.3V, 25
C, 10mV
PP
Input
@2.5Gbps 2
23
1 PRBS, R
LOAD
= 50
to V
CC
TIME (100ps/div.)
Output Swing
(75mV/div
.)
2
SY88883V
Micrel
M9999-031804
hbwhelp@micrel.com or (408) 955-1690
PACKAGE/ORDERING INFORMATION
1
GND
DIN
/DIN
GND
SDLVL
10 VCC
DOUT
/DOUT
VCC
SD
9
8
7
6
2
3
4
5
10-Pin MSOP (K10-1)
Ordering Information
Package
Operating
Package
Part Number
Type
Range
Marking
SY88883VKI
K10-1
Industrial
883V
SY88883VKITR
(1)
K10-1
Industrial
883V
Note:
1.
Tape and Reel.
PIN DESCRIPTION
Pin Number
Pin Name
Type
Pin Function
1, 4
GND
Ground
Device ground.
2, 3
DIN, /DIN
Differential Data Input
Differential data input. Each pin internally terminates to an internal
reference voltage (V
REF
) through 50
.
5
SDLVL
Input:
Signal Detect Level Set: A resistor from this pin to V
CC
sets the
Default is
threshold for the data input amplitude at which the SD output will be
maximum sensitivity.
asserted. Bypass with 0.01
F low ESR capacitor from SD
LVL
to V
CC
to stabilize SD
LVL
.
6
SD
Open Collector
Signal Detect: Asserts high when the data input amplitude rises
TTL Output with
above the threshold set by SD
LVL
.
internal 5k
pull-up
resistor
7, 10
VCC
Power Supply
Positive power supply. Bypass with 0.1
F
0.01
F low ESR
capacitors. 0.01
F capacitors should be as close to VCC pins as
possible.
8, 9
DOUT, /DOUT
Differential CML Output
Differential data output.
3
SY88883V
Micrel
M9999-031804
hbwhelp@micrel.com or (408) 955-1690
Absolute Maximum Ratings
(1)
Supply Voltage (V
CC
) ....................................... 0V to +7.0V
SD
LVL
Voltage ........................................................ 0 to V
CC
SD Current .................................................................
5mA
D
OUT
, /D
OUT
Current ................................................
25mA
D
IN
, /D
IN
Current ......................................................
10mA
Storage Temperature (T
S
) ....................... 65
C to +150
C
Lead Temperature (soldering, 10 sec.) ..................... 220
C
Operating Ratings
(2)
Supply Voltage (V
CC
) .............................. +3.0V to +3.6V or
............................................................ +4.5V to +5.5V
Ambient Temperature (T
A
) ......................... 40
C to +85
C
Junction Temperature (T
J
) ....................... 40
C to +120
C
Package Thermal Resistance
(3)
MSOP
(
JA
) Still-Air .................................................. 113
C/W
(
JB
) ................................................................ 74
C/W
V
CC
= 3.0V to 3.6V or 4.5V to 5.5V; R
LOAD
= 50
to V
CC
; T
A
= 40
C to +85
C; typical values at V
CC
= 3.3V, T
A
= 25
C.
Symbol
Parameter
Condition
Min
Typ
Max
Units
I
CC
Power Supply Current
(4)
3.3V
19
28
mA
5V
21
31
mA
I
CC
Power Supply Current
(5)
3.3V
32
53
mA
5V
38
58
mA
V
REF
Internal Reference Voltage
V
CC
1.3
V
SD
LVL
SD
LVL
Level
V
REF
V
CC
V
V
OH
Output HIGH Voltage
Note 6
V
CC
0.020 V
CC
0.005
V
CC
V
V
OL
Output LOW Voltage
Note 6
V
CC
0.400 V
CC
0.275
V
V
OFFSET
Differential Output Offset
80
mV
Z
O
Single-Ended Output Impedance
40
50
60
Z
I
Single-Ended Input Impedance
40
50
60
DC ELECTRICAL CHARACTERISTICS
V
CC
= 3.0V to 3.6V or 4.5V to 5.5V; R
LOAD
= 50
to V
CC
; T
A
= 40
C to +85
C; typical values at V
CC
= 3.3V, T
A
= 25
C.
Symbol
Parameter
Condition
Min
Typ
Max
Units
V
OH
SD Output HIGH Level
Sourcing 100
A
2.4
V
CC
V
V
OL
SD Output LOW Level
Sinking 2mA
0.5
V
Notes:
1.
Permanent device damage may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for
extended periods may affect device reliability.
2.
The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3.
Thermal performance assumes use of 4-layer PCB.
4.
Excludes current of CML output stage. See "Detailed Description."
5.
Total device current with no output load.
6.
Output levels are based on a 50
to V
CC
load impedance. If the load impedance is different, the output level will be changed. Amplifier is in limiting
mode.
TTL DC ELECTRICAL CHARACTERISTICS
4
SY88883V
Micrel
M9999-031804
hbwhelp@micrel.com or (408) 955-1690
V
CC
= 3.0V to 3.6V or 4.5V to 5.5V; R
LOAD
= 50
to V
CC
; T
A
= 40
C to +85
C; typical values at V
CC
= 3.3V, T
A
= 25
C.
Symbol
Parameter
Condition
Min
Typ
Max
Units
HYS
SD Hysteresis
Note 7
2
4.6
8
dB
PSRR
Power Supply Rejection Ratio
35
dB
t
OFF
SD Release Time
0.1
0.5
s
t
ON
SD Assert Time
0.2
0.5
s
t
r
, t
f
Differential Output Rise/Fall Time
Note 8
60
120
ps
(20% to 80%)
t
JITTER
Deterministic
Note 9
15
ps
pp
Random
5
ps
rms
V
ID
Differential Input Voltage Swing
10
1800
mV
pp
V
OD
Differential Output Voltage Swing
Note 10
550
800
mV
pp
V
SR
SD Sensitivity Range
Note 11
10
50
mV
pp
B
3dB
3dB Bandwidth
2.2
GHz
A
V(Diff)
Differential Voltage Gain
32
38
dB
S
21
Single-Ended Small-Signal Gain
26
32
dB
Notes:
7.
Electrical signal.
8.
With input signal V
ID
> 50mV
pp
and 50
load.
9.
Deterministic jitter measured using K28.5 pattern at 2.488Gbps, V
ID
= 10mV
pp
. Random jitter measured using K28.7 pattern at 2.488Gbps,
V
ID
= 10mV
pp
.
10. Input is a 200MHz square wave, t
r
< 300ps, 50
load. V
ID
14mV
pp
.
11. This is the detectable range of input amplitudes that can de-assert SD. The input amplitude to assert SD is 28dB higher than the de-assert
amplitude. See "Typical Operating Characteristics" for a graph showing how to choose a particular R
SDLVL
for a particular SD de-assert, and its
associated assert, amplitude.
AC ELECTRICAL CHARACTERISTICS
TYPICAL OPERATING CHARACTERISTICS
0
10
20
30
40
50
60
70
80
90
10
100
1000
10000 100000
V
ID
(mV
pp
)
R
SDLVL
SD Assert/De-assert Level
vs. R
SDLVL
ASSERT
DE-ASSERT
V
CC
= 3.3V, GND = 0V, T
A
= 25
C, unless otherwise stated.
5
SY88883V
Micrel
M9999-031804
hbwhelp@micrel.com or (408) 955-1690
DETAILED DESCRIPTION
The SY88883V low-power limiting post amplifier operates
from a single +3.3V or +5V power supply, over temperatures
from 40
C to +85
C. Signals with data rates up to 3.2Gbps
and as small as 10mV
pp
can be amplified. Figure 1 shows
the allowed input voltage swing. The SY88883V generates
an SD output. SD
LVL
sets the sensitivity of the input
amplitude detection.
Input Amplifier/Buffer
The SY88883V's inputs are internally terminated with 50
to an internal reference voltage (V
REF
). V
REF
is typically
1.3V below V
CC
. Unless not affected by this internal
termination scheme, upstream devices need to be
AC-coupled to the SY88883V's inputs. Figure 2 shows a
simplified schematic of the input stage.
The high-sensitivity of the input amplifier allows signals
as small as 10mV
pp
to be detected and amplified. The input
amplifier allows input signals as large as 1800mV
pp
. Input
signals are linearly amplified with a typically 38dB differential
voltage gain. Since it is a limiting amplifier, the SY88883V
outputs typically 800mV
pp
voltage-limited waveforms for input
signals that are greater than 10mV
pp
. Applications requiring
the SY88883V to operate with high-gain should have the
upstream TIA placed as close as possible to the SY88883V's
input pins to ensure the best performance of the device.
Output Buffer
The SY88883V's CML output buffer is designed to drive
50
lines. The output buffer requires appropriate termination
for proper operation. An external 50
resistor to V
CC
or
equivalent for each output pin provides this. Figure 3 shows
a simplified schematic of the output stage and includes an
appropriate termination method. Of course, driving a
downstream device with a CML input that is internally
terminated with 50
to V
CC
eliminates the need for external
termination. As noted in the previous section, the amplifier
outputs typically 800mV
pp
waveforms across 25
total loads.
The output buffer, thus, switches typically 16mA tail-current.
Figure 4 shows the power supply current measurement
which excludes the 16mA tail-current.
Signal Detect
The SY88883V generates a chatter-free signal detect
(SD) open-collector TTL output with internal 5k
pull-up
resistor as shown in Figure 5. SD is used to determine that
the input amplitude large enough to be considered a valid
input. SD asserts high if the input amplitude rises above the
threshold set by SD
LVL
and deasserts low otherwise.
Typically 4.6dB SD hysteresis is provided to prevent
chattering.
Signal Detect-Level Set
A programmable signal detect-level set pin (SD
LVL
) sets
the threshold of the input amplitude detection. Connecting
an external resistor between V
CC
and SD
LVL
sets the voltage
at SD
LVL
. This voltage ranges from V
CC
to V
REF
. The
external resistor creates a voltage divider between V
CC
and
V
REF
as shown in Figure 6. If desired, an appropriate
external voltage may be applied rather than using a resistor.
The smaller the external resistor, implying a smaller voltage
difference from SD
LVL
to V
CC
, lowers the SD sensitivity.
Hence, larger input amplitude is required to assert SD.
"Typical Operating Characteristics" shows the relationship
between the input amplitude detection sensitivity and the
SD
LVL
setting resistor.
Hysteresis
The SY88883V provides typically 4.6dB SD electrical
hysteresis. By definition, a power ratio measured in dB is
10log(power ratio). Power is calculated as V
2
IN
/R for an
electrical signal. Hence, the same ratio can be stated as
20log(voltage ratio). While in linear mode, the electrical
voltage input changes linearly with the optical power and,
hence, the ratios change linearly. Therefore, the optical
hysteresis in dB is half the electrical hysteresis in dB given
in the data sheet. The SY88883V provides typically 2.3dB
SD optical hysteresis. As the SY88883V is an electrical
device, this data sheet refers to hysteresis in electrical terms.
With 4.6dB SD hysteresis, a voltage factor of 1.7 is required
to assert SD from its deassert level.
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