The GP2021 is a 12 channel C/A code baseband
correlator for use in NAVSTAR GPS and GLONASS satellite
navigation receivers. The GP2021 complements the GP2015
and GP2010 C/A code RF downconverters available from
Mitel Semiconductor.
The GP2021 is compatible with most 16 bit and 32 bit
microprocessors, especially those from Motorola and Intel,
with additional onchip support for the ARM60 32 bit RISC
processor. When the ARM60 is used, the onchip memory
management functions allow implementation of a full GPS
receiver with minimal external logic.
The GP2021 allows individual channel deactivation, for
systems not requiring full 12 channel operation, to save power
and processor loading. Receiver power may be further
conserved by reducing the supply voltage to 2.2V under
battery backup. Although all system functions are disabled,
the 32.768kHz oscillator and Real Time Clock are maintained
for the microprocessor to estimate satellite visibility at power
on to reduce signal acquisition time.
A development system called the GPS Architect is
available as a basis for receiver design using the GP2021 and
associated products.
FEATURES
s
12 Fully Independent Correlation Channels
s
1PPS UTC Aligned Timing Output
s
OnChip Dual UART and Real Time Clock
s
Compatible with most 16 and 32 bit Microprocessors
s
Memory Control Logic for ARM60 Microprocessor
s
Low Voltage, Low Current PowerDown Mode
s
Power Dissipation 150mW Typical
s
Compatible with GP2015 and GP2010 RF Front Ends
s
Battery Backup Voltage 2.2V (min)
APPLICATIONS
s
GPS Navigation Systems
s
High Integrity Combined GPSGLONASS Receivers
s
GPS Geodetic Receivers
s
Time Transfer Receivers
ORDERING INFORMATION
GP2021/IG/GQ1R
Fig.1 Pin connections - top view
GQ80
GP2021
PIN 1
PIN 1 IDENT
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DESCRIPTION
MULTI_FN_IO
POWER _GOOD
NRESET_OP
NARMSYS
XIN
XOUT
TXA
TXB
RXA
RXB
NROM / NC
NEEPROM / NC
NSPARE_CS / NC
V
DD
V
SS
NRAM / BC
NW0 / NC
NW1 / NC
NW2 / NC
NW3 / NC
NRD / NC
ARM_ALE / NC
DBE / NC
ACCUM_INT
MEAS_INT
NBW / WRPROG
NMREQ / DISCIP2
NOPC / NINTELMOT
NRW / DISCIP3
MCLK / NC
ABORT / MICRO_CLK
DISCIO
A22 / READ
VDD
VSS
A21 / NCS
A20 / WREN
A9
A8
A7
DESCRIPTION
A6
A5
A4
A3
A2
A1 / ALE_IP
A0 / NRESET_IP
D0
D1
D2
D3
D4
D5
D6
V
DD
V
SS
D7
D8
D9
D10
D11
D12
D13
D14
D15
PLL_LOCK
VDD
DISCOP
V
SS
CLK_T
CLK_I
V
SS
SAMPCLK
V
DD
NBRAM / DISCIP4
SIGN0
MAG1
SIGN1
MAG1
DISCIP1
PIN
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
DS4077 - 2.6 July 1996
GP2021
GPS 12 channel Correlator
Advance Information
RELATED PRODUCTS
PART
DESCRIPTION
DATASHEET
REFERENCE
GP2015
GPS Receiver RF Front End
DS4374
TQFP 48 package
GP2010
GlPS Receiver RF Front End
DS4056
PQFP 44 package
DW9255
35.42MHz SAW Filter
DS3861
P60ARM
32 bit RISC Microprocessor
DS3553
GPS Architect
GPS 12 Channel
DS4004
Receiver Development System
2
GP2021
TABLE OF CONTENTS
HEADING
PAGE
TYPICAL GPS RECEIVER
4
PIN DESCRIPTION
4
Differences between Real and Complex_Input Mode
7
FUNCTIONAL DESCRIPTION
7
12 CHANNEL CORRELATOR
8
Clock Generator
8
Timebase Generator
8
Status Registers
9
Sample Latches
9
Address Decoder
9
Bus Interface
9
TRACKING MODULES
9
Carrier DCO
9
Code DCO
9
Carrier Cycle Counter
9
C/A Code Generator
9
Source Selector
10
Carrier Mixers
10
Code Mixers
10
Accumulate and Dump
10
Code Phase Counter
10
Code Slew Counter
10
Epoch Counter
11
PERIPHERAL FUNCTIONS
11
Dual UART
11
Receiver
11
Transmitter
11
Reset
11
Channel Loopback
12
Real Time Clock (RTC) and Watchdog
12
Power and Reset Control
12
Power Down Mode
12
Hardware Reset Generation
13
System Error Status Register
13
Discrete I/O
14
Digital System Test Interface
15
MICROPROCESSOR INTERFACE
15
General Interface Timing
15
Write Cycle to Read Cycle Timings
15
Write Cycle to Write Cycle Timings
15
Notes about Interface Timing Constraints
15
ARM System Mode
17
Address Map
17
Control Signals
17
ARM System Timing
17
Wait State Generation
17
Debug (Abort) Function
20
Standard Interface Mode
20
Control Signals
21
Motorola Style Interface
21
Intel 80186 Style Interface
21
Intel 486 Style Interface
21
Reset
21
Register Addressing
21
CONTROLLING THE GP2021
22
Search Operation
22
Carrier DCO Programming
22
Code DCO Programming
22
Code Generator Programming
22
Reading the Accumulated Data
22
Search on Other Code Phases
22
Data Bit Synchronisation
22
Reading the Measurement Data
22
Preset Mode
23
3
GP2021
Interrupts
23
Signal Path Delay (Introduced by Hardware Signal Processing)
23
Integrated Carrier Phase Measurement
23
Timemark Generation
24
GP2021 Register Map
25
Correlator Registers
26
Tracking Channel Registers
27
ACCUM_STATUS_A
28
ACCUM_STATUS_B
28
ACCUM_STATUS_C
28
CHx_ACCUM_RESET
29
CHx_CARRIER_CYCLE_COUNTER
29
CHx_CARRIER_CYCLE_HIGH
29
CHx_CARRIER_DCO_INCR_HIGH
29
CHx_CARRIER_DCO_PHASE
29
CHx_CODE_DCO_INCR_HIGH
30
CHx_CODE_DCO_PHASE
30
CHx_CODE_DCO_PRESET_PHASE
30
CHx_CODE_PHASE
30
CHx_CODE_SLEW
30
CHx_EPOCH_CHECK
31
CHx_EPOCH
31
CHx_EPOCH_COUNT_LOAD
31
CHx_I_TRACK, CHx_Q_TRACK, CHx_I_PROMPT,CHx_Q_PROMPT
31
CHx_SATCNTL
31
MEAS_STATUS_A
33
MULTI_CHANNEL_SELECT
33
PROG_ACCUM_INT
33
PROG_TIC_HIGH, PROG_TIC_LOW
34
RESET_CONTROL
34
STATUS
35
SYSTEM_SETUP
35
TEST_CONTROL
35
TIMEMARK_CONTROL
36
X_DCO_INCR_HIGH
37
Peripheral Functions Registers
37
Real Time Clock and Watchdog
37
RTC_LS, RTC_2ND, RTC_MS
37
CLOCK_RESET
37
WATCHDOG_RESET
37
DUART
38
CONFIG_A, CONFIG_B
38
STATUS_A, STATUS_B
38
RESET_A, RESET_B
38
TX_DATA_A, TX_DATA_B, RX_DATA_A, RX_DATA_B
38
TX_RATE_A, TX_RATE_B
39
System Control
39
WAIT_STATE
39
SYSTEM_CONFIG
39
SYSTEM_ERROR_STATUS
39
CHIP_REVISION
39
DATA_RETENT
40
General Control
40
IO_CONFIG
40
TEST_CONFIG
41
DATA_BUS_TEST
41
ABSOLUTE MAXIMUM RATINGS
41
Electrostatic Discharge Protection (ESD)
41
Crystal Specification
41
ELECTRICAL CHARACTERISTICS
42
PIN TYPES
44
TIMING CHARACTERISTICS
47
PACKAGE DETAILS
64
DETAILED DESCRIPTION OF REGISTERS
25
4
GP2021
TYPICAL GPS RECEIVER
Fig. 2 shows a typical GPS receiver employing a GP2010
RF frontend, a GP2021 correlator and an ARM60 32 bit RISC
microprocessor.
A single front end may be used, since all GPS satellites use
the same L1 frequency of 1575.42 MHz. However, in order to
achieve better sky coverage, it is sometimes desirable to use
more than one antenna. In this case, separate front ends will
be needed.
The RF section, GP2010, performs down conversion of
the L1 signal for digital baseband processing. The resultant
signal is then correlated in the GP2021 with an internally
generated replica of the satellite code to be received.
Individual codes for each channel may be selected
independently to enable acquisition and tracking of up to 12
different satellites simultaneously
The results of the correlations form the accumulated data
and are transferred to the microprocessor to give the
broadcast satellite data (the 'Navigation Message') and to
control the software signal tracking loops.
The GP2021 can be interfaced to one of two styles of front
end. In Real_Input mode, the front end supplies either a 1
(sign) or 2 (sign and magnitude) bit signal to either the
SIGN0/MAG0 or SIGN1/MAG1 inputs of the GP2021.
Alteratively, in Real_Input mode, 2 separate front ends can be
connected to a single GP2021 and selected under software
control. The GP2015 and GP2010 are Real_Input mode front
ends.
In Complex_Input mode, the front end is required to supply
Inphase (I) and Quadrature (Q) signals to the SIGN0/MAG0
and SIGN1/MAG1 inputs respectively. Hence, only a single
front end can be used with each GP2021 in Complex_Input
mode.
GP2010
SIGN
MAG
SAMPCLK
CLK_T
CLK_I
PLL_LOCK
10MHz
TCXO
TX/RX
SERIAL COMMS PORT
ACCUM_INT,MEAS_INT
12
CHANNEL
CORRELATOR
WREN
READ
MICRO_CLK
PERIPHERAL
FUNCTIONS
MEMORY
CONTROL
MEMORY
CONTROL
DATA
ADDR
ARM60
GP2021
L1 ANTENNA
Fig. 2 Block diagram of typical ARM based receiver
PIN DESCRIPTION
All V SS and V DD pins must be connected in order to ensure reliable operation. Any unused inputs must be tied High or Low.
The Table below describes the pin functions in Real_Input mode and assumes a master clock input frequency of 40MHz.
Those pins whose functions differ in Complex_Input mode are described at the end of the table.
Note that those pin names containing a `/' have dual functionality between ARM System and Standard Interface modes. The
Pin mnemonic for ARM System mode always precedes the `/'.
Pin No
Signal Name
Type
Description ARM System Mode
Description Standard Interface
Mode
15, 35,
V SS
-
Ground Pin
56, 69,
72
14, 34,
V DD
+
Power supply to device.
55, 67,
74
1
MULTI_FN_IO
I/O
Multifunction input / output. Its function is configured by the IO_CONFIG register.
After a GP2021 reset it acts as the Digital System Test Enable input. It can also
be configured as a discrete output, or a discrete input if certain conditions are met.
Can be configured as the TRIGGER
input to the DEBUG block in ARM
System mode.
5
GP2021
Pin No
Signal Name
Type
Description ARM System Mode
Description Standard Interface
Mode
2
POWER_GOOD
I
Power Monitor input. High for normal operation. Low forces the GP2021 into
Power Down mode.
3
NRESET_OP O
System Reset output (Active Low). Lasts for 4 MICRO_CLK cycles after all reset
conditions have cleared.
4
NARMSYS
I
Processor Mode Selection input. When Low, this input selects ARM System
mode. When High, Standard Interface mode is selected.
5
XIN
I
Crystal input connection to Real Time Clock.
6
XOUT
O
Crystal output connection from Real Time Clock.
7
TXA
O
Transmit Data output from Channel A of the Dual UART.
8
TXB
O
Transmit Data output from Channel B of the Dual UART.
9
RXA
1
Receive Data input to Channel A of the Dual UART. This pin acts as a master clock
input in Digital System Test mode.
10
RXB
I
Receive Data input to Channel B of the Dual UART. This pin acts as the Real Time
Clock reset in Digital System Test mode.
11
NROM / NC
O
ROM Chip Select output (Active Low).
Unused output. (Do not connect.)
12
NEEPROM / NC
O
EEPROM Chip Select output (Active Low)
Unused output. (Do not connect.)
13
NSPARE_CS / NC
O
Spare Chip Select output (Active Low).
Unused output. (Do not connect.)
16
NRAM / NC
O
RAM Chip Select output (Active Low).
Unused output. (Do not connect.)
17
NW0 / NC
O
Byte 0 Write Strobe output (Active Low).
Unused output. (Do not connect.)
18
NW1 / NC
O
Byte 1 Write Strobe output (Active Low).
Unused output. (Do not connect.)
19
NW2 / NC
O
Byte 2 Write Strobe output (Active Low).
Unused output. (Do not connect.)
20
NW3 / NC
O
Byte 3 Write Strobe output (Active Low).
Unused output. (Do not connect.)
21
NRD / NC
O
Read Data Strobe output (Active Low).
Unused output. (Do not connect.)
22
ARM_ALE / NC
O
ALE output to the microprocessor
Unused output. (Do not connect.)
(Active High). Controls the transparent
latches at the microprocessor address
outputs.
23
DBE / NC
O
Data Bus Enable output to the
Unused output. (Do not connect.)
microprocessor. When Low, places the
microprocessor data bus drivers in a
high impedance state.
24
ACCUM_INT
O
A free running interrupt to the microprocessor. It allows control of data transfer
between the accumulators in the correlator and the microprocessor. It is active
Low when configured for ARM System mode or Motorola mode and is active High
in Intel mode.
25
MEAS_INT
O
An interrupt to the microprocessor. It allows control of measurement data transfer
between the correlator and the microprocessor. It is active Low when configured
for ARM System mode or Motorola mode and is active High in Intel mode.
26
NBW / WRPROG
I
Byte/Word input from the
WriteRead Program input. In Intel
microprocessor. Low indicates a byte
mode, High selects 486 style
transfer, and High a word transfer.
interface and Low 186 style.
Unused in Motorola mode
27
NMREQ / DISCIP2
I
Memory Request input from the
Multipurpose discrete input.
microprocessor. Low indicates that the
microprocessor requires a memory
access during the following cycle.
28
NOPC / NINTELMOT
I
Opcode fetch input from the
High selects Motorola mode and
microprocessor. Low indicates that an
Low Intel mode.
instruction is being fetched and High
that data is being transferred.
29
NRW / DISCIP3
I
Read/Write Select input from the
Multipurpose discrete input.
microprocessor. Low indicates a read
cycle and High a write cycle.
30
MCLK / NC
O
Microprocessor Clock output
Unused output. (Do not connect.)
(nominally 20MHz). Its phases can be
stretched under control of the
Microprocessor Interface.
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