4-188

MH89790B

Preliminary Information

Figure 2 - Pin Connections

Pin Description

Pin #

Name

Description

Internal Connection. Leave open circuit.

E2o

2048 kHz Extracted Clock (Output): This clock is extracted by the device from the
received signal. It is used internally to clock in data received at RxT and RxR.

D.C. Power Input. (+5V).

RxA

Receive A (Output): The bipolar CEPT signal received by the device at the RxR and
RxT inputs is converted to a unipolar format and output at this pin.

6
7

RxT

RxR

Receive Tip and Receive Ring Inputs. The AMI receive signal is input to these pins.
Both inputs should be connected to a center-tapped, center-grounded transformer.If the
receive side of the device is not used, these pins must be tied to ground through 1k

resistors.

RxB

Receive B (Output): The bipolar CEPT signal received by the device at the RxR and
RxT inputs is converted to a unipolar format and output at this pin.

No Connection.

CSTi1

Control ST-BUS Input #1: A 2048 kbit/s stream that contains channel associated
signalling, frame alignment and diagnostic functions.

CSTi0

Control ST-BUS Input #0: A 2048 kbit/s stream that contains 30 per channel control
words and two Master Control Words.

E8Ko

8 kHz Extracted Clock (Output): An 8 kHz output generated by dividing the extracted
2048 kHz clock by 256 and aligning it with the received CEPT frame. The 8 kHz signal
can be used for synchronizing the system clock to the extracted 2048 kHz clock. Only
valid when device achieves synchronization (goes low during a loss of signal or a loss
of basic frame synchronization condition).

E8Ko goes to high impedance when 8kHzSEL = 0 in MCW2.

XCtl

External Control (Output): An uncommitted external output pin which is set or reset via
bit 1 in Master Control Word 2 on CSTi0. The state of XCtl is updated once per frame.

XSt

External Status: The state of this pin is sampled once per frame and the status is
reported in bit 1 of the Master Status Word 1 on CSTo.

CSTo

Control ST-BUS Output: A 2048 kbit/s serial control stream which provides the 16
signalling words, two Master Status Words, Phase Status Word and CRC Error Count.

E2o

VDD

RxA

RxT

RxR

RxB

CSTi1
CSTi0

E8Ko

XCtl

XSt

CSTo

NC
LOS
NC
NC
NC
NC
VSS
NC
DSTo
NC
OUTB
NC
RxMF

ADl

DSTi

C2i

E2o

F0i

TxMF

OUTA

PADo
TxG
PADi

VSS

2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

4-189

Preliminary Information

MH89790B

ADI

Alternate Digit Inversion (Input): If this input is high, the CEPT timeslots which are
specified on CSTi0 as voice channels are ADI coded and decoded. When this bit is low
it disables ADI coding for all channels. This feature allows either ADI or non-ADI codecs
to be used on DSTi and DSTo. Internally pulled with a 4.7k

resistor to +V

DSTi

Data ST-BUS Input: This pin accepts a 2048 kbit/s serial stream which contains the 30
PCM or data channels to be transmitted on the CEPT trunk.

C2i

2048 kbit/s System Clock (Input): The master clock for the ST-BUS section of the
chip. All data on the ST-BUS is clocked in on the falling edge of the C2i and output on the
rising edge. The falling edge of C2i is also used to clock out data on the CEPT PCM 30
transmit link.

E2o

2048 kHz Extracted Clock (Output): Internally connected to pin 3.

F0i

Frame Pulse Input: The ST-BUS frame synchronization signal which defines the
beginning of the 32 channel frame.

Ground. D.C. Power Return.

PADi

PAD Input: Input to the symmetrical resistive 75 ohm T-type line matching circuit. In a
typical application connect this input to the output of the line driving transformer.

TxG

Transmit Ground: Common point of the T-type PAD circuit. Connect to GND in a typical
application.

PADo

PAD Output: Output from the T-type PAD circuit. Output impedance of the PAD is pure
resistive 75

OUTA

Output A (Open Collector Output): This is the output of the CEPT transmitter. It is
suitable for use with an external pulse transformer to generate the transmit bipolar line
signal.

TxMF

Transmit Multiframe Boundary (Input): This input can be used to set the channel
associated and CRC transmitted multiframe boundary (clear the frame counters). If a
transmit multiframe signal is not being generated externally to the device, the MH89790B
will internally generate its own multiframe when this pin is tied high.

RxMF

Received Multiframe Boundary (Output): An output pulse delimiting the received
multiframe boundary. (This multiframe is not related to the received CRC multiframe.)

No Connection.

OUTB

Output B (Open Collector Output): Output of the CEPT transmitter. It is suitable for
use with an external pulse transformer to generate the transmit bipolar line signal.

No Connection.

DSTo

Data ST-BUS Output: A 2048 kbit/s serial output stream which contains the 30 PCM or
data channels received from the CEPT line.

No Connection.

Ground. D.C. Power Return.

34 - 37

No Connection.

LOS

Loss of Signal (Output): This pin goes High when 128 contiguous ZEROs are received
on the RxT and RxR inputs. When LOS is High, RxA and RxB are forced High. LOS is
reset when 64 ONEs are received in a two E1-frame period.

39 - 40

No Connection.

Pin Description (Continued)

Pin #

Name

Description

4-190

MH89790B

Preliminary Information

Functional Description

The MH89790B is a digital trunk interface
conforming to CCITT Recommendation G.704 for
PCM 30 and I.431 for ISDN. It includes features
such as insertion and detection of synchronization
patterns, optional cyclical redundancy check
(CRC-4) and far end error performance reporting,
HDB3 decoding and optional coding, channel
associated or common channel signalling,
programmable digital attenuation, and a two frame
received elastic buffer. The MH89790B can also
monitor several conditions on the CEPT digital trunk
which include the following: Loss of Signal (LOS)
indication, frame and multiframe synchronization,
received all 1's alarms, data slips, as well as near
and far end framing and CRC errors.

The system interface to the MH89790B is a serial
bus that operates at 2048 kbit/s known as the
ST-BUS. This serial stream is divided into 125 µs
frames that are made up of 32 x 8 bit channels.

The line interface to the MH89790B consists of split
phase unipolar inputs and outputs which are
supplied from/to a bipolar line receiver/driver,
respectively.

CEPT Interface

The CEPT frame format consists of 32, 8 bit
timeslots. Of the 32 timeslots in a frame, 30 are
defined as information channels, timeslots 1-15 and
17-31 which correspond to telephone channels 1-30.
An additional data channel may be obtained by
placing the device in common channel signalling

mode. This allows use of timeslot 16 for 64 kbit/s
common channel signalling. Synchronization is
included within the CEPT bit stream in the form of a
bit pattern inserted into timeslot 0. The contents of
timeslot 0 alternate between the frame alignment
pattern and the non-frame alignment pattern as
described in Figure 3 below. Bit 1 of the frame
alignment and non-frame alignment bytes have
provisions for additional protection against false
synchronization or enhanced error monitoring. This
is described in more detail in the following section.

In order to accomplish multiframe synchronization, a
16 frame multiframe is defined by sending four zeros
in the high order quartet of timeslot 16 frame 0, i.e.,
once every 16 frames (see Figure 4). The CEPT
format has four signalling bits, A, B, C and D.
Signalling bits for all 30 information channels are
transmitted in timeslot 16 of frames 1 to 15. These
timeslots are subdivided into two quartets (see Table
6).

Cyclic Redundancy Check (CRC)

An optional cyclic redundancy check (CRC) has
been incorporated within CEPT bit stream to provide
additional protection against simulation of the frame
alignment signal, and/or where there is a need for an
enhanced error monitoring capability. The CRC
process treats the binary string of ones and zeros
contained in a submultiframe (with CRC bits set to
binary zero) as a single long binary number. This
string of data is first multiplied by x

then divided by

the polynomial x

+x+1. This process takes place at

both the transmitter and receiver end of the link. The
remainder calculated at the receiver is compared to
the one received with the data over the link. If they

Figure 3 - Allocation of Bits in Timeslot 0 of the CEPT Link

Note 1 : With CRC active, this bit is ignored.
Note 2 : With SiMUX active, this bit transmits SMF CRC results in frames 13 and 15.
Note 3 : Reserved for National use.

Figure 4 - Allocation of Bits in Timeslot 16 of the CEPT Link

Bit Number

Timeslot 0 containing the
frame alignment signal

Reserved for
International
use

(1)

Timeslot 0 containing the
non-frame alignment signal

Reserved for
International
use

(2)

Alarm indication to the
remote PCM multiplex
equipment

See

Note

See

Note

See

Note

See

Note

See

Note

Timeslot 16 of frame 0

Timeslot 16 of frame 1

· · ·

Timeslot 16 of frame 15

0000

XYXX

ABCD bits for

telephone
channel 1

(timeslot 1)

ABCD bits for

telephone

channel 16

(timeslot 17)

ABCD bits for

telephone

channel 15

(timeslot 15)

ABCD bits for

telephone

channel 30

(timeslot 31)

4-191

Preliminary Information

MH89790B

are the same, it is of high probability that the
previous submultiframe was received error free.

The CRC procedure is based on a 16 frame
multiframe which is divided into two 8 frame
submultiframes (SMF). The frames which contain
the frame alignment pattern contain the CRC bits, C

to C

respectively, in the bit 1 position. The frame

which contains the non-frame alignment pattern
contains within the bit 1 position, a 6 bit CRC
multiframe alignment signal and two spare bits (in
frames 13 and 15) which are used for CRC error
performance reporting (refer to Figure 5). During the
CRC encoding procedure the CRC bit positions are
initially set at zero. The remainder of the calculation
is stored and inserted into the respective CRC bits of
the next SMF. The decoding process repeats the
multiplication/division process and compares the
remainder with the CRC bits received in the next
SMF.

The two spare bits (denoted Si1 and Si2 in Figure 5)
following the 6-bit CRC multiframe alignment signal
can be used to monitor far-end error performance.
The results of the CRC-4 comparisons for the
previously received SMFII and SMFI are encoded
and transmitted back to the far end in the Si bits
(refer to Table 1).

ST-BUS Interface

The ST-BUS is a synchronous time division
multiplexed serial bus with data streams operating at
2048 kbit/s and configured as 32, 64 kbit/s channels

(refer Figure 6). Synchronization of the data transfer
is provided from a frame pulse which identifies the
frame boundaries and repeats at an 8 kHz rate.
Figure 2 shows how the frame pulse (F0i)
defines the ST-BUS frame boundaries. All data is
clocked into the device on the falling edge of the
2048 kbit/s clock (C2i), while data is clocked out on
the rising edge of the 2048 kbit/s clock at the start of
the bit cell.

Table 1. Coding of Spare Bits Si1 and Si2

Si1 bit
(frame

13)

Si2 bit
(frame

15)

Meaning

CRC results for both SMFI, II are
error free.

CRC result for SMFII is in error.
CRC result for SMFI is error free.

CRC result for SMFII is error free.
CRC result for SMFI is in error.

CRC results for both SMFI, II are
in error.

Figure 5 - CRC Bit Allocation and Submultiframing

Note 1 : Remote Alarm. Keep at 0 for normal operation.
Note 2 : Reserved for National use. Keep at 1 for normal operation.
Note 3 : Used to monitor far-end CRC error performance.

Multiple Frame

Component

Frame Type

CRC

Frame #

Timeslot Zero

Frame Alignment Signal

Non-Frame Alignment Signal

(1)

(2)

Frame Alignment Signal

Non-Frame Alignment Signal

(1)

(2)

Frame Alignment Signal

Non-Frame Alignment Signal

(1)

(2)

Frame Alignment Signal

Non-Frame Alignment Signal

(1)

(2)

Frame Alignment Signal

Non-Frame Alignment Signal

(1)

(2)

Frame Alignment Signal

Non-Frame Alignment Signal

(1)

(2)

Frame Alignment Signal

Non-Frame Alignment Signal

Si1

(3)

(1)

(2)

Frame Alignment Signal

Non-Frame Alignment Signal

Si2

(3)

(1)

(2)

indicates position of CRC-4 multiframe alignment signal

4-192

MH89790B

Preliminary Information

Figure 6 - ST-BUS Stream Format

CHANNEL

BIT

CHANNEL

BIT

· · ·

Least
Significant
Bit (Last)

Most

Significant

Bit (First)

(8/2.048)

125

Data Input (DSTi)

The MH89790B receives information channels on
the DSTi pin. Of the 32 available channels on this
serial input, 30 are defined as information channels.
They are channels 1-15 and 17-31. These 30
timeslots are the 30 telephone channels of the CEPT
format numbered 1-15 and 16-30.

Timeslot 0 and 16 are unused to allow the
synchronization and signalling information to be
inserted, from the Control Streams (CSTi0 and
CSTi1). The relationship between the input and
output ST-BUS stream and the CEPT line is

illustrated in Figures 7 to 11. In common channel
signalling mode timeslot 16 becomes an active
channel. In this mode channel 16 on DSTi is
transmitted on timeslot 16 of the CEPT link
unaltered. This mode is activated by bit 5 of channel
31 of CSTi0.

Control

Input 0 (CSTi0)

All the necessary control and signalling information
is input through the two control streams. Control
ST-BUS input number 0 (CSTi0) contains the control
information that is associated with each information
channel. Each control channel contains the per
channel digital attenuation information, the individual

Table 2. Per Channel Control Word: Data Format for CSTi0 Channels 0-14, and 16-30

BIT

NAME

DESCRIPTION

DATA

Data Channel: If `1`, then the controlled timeslot on the CEPT 2048 kbit/s link is treated as a
data channel; i.e., no ADI encoding or decoding is performed on transmission or reception,
and digital attenuation is disabled. If `0`, then the state of the ADI pin determines whether or
not ADI encoding and decoding is performed.

LOOP

Per-Channel Loopback: If `1`, then the controlled timeslot on the transmitted CEPT 2048
kbit/s link is looped internally to replace the data on the corresponding received timeslot. If
`0`, then this function is disabled. This function only operates if frame synchronization is
received from the CEPT link. If more than one channel is looped per frame only the first one
will be active.

5,4,3

RXPAD4,2,1

Receive Attenuation Pad: Per timeslot receive attenuation control bits.

RXPAD4

0
0
0
0
1
1
1
1

RXPAD2

0
0
1
1
0
0
1
1

RXPAD1

0
1
0
1
0
1
0
1

Gain (dB)

-1
-2
-3
-4
-5
-6

2,1,0

TXPAD4,2,1

Transmit Attenuation Pad: Per timeslot transmit attenuation control bits.

TXPAD4

0
0
0
0
1
1
1
1

TXPAD2

0
0
1
1
0
0
1
1

TXPAD1

0
0
1
0
1
0
1
0

Gain (dB)

-1
-2
-3
-4
-5
-6

4-193

Preliminary Information

MH89790B

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4-194

MH89790B

Preliminary Information

Table 3. Master Control Word 1 (MCW1): Data Format for CSTi0 Channel 15

Table 4. Master Control Word 2 (MCW2): Data Format for CSTi0 Channel 31

Table 5. Multiframe Alignment Signal:Data Format for CSTi1Channel 0 on the Transmitted CEPT Link

BIT

NAME

DESCRIPTION

(N/A)

Keep at `1` for normal operation.

LOOP16

Channel 16 Loopback: If `1`, then timeslot 16 on the transmitted CEPT 2048 kbit/s link is
looped internally to replace the data received on timeslot 16. If `0,` then this function is
disabled.
This function only operates if frame synchronization is received from the CEPT link and only a
single timeslot can be looped within the frame.

5,4

(N/A)

Keep at `1` for normal operation.

3,2,

& 0

NDBD, NDBC,

NDBB

& NDBA

Signalling Bit Debounce: If `1`, then no debouncing is applied to the received A, B, C or D
signalling bits. If `0`, then the received A, B, C or D signalling bits are debounced for between
6 and 8 ms.

BIT

NAME

DESCRIPTION

(N/A)

Keep at `1` for normal operation.

(N/A)

Keep at `0` for normal operation.

CCS

Common Channel Signalling: If 1, then the MH89790B operates in its common channel
signalling mode. Channel 16 on the DSTi pin is transmitted on timeslot 16 of the CEPT link, and
timeslot 16 from the received CEPT link is output on channel 16 on the DSTo pin. Channel 15 on
the CSTi0 pin contains the information for the control of timeslot 16. Channels 0 to 15 on CSTi1
and CSTo are unused.
If `0`, the device is in channel associated signalling mode where channel 16 is used to transmit
the ABCD signalling bits.

8kHzSEL

8kHz Select: If `1`, then an 8 kHz signal synchronized to the received CEPT 2048 kbit/s link is
output on the E8Ko pin. This feature is only valid when frame synchronization is received from
the CEPT link.
If `0`, then the E8Ko pin goes into its high impedance state.

TXAIS

Transmit Alarm Indication Signal:
If `1`, then an all 1' s alarm signal is transmitted on all timeslots.
If `0`, then the timeslots functions normally.

TXTS16AIS

Transmit Timeslot 16 Alarm Indication Signal:
If `1`, then an all 1's alarm signal is transmitted on timeslot 16.
If `0`, then timeslot 16 functions normally.

XCtl

External Control:
If `1`, then the XCtl pin is driven high.
If `0`, then the XCtl pin is driven low.

(N/A)

(unused)

BIT

NAME

DESCRIPTION

7-4

MA1-4

Transmit Multiframe Alignment Bits 1 to 4: These bits are transmitted on the CEPT 2048
kbit/s link in bit positions 1 to 4 of timeslot 16 of frame 0 of the multiframe. They should be kept at
`0` to allow multiframe alignment to be detected.

This bit is transmitted on the CEPT 2048 kbit/s link in bit position 5 of timeslot 16 of frame 0 of the
multiframe. It is a spare bit which should be kept at `1` if unused.

This bit is transmitted on the CEPT 2048 kbit/s link in bit position 6 of timeslot 16 of frame 0 of the
multiframe. It is used to indicate the loss of multiframe alignment to the remote end of the link. A
`1` on this bit is the signal that multiframe alignment on the received link has been lost. A `0'
indicates that multiframe alignment is detected.

1,0

X2,X3

These bits are transmitted on the CEPT 2048 kbit/s link in bit positions 7 and 8 respectively, of
timeslot 16 of frame 0 of the multiframe. They are spare bits which should be kept at `1` if unused.

4-195

Preliminary Information

MH89790B

loopback control bit, and the voice or data channel
identifier, see Table 2. When a channel is in data
mode (B7 is high) the digital attenuation and
Alternate Digit Inversion are disabled. It should be
noted that the control word for a given information
channel is input one timeslot early, i.e., channel 0 of
CSTi0 controls channel 1 of DSTi. Channels 15 and

31 of CSTi0 contain Master Control Words 1 and 2
(MCW1, MCW2) which are used to set up the
interface feature as seen by the respective bit
functions of Tables 3 and 4.

Table 6. Channel Associated Signalling: Data Format for CSTi1 Channels 1 to 15

Table 7. Frame-Alignment Signal: Data Format for CSTi1 Channel 16

Table 8. Non-Frame-Alignment Signal: Data Format for CSTi1 Channel 17

BIT

NAME

DESCRIPTION

7,
6,

& 4

A(N),
B(N),

C(N)

& D(N)

Transmit Signalling Bits for Channel N: These bits are transmitted on the CEPT 2048 kbit/s
link in bit positions 1 to 4 of timeslot 16 in frame N, and are the A, B, C and D signalling bits
associated with telephone channel N. The value of N lies in the range 1 to 15 and refers to the
channel on the CSTi1 channel from which the bits are sourced, the telephone channel with which
the bits are associated and the frame on the CEPT link on which the bits are transmitted. For
example, the bits input on the CSTi1 pin on channel 3 are associated with telephone channel 3,
which is timeslot 3 of the CEPT link, and are transmitted on bits positions 1 to 4 of timeslot 16 in
frame 3 of each multiframe on the CEPT link . If bits B, C or D are not used they should be given
the values `1, 0` and `1` respectively. The combination `0000` for ABCD bits should not be used for
telephone channels 1 to 15 as this would interfere with multiframe alignment.

3,
2,

& 0

A(N+15),
B(N+15),

C(N+15)

& D(N+15)

Transmit Signalling Bits for Channel N+15: These bits are transmitted on the CEPT 2048
kbit/s link in bit positions 5 to 8 of timeslot 16 in frame N, and are the A, B, C and D signalling bits
associated with telephone channel N+15. The value of N lies in the range 1 to 15 and refers to
both the channel on the CSTi1 stream where the bits are supplied and the frame on the CEPT
link on which the bits are transmitted, and indirectly indicates the telephone channel with which
the bits are are associated. For example, the bits input on the CSTi1 pin on channel 3 are
associated with telephone channel 18, which is timeslot 19 of the CEPT link, and are transmitted
in bits positions 5 to 8 of timeslot 16 in frame 3 of each multiframe on the CEPT link .

BIT

NAME

DESCRIPTION

IU0

International Use 0: When CRC is disabled, this bit is transmitted on the CEPT 2048 kbit/s link
in bit position 1 of timeslot 0 of frame-alignment frames . It is reserved for international use and
should be kept at `1' when not used. If CRC is enabled, this bit is not used.

6-0

FAF2-8

Transmit Frame Alignment Signal Bits 2 to 8: These bits are transmitted on the CEPT 2048
kbit/s link in bit positions 2 to 8 of timeslot 0 of frame-alignment frames. These bits form the
frame alignment signal and should be set to `0011011`.

BIT

NAME

DESCRIPTION

IU1

International Use 1: When the CRC is disabled and SiMUX bit in MCW3 is disabled, this bit is
transmitted on the CEPT 2048 kbit/s link in bit position 1 of timeslot 0 of non-frame-alignment
frames . It is reserved for international use and should be kept at `1` when not used. If CRC is
enabled and SiMUX is disabled, this bit is transmitted in bit 1 of timeslot 0 for frame 13 and 15. If
both CRC and SiMUX are enabled, then this bit is not used.

NFAF

Transmit Non-Frame Alignment Bit: This bit is transmitted on the CEPT 2048 kbit/s link in bit
position 2 of timeslot 0 of non-frame-alignment frames . In order to differentiate between
frame-alignment frames and non-frame-alignment frames, this bit should be kept at `1`.

ALM

Non-Frame Alignment Alarm: This bit is transmitted on the CEPT 2048 kbit/s link in bit position
3 of timeslot 0 of non-frame-alignment frames . It is used to signal an alarm to the remote end of
the CEPT link. The bit should be set to `1` to signal an alarm and should be kept at `0` under
normal operation.

4-0

NU1-5

National Use: These bits are transmitted on the CEPT 2048 kbit/s link in bit positions 4 to 8 of
timeslot 0 of non-frame-alignment frames . These bits are reserved for national use, and on
crossing international borders they should be set to `1`.

4-196

MH89790B

Preliminary Information

Table 9. Master Control Word 3 (MCW3): Data Format for CSTi1 Channel 18

Table 10. Received Multiframe Alignment Signal: Data Format for CSTo Channel 0

BIT

NAME

DESCRIPTION

N/A

Keep at zero for normal operation.

SiMUX

When set to `1', this bit will cause the SMFI CRC result to be transmitted in the next outgoing Si1
bit in frame 13 and the SMFII CRC result to be transmitted in the next outgoing Si2 bit in frame
15.

RMLOOP

Remote Loopback: If set the RxT and RxR signals are looped to OUTA and OUTB,
respectively.

HDB3en

Enable HDB3 Encoding: A '1' will disable the HDB3 line coding and transmit the information
transparently.

Maint

Maintenance: A '1' will force a complete reframe if the CRC multiframe synchro- nization is not
achieved within 8 ms of frame synchronization. Reframe will also be generated if more than 914
CRC errors occur within a one second interval (CRC error counter is reset with every one second
interval). A '0' will disable this option.

CRCen

Enable Cyclical Redundancy Check: A '1' will enable the CRC generation on the transmit
data. A '0' will disable the CRC generator. The CRC receiver is always active regardless of the
state of CRCen.

DGLOOP

Digital Loopack: When set, the transmitted signal is looped around from DSTi to DSTo. The
normal received data is interrupted.

ReFR

Force Reframe: If set, for at least one frame, and then cleared the chip will begin to search for a
new frame position when the chip detects the change in state from high to low. Only the change
from high to low will cause a reframe, not a continuous low level.

BIT

NAME

DESCRIPTION

7-4

MA1-4

Receive Multiframe Alignment Bits 1 to 4: These are the bits which are received from the
CEPT 2048 kbit/s link in bit positions 1 to 4 of timeslot 16 of frame 0 of the multiframe. They
should all be `0`.

This is the bit which is received on the CEPT 2048 kbit/s link in bit position 5 of timeslot 16 of
frame 0 of the multiframe. It is a spare bit which should be `1` if unused. It is not debounced.

This is the bit which is received on the CEPT 2048 kbit/s link in bit position 6 of timeslot 16 of
frame 0 of the multiframe. It is used to indicate the loss of multiframe alignment at the remote end
of the link. A `1` on this bit is the signal that multiframe alignment at the remote end of the link has
been lost. A `0` indicates that multiframe alignment is detected. It is not debounced.

1,0

X2,X3

These are the bits which are received on the CEPT 2048 kbit/s link in bit positions 7 and 8
respectively, of timeslot 16 of frame 0 of the multiframe. They are spare bits which should be `1` if
unused. They are not debounced.

Control

Input 1 (CSTi1)

Control ST-BUS input stream number 1 (CSTi1)
contains the synchronization information and the A,
B, C & D signalling bits for insertion into timeslot 16
of the CEPT stream (refer to Tables 5 to 8). Timeslot
0 contains the four zeros of the multiframe alignment
signal plus the XYXX bits (see Figure 4). Channels 1
to 15 of CSTi1 contain the A, B, C & D signalling bits
as defined by the CEPT format (see Figure 4), i.e.,
channel 1 of CSTi1 contains the A, B, C & D bits for
DSTi timeslots 1 and 17. Channel 16 contains the
frame alignment signal, and channel 17 contains the
non-frame alignment signal (see Figure 3). Channel
18 contains the Master Control Word 3 (see Table 9).

Figure 10 shows the relationship between the control
stream (CSTi1) and the CEPT stream.

Control Output (CSTo)

Control ST-BUS output (CSTo) contains the
multiframe signal from timeslot 16 of frame 0 (see
Table 10). Signalling bits, A, B, C & D for each CEPT
channel are sourced from timeslot 16 of frames 1-15
and are output in channels 1-15 on CSTo , as shown

in Table 11. The frame alignment signal and
non-frame alignment signal, received from timeslot
0 of alternate frames are output in timeslots 16 and
17, as shown in Tables 12 and 13.

4-197

Preliminary Information

MH89790B

Table 11. Received Channel Associated Signalling: Data Format for CSTo Channels 1 to 15

Table 12. Received Frame Alignment Signal: Data Format for CSTo Channel 16

Table 13. Received Non-Frame Alignment Signal: Data Format for CSTo Channel 17

BIT

NAME

DESCRIPTION

7,
6,

& 4

A(N),
B(N),

C(N)

& D(N)

Receive Signalling Bits for Channel N: These are the bits which are received from the CEPT
2048 kbit/s link in bit positions 1 to 4 of timeslot 16 in frame N (frame #), and are the A, B, C and
D signalling bits associated with telephone channel N. The value of N lies in the range 1 to 15 and
refers to the channel on the CSTo stream on which the bits are output, the telephone channel with
which the bits are associated and the frame on the CEPT link on which the bits are received. For
example, the bits output on the CSTo stream on channel 3 are associated with telephone channel
3, which is timeslot 3 of the CEPT link, and are received on bits positions 1 to 4 of timeslot 16 in
frame 3 of each multiframe on the CEPT link . If bits B, C or D are not used they should have the
values `1, 0` and `1', respectively. The combination `0000` for ABCD bits should not be found for
telephone channels 1 to 15 as this implies interference with multiframe alignment.

3,
2,

& 0

A(N+15),
B(N+15),

C(N+15)

& D(N+15)

Receive Signalling Bits for Channel N+ 15: These are the bits which are received from the
CEPT 2048 kbit/s link in bit positions 5 to 8 of timeslot 16 in frame N, and are the A, B, C and D
signalling bits associated with telephone channel N+15. The value of N lies in the range 1 to 15
and refers to both the channel on the CSTo stream where the bits are output and the frame on the
CEPT link on which the bits are received, and indirectly indicates the telephone channel with
which the bits are are associated. The associated channel is N+15.
For example, the bits output on the CSTo stream on channel 3 are associated with telephone
channel 18, which is timeslot 19 of the CEPT link, and are received on bits positions 5 to 8 of
timeslot 16 in frame 3 of each multiframe on the CEPT link .

BIT

NAME

DESCRIPTION

IU0

International Use 0: This is the bit which is received from the CEPT 2048 kbit/s link in bit
position 1 of timeslot 0 of frame-alignment frames . It is reserved for the CRC remainder or for
international use.

6-0

FAF2-8

Frame Alignment Signal Bits 2 to 8: These are the bits which are received from the CEPT
2048 kbit/s link in bit positions 2 to 8 of timeslot 0 of frame-alignment frames . These bits form the
frame alignment signal and should have the values of `0011011`.

BIT

NAME

DESCRIPTION

IU1

International Use 1: This is the bit which is received from the CEPT 2048 kbit/s link in bit
position 1 of timeslot 0 of non-frame-alignment frames. It is reserved for CRC framing bits or
international bits.

NFAF

Receive Non-Frame Alignment Bit: This is the bit which is received from the CEPT 2048 kbit/s
link in bit position 2 of timeslot 0 of non-frame-alignment frames . This bit should be `1` in order to
differentiate between frame-alignment frames and non-frame-alignment frames.

ALM

Non-Frame Alignment Alarm: This bit is received from the CEPT 2048 kbit/s link in bit position
3 of timeslot 0 of non-frame-alignment frames . It is used to signal an alarm from the remote end
of the CEPT link. This bit should have the value `0` under normal operation and should go to `1 `to
signal an alarm.

4-0

NU1-5

National Use: These are the bits which are received on the CEPT 2048 kbit/s link in bit positions
4 to 8 of timeslot 0 of non-frame-alignment frames . These bits are reserved for national use, and
on crossing international borders they should have the value `1`.

4-198

MH89790B

Preliminary Information

Table 14. Master Status Word 1 (MSW1): Data Format for CSTo Channel 18

Table 15. Phase Status Word (PSW): Data Format for CSTo Channel 19

Table 16. CRC Error Count: Data Format for CSTo Channel 20

Table 17. Master Status Word 2 (MSW2): Data Format for CSTo Channel 21

BIT

NAME

DESCRIPTION

TFSYN

Frame Sync: This bit goes to `1` to indicate a loss of frame alignment synchronization by the
MH89790B. It goes to `0` when frame synchronization is detected.

MFSYN

Multiframe Sync: This bit goes to `1` to indicate a loss of multiframe synchronization by the
MH89790B. It goes to `0` when multiframe synchronization is detected.

ERR

Frame Alignment Error: This bit changes state when 16 or more errors have been detected in
the frame alignment signal. It will not change state more than once every 128 ms.

SLIP

Control Slip: This bit changes state when a slip occurs between the received CEPT 2048 kbit/s
link and the 2048 kbit/s ST-BUS.

RXAIS

Receive Alarm Indication Signal: This bit goes to `1` to signal that an all-ones alarm signal has
been detected on the received CEPT 2048 kbit/s link. It goes to '0' when the all-ones alarm
signal is removed.

RXTS16AIS

Receive Timeslot 16 Alarm Indication Signal: This bit goes to `1` to signal that an all-ones
alarm signal has been detected on channel 16 of the received CEPT 2048 kbit/s link. It goes to
`0` when the all-ones alarm signal is removed.

XSt

External Status: This bit contains the data sampled once per frame at the XSt pin.

N/A

(Unused).

BIT

NAME

DESCRIPTION

7 - 3

TxTSC

Transmit Timeslot Count: The value of these five bits indicate the timeslot count between the
ST-BUS frame pulse and the rising edge of E8Ko.

2 - 0

TxBTC

Transmit Bit Count: The value of these three bits indicate the bit position within the timeslot
count reported in TxTSC above.

BIT

NAME

DESCRIPTION

7 - 0

CERC

CRC Error Counter: This byte is the CRC error counter. The counter will wrap around once it
reaches FF count. If maintenance option is activated, the counter will reset once per second.

BIT

NAME

DESCRIPTION

Si2

The received Si bit in frame 15 is reported in this bit. Si2 will be updated after each
RXMF pulse (pin 23).

Si1

The received Si bit in frame 13 is reported in this bit. Si1 will be updated after each
RXMF pulse (pin 23).

5-4

Unused.

CRCTimer

CRC Timer: Transition from 1 to 0 indicates the start of one second interval in which CRC errors
are accumulated. This bit stay high for 8 ms.

CRCRef

CRC Reframe: A '1' indicates that the receive CRC multiframe synchronization could not be
found within the time out period of 8 ms after detecting frame synchronization. This bit will go low
if CRCSync goes low or if Maintenance is not activated.

CRCSync

CRC Sync: A '0' indicates that CRC multiframing has been detected.

FrmPhase

Frame Count: This is the ninth and most significant bit of the Phase Status Word (see Table 15).
If the phase status word is incrementing, this bit will toggle when the phase reading exceeds
ST-BUS channel 31, bit 7. If the phase word is decrementing, then this bit will toggle when the
reading goes below ST-BUS channel 0, bit 0.

4-199

Preliminary Information

MH89790B

Channel 18 contains a Master Status Word 1
(MSW1) which provides to the user information
needed to determine the operating condition of the
CEPT interface, i.e., frame synchronization,
multiframe synchronization, frame alignment byte
errors, slips, alarms, and the logic of the external
status pin (see Table 14). Figure 11 shows the
relationship between the control stream channels,
and the CEPT signalling channels in the multiframe.
The ERR bit in the Master Status Word 1 is an
indicator of the number of errored frame alignment
bytes that have been received in alternate timeslot
zero. The time interval between toggles of the ERR
bit can be used to evaluate the bit error rate of the
line according to the CCITT Recommendation G.732
(see section on Frame Alignment Error Counter).

Channel 19 contains the Phase Status Word (see
Table 15) which can be used to determine the phase
relationship between the ST-BUS frame pulse (F0i)
and the rising edge of E8Ko. This information could
be used to determine the long term trend of the
received data rate, or to identify the direction of a
slip.

Channel 20 contains the CRC error count (see Table
16). This counter will wrap around once terminal
count is achieved (256 errors). If the maintenance
option is selected (bit 3 of MCW3) the counter is
reset once per second.

Channel 21 contains the Master Status Word 2 (see
Table 17). This byte identifies the status of the CRC
reframe and CRC sync. It also reports the Si bits
received in timeslot 0 of frames 13 and 15 and
the ninth and most significant bit (b

) of the 9-bit

Phase Status Word.

Elastic Buffer

The MH89790B has a two frame elastic buffer at the
receiver which absorbs the jitter and wander in the
received signal. The received data is written into the
elastic buffer with the extracted E2o (2048 kHz)
clock and read out of the buffer on the ST-BUS side
with the system C2i (2048 kHz) clock (e.g., PBX
system clock). Under normal operating conditions,
in a synchronous network, the system C2i clock is
phase-locked to the extracted E2o clock. In this
situation every write operation to the elastic buffer is
followed by a read operation. Therefore, underflow
or overflow of data in the elastic buffer will not occur.

If the system clock is not phase-locked to the
extracted clock (e.g., lower quality link which is not
selected as the clock source for the PBX) then the
data rate at which the data is being written into the

device on the line side may differ from the rate at
which it is being read out on the ST-BUS side.

When the clocks are not phase-locked, two
situations can occur:

Case #1:

If the data on the line side is being written

in at a rate SLOWER than it is being read out on the
ST-BUS side, the distance between the write pointer
and the read pointer will begin to decrease over time.
When the distance is less than two channels, the
buffer will perform a controlled slip which will move
the read pointers to a new location 34 channels
away from the write pointer. This will result in the
REPETITION of the received frame.

Case #2:

If the data on the line side is being written

in at a rate FASTER than it is being read out on the
ST-BUS side, the distance between the write pointer
and the read pointer will begin to increase over time.
When the distance exceeds 42 channels, the elastic
buffer will perform a controlled slip which will move
the read pointer to a new location ten channels away
from the write pointer. This will result in the LOSS of
the last received frame.

Note that when the device performs a controlled slip,
the ST-BUS address pointer is repositioned so that
there is either a 10 channel or 34 channel delay
between the input CEPT frame and the output
ST-BUS frame. Since the buffer performs a
controlled slip only if the delay exceeds 42 channels
or is less than two channels, there is a minimum
eight channel hysteresis built into the slip
mechanism. The device can, therefore, absorb eight
channels or 32.5

s of jitter in the received signal.

There is no loss of frame synchronization, multiframe
synchronization or any errors in the signalling bits
when the device performs a slip.

Frame Alignment Error Counter

The MH89790B provides an indication of the bit error
rate found on the link as required by CCITT
Recommendation G.703. The ERR bit (Bit 5 of
MSW1) is used to count the number of errors found
in the frame alignment signal and this can be used to
estimate the bit error rate. The ERR bit changes
state when 16 errors have been detected in the
frame alignment signal. This bit can not change state
more than once every 128 ms, placing an upper limit
on the detectable error rate at approximately 10

-3

The following formula can be used to calculate the
BER:

4-200

MH89790B

Preliminary Information

where:

-is the number of bits in the frame

alignment signal (0011011).

-is the number of errored frame alignment

signals counted between changes of state
of the ERR bit.

4000

-is the number of frame alignment signals in

a one second interval.

This formula provides a good approximation of the
BER given the following assumptions:

1. The bit errors are uniformly distributed on the

line. In other words, every bit in every channel is
equally likely to get an error.

2. The errors that occur in channel 0 are bit errors.

If the first assumption holds and the bit error rate
is reasonable, (below 10

-3

) then the probability of

two or more errors in 7 bits is very low.

Attenuation ROM

All transmit and receive data in the MH89790B is
passed through the digital attenuation ROM
according to the values set on bits 5 - 0 of data
channels in the control stream (CSTi0). Data can be
attenuated on a per-channel basis from 1 to 6 dB for
both Tx and Rx data (refer Table 2).

Digital attenuation is applied on a per-channel basis
to the data found one channel after the control
information stored in the control channel CSTi0, i.e.,
control stream 0 channel 4 contains the attenuation
setting for data stream (DSTo) channel 5.

Signalling Bit RAM

The A, B, C, & D Bit RAM is used to retain the status
of the per-channel signalling bits so that they may be
multiplexed into the Control Output Stream (CSTo).
This signalling information is only valid when the
module is synchronized to the received data stream.
If synchronization is lost, the status of the signalling
bits will be retained for 6.0 ms provided the signalling
debounce is active.

Integrated into the signalling bit RAM is a debounce
circuit which will delay valid signalling bit changes for

BER=

16* number of times ERR bit toggles

7* 4000 * elapsed time in seconds

6.0 to 8.0 ms. By debouncing the signalling bits, a
bit error in the latter will not affect the call in
progress. (See Table 3, bits 3-0 of channel 15 on the
CSTi0 line.)

CEPT PCM 30 Format MUX

The internal multiplexer formats the data stream
corresponding to the CEPT PCM 30 format. The
multiplexer will use timeslots 1 to 15 and 17 to 31 for
data and timeslots 0 & 16 for the synchronization
and channel associated signalling.

The frame alignment and non-frame alignment
signals for timeslot zero are sourced by the control
stream input CSTi1 channel 16 and 17,
respectively. The most significant bit of timeslot zero
will optionally contain the cyclical redundancy check,
CRC multiframe signal and Si bits used for far-end
CRC monitoring.

Framing Algorithms

There are three distinct framers within the
MH89790B. These include a frame alignment signal
framer, a multiframe framer and a CRC framer.
Figure 12 shows the state diagram of the framing
algorithms. The dotted lines show optional features
which are enabled in the maintenance mode, that is
selected by setting Maint bit of the Master Control
Word 3 to "1".

The frame synchronization circuit searches for the
first frame alignment signal within the bit stream.
Once detected, the frame counters are set to find the
non-frame alignment signal. If bit 2 of the non-frame
alignment signal is not one, a new search is initiated,
else the framer will monitor for the frame alignment
in the next frame. If the frame alignment signal is
found, the device immediately declares frame
synchronization.

The multiframe synchronization algorithm is
dependent upon the state of frame alignment framer.
The multiframe framer will not initiate a search for
multiframe synchronization until frame sync is
achieved. Multiframe synchronization will be
declared on the first occurrence of four consecutive
zeros in the higher order quartet of channel 16.
Once multiframe synchronization is achieved, the
framer will only go out of synchronization after
detection of two errors in the multiframe signal or
loss of frame alignment synchronization.

The CRC synchronization algorithm is also
dependent on the state of the frame alignment

4-201

Preliminary Information

MH89790B

framer, but is independent of the multiframe
synchronization. The CRC framer will not initiate a
search for CRC framing signal until frame alignment
synchronization is achieved. Once frame alignment
synchronization is acquired, the CRC framer must
find two framing signals in bit 1 of the non-frame
alignment signal. Upon detection of the second CRC
framing signal the MH89790B will immediately go
into CRC synchronization. When maintenance
feature is enabled (maint bit = 1) the CRC framer will
force a complete reframe of the device if CRC frame
synchronization is not found within 8 ms or more
than 914 CRC errors occur per second.

Bipolar Line Receiver

The MH89790B receiver interfaces to the
transmission line through a pulse transformer which
splits the received AMI line signal into RxA and
RxB. These two signals are combined by an
internal NAND gate to form a new signal, which
represents received data. The received data is
clocked into the chip on the falling edge of E2o.
Figure 28 shows the functional timing of the bipolar
receiver.

Input impedance seen by the transmission line is
about 75 ohms, (transformer ratio 1:1:1 with
center-tap grounded) as required by G.703 for
coaxial cable. Attenuation of the transmission line
shall not exceed 6dB (at 1024 kHz) and attenuation
characteristics shall be close to the "square root of
F".

AF [dB] = AF

ref

[dB] *

where

AF -

attenuation at frequency f in dB

ref

- attenuation at frequency f

ref

in dB (in this

case 6 dB)

ref

reference frequency (in this case 1024
kHz)

f -

frequency in kHz

Input jitter tolerance of the MH89790B exceeds
minimum jitter tolerance as specified in CCITT I.431
and G.823 (see Figure 13).

ref

Figure 12 - Synchronization State Diagram

out of

synchronization

search for frame

alignment

signal

verify bit 2 of non-

frame alignment

signal

verify second

occurrence of frame

alignment signal

find two CRC

frame alignment

CRC synchronization

acquired

search for

multiframe align-

ment signal

multiframe synchro-

nization acquired

check for two errored

multiframe alignment

signals

Yes

# of consecutive incorrect
frame alignment signals = 3

time out > 8ms

- - - - - Only if the

maintenance
option is
selected

signals

number of CRC

errors > 914/s

frame synchroni-

zation acquired

4-202

MH89790B

Preliminary Information

Bipolar Line Transmitter

The MH89790B provides two open collector drivers,
OUTA and OUTB. These outputs are suitable for
driving a center-tapped pulse transformer. Figure 29
illustrates how the two outputs combine to create
opposite polarities of the AMI line code. Each output
steers the transformer into producing a pulse of the
opposite polarity.

Clock Extractor

The MH89790B contains a clock extraction circuit
that generates the E2o clock from the received data.
This clock is used to latch received data. The falling
edge of E2o is approximately aligned with the center
of the received data pulse. Alignment between these
signals can be disrupted by jitter and wander on the
received signal. Maximum tolerance of the
MH89790B to the input jitter is shown in Figure 13
relative to minimum jitter tolerance specified in
G.823 and I.431.

The extracted 8 kHz output (E8Ko) is derived from
E2o clock by dividing it by 256. It can be used by an
external phase-locked loop to generate the system
clock and frame pulse that is synchronized to the
network (see Figure 15).

Figure 13 - Input Jitter Tolerance of MH89790B

- Maximum jitter tolerance of receiver

- Minimum jitter tolerance specified by G.823 and I.431

AAAA

20 Hz

2.4 kHz

18 kHz

12 x 10

-8

1 Hz

10 Hz

100 Hz

1 K

10 K

100 K

36.90

20.50

10.0

8.00

2.50

1.5

1.00

0.54

(SINUSOIDAL)

0.20

P
E
A
K
·
T
O
·
P
E
A
K

J
I
T
T
E
R
S

JITTER FREQUENCY

AAAA

4-205

Preliminary Information

MH89790B

Table 18. Typical Parameters of the Input and Output Transformers

Parameter

(Units)

Through Hole

Units

TFS 2574-4

TFS 2915

-4

-5

Transformer Type

input

output

Inductance (mH)

(COM1-75

)

(COM1-120

)

>1.2
>1.9

0.49
0.81

>1.5

Turns Ratio

(COM1-75

):(A-F1):(B-F2)

(COM1-120

):(COM1-75

)

1:1:1

1·26:1

0·4:1:1

1·28:1

1·12:1:1

1·22:1

Line Impedance (

)

75/120

Operational Voltage (Volts)

+12

Dielectric Strength (Vrms)

1500

Line Side

System Side

COM1

120

Applications

ISDN Primary Rate User Network Interface

Typical examples of primary rate interfaces are high
capacity links from a PBX to a Central Office
Exchange or multiple links between PBX's in a large
private network. With the advent of Integrated
Services Digital Networks (ISDN) a limited set of
network interfaces is specified to allow equipment
from different vendors to operate in the network.
The MH89790B conforms to the ISDN S/T Primary
Rate reference point standard, which calls for 30 B
channels (64 kbit/s) and one D channel (64 kbit/s).
Figure 15 illustrates a typical application of the
MH89790B in an ISDN environment.

Three types of information are passed through serial
busses of the MH89790B:

USER DATA

- The data streams of the MH89790B

are shown connected to the MT8980 Digital
Crosspoint Switch. This allows voice and data
channels to be switched dynamically within the
system.

SIGNALLING -

Signalling information on the ISDN

primary rate interface is carried over the D-channel
using LAPD procedures. The ISDN D-channel is
created by placing the MH89790B in Common
Channel Signalling mode. The D-channel is tapped
off from the ST-BUS and connected to the MT8952
Protocoller Controller. It receives and transmits data
packets serially, in accordance with LAPD protocol
requirements.

CONTROL -

The MT8920B (STPA) provides

microprocessor access to directly control the
MH89790B through its transmit and receive dual port
RAMs. Status information can generate interrupts to
notify the system in case of slips, loss of
synchronization, alarms, violations, etc.

Interfacing to the Coaxial Cable Transmission
Line

Reliable operation of the CEPT link is directly related
to the type of transmission medium and method of
interfacing. Coaxial cables provide excellent
transmission mediums if used properly. One of the
most important things to remember is that the
receive end of the cable must not be connected to
ground, as shown in Figure 16. If both ends are

4-207

Preliminary Information

MH89790B

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

Timing is over recommended temperature & power supply voltages.
Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

Absolute Maximum Ratings*

Parameter

Symbol

Min

Max

Units

Supply Voltage with respect to V

-0.3

Voltage on any pin other than supplies

-0.3

+0.3

Current at any pin other than supplies

Storage Temperature

-40

°C

Package Power Dissipation

800

Recommended Operating Conditions

- Voltages are with respect to ground (V

) unless otherwise stated.

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Operating Temperature

°C

Supply Voltage

4.5

5.0

5.5

Input High Voltage

2.4

For 400 mV noise margin

1.2

RxT and RxR

Input Low Voltage

0.4

For 400 mV noise margin

0.3

RxT and RxR

DC Electrical Characteristics -

Clocked operation over recommended temperature ranges and power supply voltages.

Parameters

Sym

Min

Typ

Max

Units

Test Conditions

Supply Current

Outputs Unloaded

Input High Voltage

2.0

Digital Inputs

Input Low Voltage

0.0

0.8

Digital Inputs

Input Leakage Current

+10

Digital Inputs V

=0 toV

Output High Voltage

2.4

=10mA

Output High Leakage

500

= 0 to V

Output High Current

Source Current, V

=2.4V

Output Low Voltage

0.4

=2mA

OUTA or OUTB

0.25

=10mA

Output Low Current

Sink Current, V

=0.4V

Input Impedance RxT to RxR

319

AC Electrical Characteristics

- Capacitance

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Input Pin Capacitance

Output Pin Capacitance

4-216

MH89790B

Preliminary Information

Appendix

Control and Status Register Summary

Master Control Word 1 (MCW1) - CSTi0, Channel 15

Master Control Word 2 (MCW2) - CSTi0, Channel 31

Master Control Word 3 (MCW3) - CSTi1, Channel 18

Per Channel Control Word - CSTi0, Channels 0-14 and 16-30

Channel Associated Signalling - CSTi1, Channels N = 1 to 15

Frame Alignment Signal - CSTi1, Channel 16

Multiframe Alignment Signals - CSTi1, Channel 0

Non-Frame Alignment Signal - CSTi1, Channel 17

UNUSED

Keep at 1

LOOP16

1 Enabled

0 Disabled

UNUSED

Keep at 1

NDBD

1 No
Debounce

0 Debounce

NDBC

1 No

Debounce

0 Debounce

NDBB

1 No

Debounce

0 Debounce

NDBA

1 No

Debounce

0 Debounce

UNUSED

Keep at 1

UNUSED

Keep at 0

CCS

1 Common
Channel

0 Channel

Associated

8 kHz SEL

1 Enabled

0 Disabled

TXAIS

1 Alarm On

0 Alarm Off

TXTS16AIS

1 Alarm On

0 Alarm Off

XCTL

1 Set High

0 Cleared

UNUSED

Keep at 0

SiMUX

1 Enabled

0 Disabled

RMLOOP

1 Enabled

0 Disabled

HDB3en

1 Disabled

0 Enabled

Maint

1 Enabled

0 Disabled

CRCen

1 Enabled

0 Disabled

DGLOOP

1 Enabled

0 Disabled

ReFR

Device

reframes on

High to Low

Transition

DATA

1 No ADI

0 Enable ADI

LOOP

1 Enabled

0 Disabled

RxPAD4

RxPAD2

RxPAD1

TxPAD4

TxPAD2

TxPAD1

A(N)

Signalling Bit

B(N)

Signalling Bit

C(N)

Signalling Bit

D(N)

Signalling Bit

A(N+15)

Signalling Bit

B(N+15)

Signalling Bit

C(N+15)

Signalling Bit

D(N+15)

Signalling Bit

IUO

Should be

kept at 1

FAF2-8

Frame Alignment Signal - Keep at "0011011"

MA1-4

Multiframe Alignment Signal - Keep at "0000"

Spare Bit

Should be 1

1 Alarm On

0 Alarm off

X2, X3

Spare Bits - Should be 1

IU1

Reserved for

International

Used

NFAF

Keep at "1"

ALM

1 Alarm On

0 Alarm Off

NU1-5

Bits Reserved for National Use - Should be kept at "1"

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MH89790BN

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MH89790BN