4-223
Features
Complete primary rate 2048kb/s CEPT line
driver and receiver
Onboard pulse transformers for transmit and
receive
Meets latest ETSI requirements (ETSI ETS 300
011 (NET 5))
Inductorless clock recovery
Loss of signal indication/ polarity selection
Programmable polarity of extracted clock &
receive data
Single +5V operation
Compatible with all E1 framers
Small footprint area (<330mm
2
)
Applications
Primary rate ISDN network Interface
Multiplexer equipment
Private Network links
Isochronous LANS/WANS
Description
The Mitel MH89792 is a low cost E1 line driver/
receiver with clock extraction requiring no external
components. There are three versions available:
MH89792-1 for 120
twisted pair cable;
MH89792-2 for 75
co-axial links;
MH89792-3 for 100
digital twisted pair.
Figure 1 - Functional Block Diagram
TLA
TLB
RLA
RLB
VDD
VSS
TxA
TxB
E2o
LOSP
CLKF/
RxINV
RxA
RxB
LOS
RxD
CLKR
Line
Driver
Transmit
Isolation
Transformer
Polarity
Selection
Clock/Data
Clock
Recovery
Line
Receiver
6dB
Pad
Receive
Isolation
Transformer
EQUIPMENT SIDE
LINE SIDE
ISSUE 3
April 1995
Ordering Information
MH89792-1 20 Pin SIL Package
MH89792-2 20 Pin SIL Package
MH89792-3 20 Pin SIL Package
0
C to 70
C
MH89792
E1 Transceiver
Preliminary Information
4-224
MH89792
Preliminary Information
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
1
E2o
2048kHz Extracted clock (Output). This clock is extracted by the device from the received
signal. It is used internally to clock in data received from RLA and RLB.
2
V
DD
D.C. Power (Input) +5V supply
3
RxA
Receiver A (Output). The bipolar CEPT signal received by the device at RLA and RLB
inputs is converted to a unipolar format and output at this pin. This pin should be connected
to the positive receive pin of the framer.
4
RxB
Receiver A (Output). This pin should be connected to the negative receive gain pin of the
framer and provides a signal of the same format as RxA.
5
V
SS
Ground (Input). D.C. power return path.
6
RxD
Received Data (Output) This unipolar return to zero format signal is the product of RxA
and RxB logically "OR" ed and is required by some framers.
7
RxINV
RxA/RxB inversion (Input). A logic low applied to this pin will invert the outputs RxA and
RxB. A logic high should be applied if no inversion is required.
8
CLKF/
CLKR
E2o phase selection is achieved by use of this pin. A logic low provides E2o with a
falling edge coinciding with the centre of the data bit. A logic high provides E2o with a rising
edge.
9
LOS
Loss of signal (Output). This pin goes low when 128 continuous zeros are received on the
RLA and RLB inputs. When RxINV and LOS are low RxA and RxB are forced high. When
RxINV is high and LOS is low RxA and RxB are forced low. LOS is reset when 64 ones are
received in two dual E1 framer periods.
10
LOSP
Loss of signal Polarity (Input). A logic low applied to this pin will invert LOS. A logic high
should be applied when LOS is required.
11
NC
No connection. This pin is not fitted.
12
RLA
Received Line A (Input). The A wire or Tip Connection of the E1 receive line should be
connected to this pin.
13
RLB
Receive Line B (Input). The B wire or Ring connection of the E1 receive line should be
connected to this pin.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
E2o
VDD
RxA
RxB
VSS
RxD
RxINV
CLKF/CLKR
LOS
LOSP
NC
RLA
RLB
TLA
TLB
NC
NC
NC
TxA
TxB
Preliminary Information
MH89792
4-225
14
TLA
Transmit Line B (Output). The B wire of Ring connection of the E1 receive line should be
connected to this pin.
15
TLB
Transmit Line B (Output). The B wire or Tip connection of the E1 receive line should be
connected to this pin.
16
NC
No Connection. This pin is not fitted.
17
NC
No Connection. This pin is not fitted.
18
NC
No Connection. This pin is not fitted.
19
TXA
Transmit A (Input). A unipolar signal from the framer device used in conjunction with TxB
is used to generate the bipolar output signal.
20
TXB
Transmit B (Input). A unipolar signal from the framer device used in conjunction with TxA
is used to generate the bipolar output signal.
Pin Description (Continued)
Pin #
Name
Description
Functional Description
The MH89792 is a E1 digital trunk interface which
when used with an approved framer will conform to
CCITT recommendation G.703 for PCM30 and I.431
for the ISDN. The functions provided include line
driver and receive circuitry, inductorless clock
recovery, data and clock polarity selection and loss
of signal indication.
Bipolar Line Receiver
The MH89792 receiver interfaces to the transmission
line through an internal pulse transformer which
splits the received AMI lines signal into RxA and
RxB. These two signals are combined by internal
logic to form a new signal which represents the
received data, RxD. The signals RxA and RxB may
be inverted where required by applying a logic low
signal permanently to pin 7, (RxINV). RxD will not be
affected by use of this pin.
The input impedance seen by the transmission line is
about 120 ohms when using the -1 variant for twisted
pair applications, about 75 ohms when using the -2
variant for coaxial cable applications, and is about
100 ohms when using the -3 variant for digital
twisted pair applications.
Attenuation of the transmission line shall not exceed
6dB (at 1024kHz) and attenuation characteristics
shall be close to the "square root of f"
Af (dB) = AF
ref
(dB)*
f
f
ref
Where:
AF - attenuation at frequency f in dB
AF
ref
- attenuation at frequency f
ref
in dB (in kHz)
f
ref
- reference frequency (in this case 1024) kHz
f - frequency in kHz
Bipolar Line Transmitter
The MH89792 transmitter interfaces to the
transmission line through an internal pulse
transformer which combines the TxA and TxB data
into an AMI line coded signal. This is then passed
through the 6dB pad prior to being applied to the
line.
Clock Extractor
The MH89792 contains a clock extraction circuit
which generates the E2o clock from the received
data without the use of external crystals or a tunable
inductor.
The edge of the E2o extracted clock approximately
aligns with the centre of the received data pulse and
can be configured as either rising or falling edge by
the use of pin 8. (CLKF/CLKR).
Loss of Signal
The circuitry on the MH89792 is capable of detecting
128 continuous ZEROs received on RLA and RLB
and indicating this condition as a logic low on pin 9,
(LOS). When LOS and RxINV are low RxA and RxB
are forced high, when LOS is low and RxINV is high
RxA and RxB are forced low LOS will not reset until
64 ONEs are received in a two E1 frame period. LOS
may be inverted by applying a logic low to pin 10,
(LOSP).
4-226
MH89792
Preliminary Information
Figure 3a - Application Circuit
Figure 3b - Application Circuit
INT
DSTi
DSTo
CSTio
CSTo
CSTi1
XSt
TxA
TxB
RxD
RxA
RxB
E2i
C2i
F0i
LOS
TxA
TxB
RxD
RxA
E2o
RxINV
V
SS
V
DD
CLKF/
CLKR
RLB
RLA
TLB
TLA
RxB
Twisted Pair
+5V
MT9042
MT8979
MH89792-1
MT8941
LOSP
Coax Connection
-2 Version only
Coax Connection
-2 Version only
14
15
12
13
8
10
2
Twisted Pair
9
19
20
6
3
4
1
7
5
VDD
RESET
DSTi
DSTo
F0i
E8Ko
D0-7
AC0-4
R/W
CS
DS
IRQ
S/P
V
SS
TAIS V
DD
TxMF
TxA
TxB
RxA
RxB
E2i
C4i
33
2
26
31
32
8-15
18-22
23
24
25
7
36
37
27
29
30
42
43
35
16
41
1
+5
10K
19
20
3
4
1
2
12
14
15
13
9
8
7
10
+5
TxA
TxB
RxA
RxB
E2o
VDD
RLA
TLA
TLB
RLB
LOS
CLKF/CLKP
RXINV
LOSP
MH89792-1
0.1
NETWORK
CONNECTOR
MT9079
MT9042
4-227
Preliminary Information
MH89792
Figure 3c - Application Circuit
Figure 4 - Mechanical Data
PLL
FRAMER
ISOLATION BARRIER
MH89792
LINE
CONNECTORS
NETWORK
SIDE
1
20
SYSTEM
SIDE
NOTES:
X = Pin not fitted
Separation across barrier > 2mm recommended
.
2.0 + 0.040
(50.8 + 1.0)
0.56 Max
(14.2 Max)
0.27 Max
(6.9 Max)
0.010 + 0.002
(0.25 + 0.05)
0.1 Max
(2.5 Max)
Side View
*
0.05 + 0.01
(1.3 + 0.5)
*
*
*
0.05 + 0.02
(1.225 + 0.05)
0.020 + 0.005
(0.51 + 0.13)
0.100 + 0.010
(2.54 + 0.26)
0.18 + 0.02
(4.6 + 0.5)
1
Notes
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
* Dimensions to pin center &
tolerance non accumulative.
4-228
MH89792
Preliminary Information
Notes:
PDF 
ZIP