4-125

Features

Central office quality DTMF transmitter/
receiver

Low voltage operation (2.7-3.6V)

Adjustable guard time

Automatic tone burst mode

Call progress tone detection to -30dBm

Adaptive micro interface enables compatibility
with existing MT8880/MT8888 designs

DTMF transmitter/receiver power down via
register control

Applications

Credit card systems

Paging systems

Repeater systems/mobile radio

Interconnect dialers

Personal computers

Description

The MT88L89 is a monolithic DTMF transceiver with
call progress filter. It is fabricated in CMOS
technology offering low power consumption and high
reliability.

The receiver section is based upon the industry
standard MT8870 DTMF receiver while the
transmitter utilizes a switched capacitor D/A
converter for low distortion, high accuracy DTMF
signalling. Internal counters provide a burst mode
such that tone bursts can be transmitted with precise
timing. A call progress filter can be selected allowing
a microprocessor to analyze call progress tones.

The MT88L89 utilizes an adaptive micro interface,
which allows the device to be connected to a number
of popular microcontrollers with minimal external
logic. The MT88L89 provides enhanced power down
features. The transmitter and receiver may
independently be powered down via register control.

Ordering Information

MT88L89AE

20 Pin Plastic DIP

MT88L89AC

20 Pin Ceramic DIP

MT88L89AS

20 Pin SOIC

MT88L89AN

24 Pin SSOP

MT88L89AP

28 Pin PLCC

-40°C to +85°C

Figure 1 - Functional Block Diagram

TONE

IN+

IN-

OSC1

OSC2

Ref

ESt

St/GT

IRQ/CP

DS/RD

R/W/WR

RS0

D/A

Converters

Row and

Column

Counters

Transmit Data

Data

Bus

Buffer

Tone Burst
Gating Cct.

Oscillator

Circuit

Bias

Circuit

Control

Logic

Digital

Algorithm

and Code
Converter

Control

Logic

Steering

Logic

Status

Control

Receive Data

Interrupt

Logic

I/O

Control

Low Group

Filter

High Group

Filter

Dial

Tone
Filter

ISSUE 1

May 1995

MT88L89

3V Integrated DTMF Transceiver

with Adaptive Micro Interface

Advance Information

MT88L89

Advance Information

4-126

Figure 2 - Pin Connections

Pin Description

Pin #

Name

Description

IN+

Non-inverting op-amp input.

IN-

Inverting op-amp input.

Gain Select. Gives access to output of front end differential amplifier for connection of
feedback resistor.

Ref

Reference Voltage output (V

/2).

Ground (0V).

OSC1

Oscillator input. This pin can also be driven directly by an external clock.

OSC2

Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2
completes the internal oscillator circuit. Leave open circuit when OSC1 is driven
externally.

TONE

Output from internal DTMF transmitter.

R/W

(

)

(Motorola) Read/Write or (Intel) Write microprocessor input. TTL compatible.

Chip Select input. This signal must be qualified externally by either address strobe
(AS), valid memory address (VMA) or address latch enable (ALE) signal, see Figure 12.

RS0

Register Select input. Refer to Table 3 for bit interpretation. TTL compatible.

(

RD) (Motorola) Data Strobe or (Intel) Read

microprocessor input. Activity on this input is

only required when the device is being accessed. TTL compatible.

IRQ/CP Interrupt Request/Call Progress (open drain) output. In interrupt mode, this output

goes low when a valid DTMF tone burst has been transmitted or received. In call
progress mode, this pin will output a rectangular signal representative of the input signal
applied at the input op-amp. The input signal must be within the bandwidth limits of the
call progress filter, see Figure 8.

14-

18-

19-

D0-D3

Microprocessor data bus. High impedance when CS = 1 or DS =0 (Motorola) or RD = 1
(Intel). TTL compatible.

ESt

Early Steering output. Presents a logic high once the digital algorithm has detected a
valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt
to return to a logic low.

St/GT

Steering Input/Guard Time output (bidirectional). A voltage greater than V

TSt

detected

at St causes the device to register the detected tone pair and update the output latch. A
voltage less than V

TSt

frees the device to accept a new tone pair. The GT output acts to

reset the external steering time-constant; its state is a function of ESt and the voltage
on St.

1
2
3
4
5
6
7
8
9

20
19
18
17
16
15
14
13

IN+

IN-

VRef

VSS

OSC1
OSC2

TONE

R/W/WR

VDD
St/GT
ESt
D3
D2
D1
D0
IRQ/CP
DS/RD
RS0

1
2
3
4
5
6
7
8
9

10
11
12

24
23
22
21
20
19
18
17

IN+

IN-

VRef

VSS

OSC1
OSC2

TONE

R/W/WR

VDD
St/GT
ESt
D3
D2
D1
D0
NC
NC
IRQ/CP
DS/RD
RS0

24 PIN SSOP

20 PIN CERDIP/PLASTIC DIP/SOIC

28 PIN PLCC

5
6
7
8
9
10
11

25
24
23
22
21
20
19

VRef

VSS

OSC1
OSC2

/
R

I
N

t
/
G

/
W

I
R

/
C

NC
NC
NC
D3
D2
D1
D0

Advance Information

MT88L89

4-127

Functional Description

The MT88L89 Integrated DTMF Transceiver consists
of a high performance DTMF receiver with an
internal gain setting amplifier and a DTMF generator,
which employs a burst counter to synthesize precise
tone bursts and pauses. A call progress mode can
be selected so that frequencies within the specified
passband can be detected. The adaptive micro
interface allows microcontrollers, such as the
68HC11, 80C51 and TMS370C50, to access the
MT88L89 internal registers.

Power Down

The MT88L89 provides enhanced power down
functionality to facilitate minimization of supply
current consumption. DTMF transmitter and receiver
circuit blocks may be independently powered down
via register control. When asserted, RxEN control
bit powers down all analog and digital circuitry
associated solely with the DTMF and Call Progress
receiver. The TOUT control bit is used to disable the
transmitter and put all circuitry associated only with
the DTMF transmitter in power down mode. With the
TOUT control bit asserted, the TONE output pin is
held in a high impedance (floating) state. When both
power down control bits are asserted, circuits utilized
by both the DTMF transmitter and receiver are also
powered down. This includes the crystal oscillators,
and the V

Ref

generator. In addition, the IRQ , TONE

output and DATA pins are held in a high impedance
state.

Input Configuration

The input arrangement of the MT88L89 provides a
differential-input operational amplifier as well as a
bias source (V

Ref

), which is used to bias the inputs at

/2. Provision is made for connection of a

feedback resistor to the op-amp output (GS) for gain
adjustment. In a single-ended configuration, the
input pins are connected as shown in Figure 3.

Figure 4 shows the necessary connections for a
differential input configuration.

Receiver Section

Separation of the low and high group tones is
achieved by applying the DTMF signal to the inputs
of two sixth-order switched capacitor bandpass
filters, the bandwidths of which correspond to the low
and high group frequencies (see Table 1). The filters
also incorporate notches at 350 Hz and 440 Hz for
exceptional dial tone rejection. Each filter output is
followed by a single order switched capacitor filter
section, which smooths the signals prior to limiting.
Limiting is performed by high-gain comparators
which are provided with hysteresis to prevent
detection of unwanted low-level signals. The outputs
of the comparators provide full rail logic swings at
the frequencies of the incoming DTMF signals.

Figure 3 - Single-Ended Input Configuration

Figure 4 - Differential Input Configuration

IN+

IN-

Ref

VOLTAGE GAIN
(A

) = R

/ R

MT88L89

IN+

IN-

Ref

DIFFERENTIAL INPUT AMPLIFIER
C1 = C2 = 10 nF
R1 = R4 = R5 = 100 k

R2 = 60k

, R3 = 37.5 k

R3 = (R2R5)/(R2 + R5)

VOLTAGE GAIN
(A

diff) - R5/R1

INPUT IMPEDANCE

diff) = 2

+ (1/

MT88L89

Positive power supply (3V typ.).

8,9
16,

3,5,

10-11

23-

No Connection.

Pin Description

Pin #

Name

Description

MT88L89

4-128

0= LOGIC LOW, 1= LOGIC HIGH

Table 1. Functional Encode/Decode Table

Following the filter section is a decoder employing
digital counting techniques to determine the
frequencies of the incoming tones and to verify that
they correspond to standard DTMF frequencies. A
complex averaging algorithm protects against tone
simulation by extraneous signals such as voice while
providing tolerance to small frequency deviations
and variations. This averaging algorithm has been
developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of
interfering frequencies (third tones) and noise. When
the detector recognizes the presence of two valid
tones (this is referred to as the "signal condition" in
some industry specifications) the "Early Steering"
(ESt) output will go to an active state. Any
subsequent loss of signal condition will cause ESt to
assume an inactive state.

Steering Circuit

Before registration of a decoded tone pair, the
receiver checks for a valid signal duration (referred
to as character recognition condition). This check is
performed by an external RC time constant driven by
ESt. A logic high on ESt causes v

(see Figure 5) to

rise as the capacitor discharges. Provided that the
signal condition is maintained (ESt remains high) for
the validation period (t

GTP

), v

reaches the threshold

LOW

HIGH

DIGIT

697

1209

697

1336

697

1477

770

1209

770

1336

770

1477

852

1209

852

1336

852

1477

941

1336

941

1209

941

1477

697

1633

770

1633

852

1633

941

1633

TSt

) of the steering logic to register the tone pair,

latching 62its corresponding 4-bit code (see Table 1)
into the Receive Data Register. At this point the GT
output is activated and drives v

to V

. GT

continues to drive high as long as ESt remains high.
Finally, after a short delay to allow the output latch to
settle, the delayed steering output flag goes high,
signalling that a received tone pair has been
registered. The status of the delayed steering flag
can be monitored by checking the appropriate bit in
the status register. If Interrupt mode has been
selected, the IRQ/CP pin will pull low when the
delayed steering flag is active.

The contents of the output latch are updated on an
active delayed steering transition. This data is
presented to the four bit bidirectional data bus when
the Receive Data Register is read. The steering
circuit works in reverse to validate the interdigit
pause between signals. Thus, as well as rejecting
signals too short to be considered valid, the receiver
will tolerate signal interruptions (drop out) too short
to be considered a valid pause. This facility, together
with the capability of selecting the steering time
constants externally, allows the designer to tailor
performance to meet a wide variety of system
requirements.

Figure 5 - Basic Steering Circuit

Guard Time Adjustment

The simple steering circuit shown in Figure 5 is
adequate for most applications. Component values
are chosen according to the following inequalities
(see Figure 7):

REC

DPmax

+ t

GTPmax

- t

DAmin

REC

DPmin

+ t

GTPmin

- t

DAmax

+ t

GTAmax

- t

DPmin

DAmin

+ t

GTAmin

- t

DPmax

The value of t

is a device parameter (see AC

Electrical Characteristics) and t

REC

is the minimum

St/GT

ESt

MT88L89

GTA

= (R1C1) In (V

/ V

TSt

)

GTP

= (R1C1) In [V

/ (V

-V

TSt

)]

Advance Information

MT88L89

4-129

signal duration to be recognized by the receiver. A
value for C1 of 0.1 µF is recommended for most

Figure 6 - Guard Time Adjustment

St/GT

ESt

St/GT

ESt

GTA

= (R1C1) In (V

TSt

)

GTP

= (R

C1) In [V

/ (V

-V

TSt

)]

= (R1R2) / (R1 + R2)

GTA

= (R

C1) In (V

TSt

)

GTP

= (R1C1) In [V

/ (V

-V

TSt

)]

= (R1R2) / (R1 + R2)

a) decreasing tGTP; (tGTP < tGTA)

b) decreasing tGTA; (tGTP > tGTA)

applications, leaving R1 to be selected by the
designer. Different steering arrangements may be
used to select independent tone present (t

GTP

) and

tone absent (t

GTA

) guard times. This may be

necessary to meet system specifications which place
both accept and reject limits on tone duration and
interdigital pause. Guard time adjustment also allows
the designer to tailor system parameters such as talk
off and noise immunity.

Increasing t

REC

improves talk-off performance since

it reduces the probability that tones simulated by
speech will maintain a valid signal condition long
enough to be registered. Alternatively, a relatively
short t

REC

with a long t

would be appropriate for

extremely noisy environments where fast acquisition
time and immunity to tone drop-outs are required.
Design information for guard time adjustment is
shown in Figure 6. The receiver timing is shown in
Figure 7 with a description of the events in Figure 9.

Call Progress Filter

A call progress mode, using the MT88L89, can be
selected allowing the detection of various tones,
which identify the progress of a telephone call on the
network. The call progress tone input and DTMF
input are common, however, call progress tones can
only be detected when CP mode has been selected.

Figure 7 - Receiver Timing Diagram

ESt

St/GT

-RX

Read
Status
Register

IRQ/CP

EVENTS

REC

TONE #n

TONE
#n + 1

GTP

GTA

PStRX

PStb3

DECODED TONE # (n-1)

# n

# (n + 1)

TSt

MT88L89

Advance Information

4-130

Figure 9 - Description of Timing Events

EXPLANATION OF EVENTS
A)

TONE BURSTS DETECTED, TONE DURATION INVALID, RX DATA REGISTER NOT UPDATED.

TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER.

END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER

RETAINED UNTIL NEXT VALID TONE PAIR.

TONE #n+1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER.

ACCEPTABLE DROPOUT OF TONE #n+1, TONE ABSENT DURATION INVALID, DATA REMAINS UNCHANGED.

END OF TONE #n+1 DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER

RETAINED UNTIL NEXT VALID TONE PAIR.

EXPLANATION OF SYMBOLS
V

DTMF COMPOSITE INPUT SIGNAL.

ESt

EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES.

St/GT

STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT.

-RX

4-BIT DECODED DATA IN RECEIVE DATA REGISTER

DELAYED STEERING. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE

REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL. ACTIVE LOW FOR THE DURATION OF A
VALID DTMF SIGNAL.

INDICATES THAT VALID DATA IS IN THE RECEIVE DATA REGISTER. THE BIT IS CLEARED AFTER THE STATUS

IRQ/CP

INTERRUPT IS ACTIVE INDICATING THAT NEW DATA IS IN THE RX DATA REGISTER. THE INTERRUPT IS

CLEARED AFTER THE STATUS REGISTER IS READ.

REC

MAXIMUM DTMF SIGNAL DURATION NOT DETECTED AS VALID.

REC

MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION.

MINIMUM TIME BETWEEN VALID SEQUENTIAL DTMF SIGNALS.

MAXIMUM ALLOWABLE DROPOUT DURING VALID DTMF SIGNAL.

TIME TO DETECT VALID FREQUENCIES PRESENT.

TIME TO DETECT VALID FREQUENCIES ABSENT.

GTP

GUARD TIME, TONE PRESENT.

GTA

GUARD TIME, TONE ABSENT.

DTMF signals cannot be detected if CP mode has
been selected (see Table 7). Figure 8 indicates the
useful detect bandwidth of the call progress filter.
Frequencies presented to the input, which are within
the `accept' bandwidth limits of the filter, are hard-
limited by a high gain comparator with the IRQ/CP
pin serving as the output. The squarewave output
obtained from the schmitt trigger can be analyzed by
a microprocessor or counter arrangement to
determine the nature of the call progress tone being
detected. Frequencies which are in the `reject' area
will not be detected and consequently the IRQ/CP
pin will remain low.

DTMF Generator

The DTMF transmitter employed in the MT88L89 is
capable of generating all sixteen standard DTMF
tone pairs with low distortion and high accuracy. All
frequencies are derived from an external 3.579545
MHz crystal. The sinusoidal waveforms for the
individual tones are digitally synthesized using row
and column programmable dividers and switched
capacitor D/A converters. The row and column tones
are mixed and filtered providing a DTMF signal with
low total harmonic distortion and high accuracy. To
specify a DTMF signal, data conforming to the
encoding format shown in Table 1 must be written to

the transmit Data Register. Note that this is the
same as the receiver output code. The individual
tones which are generated (f

LOW

and f

HIGH

) are

referred to as Low Group and High Group tones. As
seen from the table, the low group frequencies are
697, 770, 852 and 941 Hz. The high group
frequencies are 1209, 1336, 1477 and 1633 Hz.
Typically, the high group to low group amplitude ratio
(twist) is 2 dB to com-pensate for high group
attenuation on long loops.

Figure 8 - Call Progress Response

AAAA

LEVEL

(dBm)

FREQUENCY (Hz)

-25

250

500

750

= Reject

= May Accept

= Accept

Advance Information

MT88L89

4-131

Figure 10 - Spectrum Plot

Scaling Information

10 dB/Div
Start Frequency = 0 Hz
Stop Frequency = 3400 Hz
Marker Frequency = 697 Hz and
1209 Hz

The period of each tone consists of 32 equal time
segments. The period of a tone is controlled by
varying the length of these time segments. During
write operations to the Transmit Data Register the 4
bit data on the bus is latched and converted to 2 of 8
coding for use by the programmable divider circuitry.
This code is used to specify a time segment length,
which will ultimately determine the frequency of the
tone. When the divider reaches the appropriate
count, as determined by the input code, a reset pulse
is issued and the counter starts again. The number
of time segments is fixed at 32, however, by varying
the segment length as described above the
frequency can also be varied. The divider output
clocks another counter, which addresses the
sinewave lookup ROM.

The lookup table contains codes which are used by
the switched capacitor D/A converter to obtain
discrete and highly accurate DC voltage levels. Two
identical circuits are employed to produce row and
column tones, which are then mixed using a low
noise summing amplifier. The oscillator described
needs no "start-up" time as in other DTMF
generators since the crystal oscillator is running
continuously thus providing a high degree of tone
burst accuracy. A bandwidth limiting filter is
incorporated and serves to attenuate distortion
products above 8 kHz. It can be seen from Figure 6
that the distortion products are very low in amplitude.

Burst Mode

In certain telephony applications it is required that
DTMF signals being generated are of a specific
duration determined either by the particular

application or by any one of the exchange transmitter
specifications currently existing. Standard DTMF
signal timing can be accomplished by making use of
the Burst Mode. The transmitter is capable of issuing
symmetric bursts/pauses of predetermined duration.
This burst/pause duration is 51 ms±1 ms which is a
standard interval for autodialer and central office
applications. After the burst/pause has been issued,
the appropriate bit is set in the Status Register
indicating that the transmitter is ready for more data.
The timing described above is available when DTMF
mode has been selected. However, when CP mode
(Call Progress mode) is selected, the burst/pause
duration is doubled to 102 ms ±2 ms. Note that when
CP mode and Burst mode have been selected,
DTMF tones may be transmitted only and

not

received. In applications where a non-standard
burst/pause time is desirable, a software timing loop
or external timer can be used to provide the timing
pulses when the burst mode is disabled by enabling
and disabling the transmitter.

Single Tone Generation

A single tone mode is available whereby individual
tones from the low group or high group can be
generated. This mode can be used for DTMF test
equipment applications, acknowledgment tone
generation and distortion measurements. Refer to
Control Register B description for details.

MT88L89

4-132

Table 2. Actual Frequencies Versus Standard

Requirements

Distortion Calculations

The MT88L89 is capable of producing precise tone
bursts with minimal error in frequency (see Table 2).
The internal summing amplifier is followed by a first-
order lowpass switched capacitor filter to minimize
harmonic components and intermodulation products.
The total harmonic distortion for a

single tone

can be

calculated using Equation 1, which is the ratio of the
total power of all the extraneous frequencies to the
power of the fundamental frequency expressed as a
percentage.

Equation 1. THD (%) For a Single Tone

The Fourier components of the tone output
correspond to V

.... V

as measured on the output

waveform. The total harmonic distortion for a

dual

tone

can be calculated using Equation 2. V

and V

correspond to the low group amplitude and high
group amplitude, respectively and V

IMD

is the sum

of all the intermodulation components. The internal
switched-capacitor filter following the D/A converter
keeps distortion products down to a very low level as
shown in Figure 10.

Equation 2. THD (%) For a Dual Tone

ACTIVE

INPUT

OUTPUT FREQUENCY (Hz)

%ERROR

SPECIFIED

ACTUAL

697

699.1

+0.30

770

766.2

-0.49

852

847.4

-0.54

941

948.0

+0.74

1209

1215.9

+0.57

1336

1331.7

-0.32

1477

1471.9

-0.35

1633

1645.0

+0.73

THD (%) = 100

fundamental

+ V

+ .... V

+ ....

+ ..

IMD

THD (%) = 100

DTMF Clock Circuit

The internal clock circuit is completed with the
addition of a standard television colour burst crystal
having a resonant frequency of 3.579545 MHz. A
number of MT88L89 devices can be connected as
shown in Figure 11 such that only one crystal is
required. Alternatively, the OSC1 inputs on all
devices can be driven from a TTL buffer with the
OSC2 outputs left unconnected.

Figure 11 - Common Crystal Connection

Microprocessor Interface

The MT88L89 design incorporates an adaptive
interface, which allows it to be connected to various
kinds of microprocessors. Key functions of this
interface include the following:

Continuous activity on DS/RD is not necessary
to update the internal status registers.

senses whether input timing is that of an Intel or
Motorola controller by monitoring the

DS (RD),

R/W (WR) and CS inputs.

generates equivalent CS signal for internal
operation for all processors.

differentiates between multiplexed and non-
multiplexed microprocessor buses. Address
and data are latched in accordingly.

compatible with Motorola and Intel processors.

Figure 16 shows the timing diagram for Motorola
microprocessors with separate address and data
buses. Members of this microprocessor family
include 2 MHz versions of the MC6800, MC6802 and
MC6809. For the MC6809, the chip select (CS) input
signal is formed by NANDing the (E+Q) clocks and
address decode output. For the MC6800 and
MC6802, CS is formed by NANDing VMA and
address decode output. On the falling edge of CS,
the internal logic senses the state of data strobe

MT88L89

OSC1

OSC2

MT88L89

OSC1

OSC2

MT88L89

OSC1

OSC2

3.579545 MHz

Advance Information

MT88L89

4-133

(DS). When DS is low,

Motorola processor operation

is selected.

Figure 17 shows the timing diagram for the Motorola
MC68HC11 (1 MHz) microcontroller. The chip select
(CS) input is formed by NANDing address strobe
(AS) and address decode output. Again, the
MT88L89 examines the state of DS on the falling
edge of CS to determine if the micro has a Motorola
bus (when DS is low). Additionally, the Texas
Instruments TMS370CX5X is qualified to have a
Motorola interface. Figure 12(a) summarizes
connection of these Motorola processors to the
MT88L89 DTMF transceiver.

Figures 18 and 19 are the timing diagrams for the
Intel 8031/8051 (12 MHz) and 8085 (5 MHz) micro-
controllers with multiplexed address and data buses.
The MT88L89 latches in the state of RD on the
falling edge of CS. When RD is high, Intel processor
operation is selected. By NANDing the address
latch enable (ALE) output with the high-byte address
(P2) decode output, CS can be generated. Figure
12(b) summarizes the connection of these Intel
processors to the MT88L89 transceiver.

NOTE: The adaptive micro interface relies on high-
to-low transition on CS

to recognize the

microcontroller interface and this pin must not be tied
permanently low.

The adaptive micro interface provides access to five
internal registers. The read-only Receive Data
Register contains the decoded output of the last
valid DTMF digit received. Data entered into the
write-only Transmit Data Register will determine
which tone pair is to be generated (see Table 1 for
coding details). Transceiver control is accomplished
with two control registers (see Tables 6 and 7), CRA
and CRB, which have the same address. A write
operation to CRB is executed by first setting the
most significant bit (b3) in CRA. The following write
operation to the same address will then be directed
to CRB, and subsequent write cycles will be directed
back to CRA. The read-only status register indicates
the current transceiver state (see Table 8).

A software reset must be included at the beginning
of all programs to initialize the control registers upon
power-up or power reset (see Figure 14). Refer to
Tables 4-7 for bit descriptions of the two control
registers.

The multiplexed IRQ/CP pin can be programmed to
generate an interrupt upon validation of DTMF
signals or when the transmitter is ready for more
data (burst mode only). Alternatively, this pin can be
configured to provide a square-wave output of the
call progress signal. The IRQ/CP pin is an open drain
output and requires an external pull-up resistor (see
Figure 13).

Figure 12 a) & b) - MT88L89 Interface Connections for Various Intel and Motorola Micros

MC6800/6802

MT88L89

A0-A15

VMA

D0-D3

MC68HC11

MC6809

MT88L89

8031/8051
8080/8085

RS0

D0-D3

R/W/WR

DS/RD

A8-A15

AD0-AD3

RS0

D0-D3

R/W/WR

DS/RD

A0-A15

D0-D3

R/W

RS0

D0-D3

R/W/WR

DS/RD

A8-A15

ALE

D0-D3

RS0

DS/RD
R/W/WR

(a)

(b)

MT88L89

MT88L89

Advance Information

4-134

Table 3. Internal Register Functions

Table 4. CRA Bit Positions

Table 5. CRB Bit Positions

Motorola

Intel

RS0

R/W

FUNCTION

Write to Transmit
Data Register

Read from Receive
Data Register

Write to Control Register

Read from Status Register

RSEL

IRQ

CP/DTMF

TOUT

C/R

S/D

TEST

BURST

ENABLE

Table 6. Control Register A Description

BIT

NAME

DESCRIPTION

TOUT

Tone Output Control. A logic high enables the tone output; a logic low turns the tone output
off. This bit controls all transmit tone functions.

CP/DTMF

Call Progress or DTMF Mode Select. A logic high enables the receive call progress mode;
a logic low enables DTMF mode. In DTMF mode the device is capable of receiving and
transmitting DTMF signals. In CP mode a retangular wave representation of the received
tone signal will be present on the IRQ/CP output pin if IRQ has been enabled (control
register A, b2=1). In order to be detected, CP signals must be within the bandwidth
specified in the AC Electrical Characteristics for Call Progress.
Note: DTMF signals cannot be detected when CP mode is selected.

IRQ

Interrupt Enable. A logic high enables the interrupt function; a logic low de-activates the
interrupt function. When IRQ is enabled and DTMF mode is selected (control register A,
b1=0), the IRQ/CP output pin will go low when either 1) a valid DTMF signal has been
received for a valid guard time duration, or 2) the transmitter is ready for more data (burst
mode only).

RSEL

Register Select. A logic high selects control register B for the next write cycle to the
control register address. After writing to control register B, the following control register
write cycle will be directed to control register A.

Advance Information

MT88L89

4-135

Table 7

Control Register B Description

Table 8

Status Register Description

BIT

NAME

DESCRIPTION

BURST

Burst Mode Select. A logic high de-activates burst mode; a logic low enables burst mode.
When activated, the digital code representing a DTMF signal (see Table 1) can be written
to the transmit register, which will result in a transmit DTMF tone burst and pause of equal
durations (typically 51 msec). Following the pause, the status register will be updated (b1 -
Transmit Data Register Empty), and an interrupt will occur if the interrupt mode has been
enabled.

When CP mode (control register A, b1) is enabled the normal tone burst and pause
durations are extended from a typical duration of 51 msec to 102 msec.

When BURST is high (de-activated) the transmit tone burst duration is determined by the
TOUT bit (control register A, b0).

RxEN

This bit enables the DTMF and Call Progress Tone receivers. A logic low enables both
circuits. A logic high deactivates and puts both receiver circuits into power down mode.

S/D

Single or Dual Tone Generation. A logic high selects the single tone output; a logic low
selects the dual tone (DTMF) output. The single tone generation function requires further
selection of either the row or column tones (low or high group) through the C/R bit (control
register B, b3).

C/R

Column or Row Tone Select. A logic high selects a column tone output; a logic low selects
a row tone output. This function is used in conjunction with the S/D bit (control register B,
b2).

BIT

NAME

STATUS FLAG SET

STATUS FLAG CLEARED

IRQ

Interrupt has occurred. Bit one
(b1) or bit two (b2) is set.

Interrupt is inactive. Cleared after
Status Register is read.

TRANSMIT DATA
REGISTER EMPTY
(BURST MODE ONLY)

Pause duration has terminated
and transmitter is ready for new
data.

Cleared after Status Register is
read or when in non-burst mode.

RECEIVE DATA REGISTER
FULL

Valid data is in the Receive Data
Register.

Cleared after Status Register is
read.

DELAYED STEERING

Set upon the valid detection of
the absence of a DTMF signal.

Cleared upon the detection of a
valid DTMF signal.

Advance Information

MT88L89

4-137

Figure 14 - Application Notes

INITIALIZATION PROCEDURE

A software reset must be included at the beginning of all programs to initialize the control registers after
power up.

Description:

Motorola Intel

Data

RS0

R/W

WR RD

1) Read Status Register

2) Write to Control Register

3) Write to Control Register

4) Write to Control Register

5) Write to Control Register

6) Read Status Register

TYPICAL CONTROL SEQUENCE FOR BURST MODE APPLICATIONS

Transmit DTMF tones of 50 ms burst/50 ms pause and Receive DTMF Tones.

Sequence:

RS0

R/W

WR RD

1) Write to Control Register A

(tone out, DTMF, IRQ, Select Control Register B)

2) Write to Control Register B

(burst mode)

3) Write to Transmit Data Register

(send a digit 7)

4) Wait for an Interrupt or Poll Status Register
5) Read the Status Register

-if bit 1 is set, the Tx is ready for the next tone, in which case ...
Write to Transmit Register

(send a digit 5)

-if bit 2 is set, a DTMF tone has been received, in which case ....
Read the Receive Data Register

-if both bits are set ...
Read the Receive Data Register

Write to Transmit Data Register

NOTE: IN THE TX BURST MODE, STATUS REGISTER BIT 1 WILL NOT BE SET UNTIL 100 ms ( ±2 ms) AFTER THE DATA IS
WRITTEN TO THE TX DATA REGISTER. IN EXTENDED BURST MODE THIS TIME WILL BE DOUBLED TO 200 ms (± 4 ms)

MT88L89

Advance Information

4-138

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

Typical figures are at 25 °C and for design aid only: not guaranteed and not subject to production testing.

Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25 °C, V

=3V and for design aid only: not guaranteed and not subject to production testing.

* See "Notes" following AC Electrical Characteristics Tables.

Absolute Maximum Ratings

Parameter

Symbol

Min

Max

Units

Power supply voltage V

-V

Voltage on any pin

-0.3

+0.3

Current at any pin (Except V

and

)

Storage temperature

-65

+150

°C

Package power dissipation

1000

Recommended Operating Conditions -

Voltages are with respect to ground (VSS) unless otherwise stated.

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

Positive power supply

2.7

3.6

Operating temperature

-40

+85

°C

Crystal clock frequency

CLK

3.575965

3.579545

3.583124

MHz

DC Electrical Characteristics

- VSS=0 V.

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

S
U
P

Operating supply voltage

2.7

3.6

Operating supply current

Device fully enabled

Power consumption

N
P
U
T
S

High level input voltage
(OSC1)

IHO

2.1

=3.0V

Low level input voltage
(OSC1)

ILO

=3.0V

Steering threshold voltage

TSt

1.4

=3.0V

O
U

T
P
U
T
S

Low level output voltage
(OSC2)

OLO

0.3

No load
V

=0V

High level output voltage
(OSC2)

OHO

2.97

No load
V

=3.0V

Output leakage current
(IRQ)

=2.4 V

Ref

output voltage

Ref

1.5

No load, V

=3V

Ref

output resistance

1.3

i
t

Low level input voltage

High level input voltage

2.1

Input leakage current

to V

Data

Bus

Source current

-6.6

=2.4V

Sink current

4.0

=0.4V

ESt
and

St/GT

Source current

-3.0

=2.4V

Sink current

=0.4V

IRQ/

Sink current

=0.4V

Advance Information

MT88L89

4-139

Typical figures are at 25°C and for design aid only: not guaranteed and not subject to production testing.

Characteristics are over recommended operating conditions (unless otherwise stated)

using the test circuit shown in Figure 13.

Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25°C, V

= 3V, and for design aid only: not guaranteed and not subject to production testing.

* *See "Notes" following AC Electrical Characteristics Tables.

Electrical Characteristics
Gain Setting Amplifier

- Voltages are with respect to ground (V

) unless otherwise stated, V

= 0V, V

=3V, T

=25°C.

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Input leakage current

±100

Input resistance

Input offset voltage

Power supply rejection

PSRR

1 kHz

Common mode rejection

CMRR

0.75

4.25V

DC open loop voltage gain

VOL

Unity gain bandwidth

1.5

MHz

Output voltage swing

4.5

100 k

to V

Allowable capacitive load (GS)

100

Allowable resistive load (GS)

Common mode range

3.0

No Load

MT88L89 AC Electrical Characteristics

- Voltages are with respect to ground (V

) unless otherwise stated.

Characteristics

Sym

Min

Typ

Max

Units

Notes*

R
X

Valid input signal levels
(each tone of composite
signal)

-34

-4

dBm

1,2,3,5,6
min @ V

=3.6V

max @ V

=2.7V

15.4

489

RMS

1,2,3,5,6

AC Electrical Characteristics

Voltages are with respect to ground (V

) unless otherwise stated. f

=3.579545 MHz.

Characteristics

Sym

Min

Typ

Max

Units

Notes*

R
X

Positive twist accept

2,3,6,9

Negative twist accept

2,3,6,9

Freq. deviation accept

±1.5%± 2Hz

2,3,5

Freq. deviation reject

±3.5%

2,3,5

Third tone tolerance

-16

2,3,4,5,9,10

Noise tolerance

-12

2,3,4,5,7,9,10

Dial tone tolerance

2,3,4,5,8,9

MT88L89

Advance Information

4-140

Characteristics are over recommended operating conditions unless otherwise stated
Typical figures are at 25°C, V

=3V, and for design aid only: not guaranteed and not subject to production testing

Characteristics are over recommended operating conditions unless otherwise stated
Typical figures are at 25°C, V

=3V, and for design aid only: not guaranteed and not subject to production testing

Timing is over recommended temperature & power supply voltages.
Typical figures are at 25°C and for design aid only: not guaranteed and not subject to production testing.

AC Electrical Characteristics

- Call Progress -

Voltages are with respect to ground (V

), unless otherwise stated.

Characteristics

Sym

Min

Typ

Max

Units

Conditions

Accept Bandwidth

310

500

@ -25 dBm,
Note 9

Lower freq. (REJECT)

290

@ -25 dBm

Upper freq. (REJECT)

540

@ -25 dBm

Call progress tone detect level (total
power)

-30

dBm

AC Electrical Characteristics

- DTMF Reception -

Typical DTMF tone accept and reject requirements. Actual

values are user selectable as per Figures 5, 6 and 7.

Characteristics

Sym

Min

Typ

Max

Units

Conditions

Minimum tone accept duration

REC

Maximum tone reject duration

REC

Minimum interdigit pause duration

Maximum tone drop-out duration

AC Electrical Characteristics

- Voltages are with respect to ground (V

), unless otherwise stated.

Characteristics

Sym

Min

Typ

Max

Units

Conditions

O
N

Tone present detect time

Note 11

Tone absent detect time

0.5

8.5

Note 11

Delay St to b3

PStb3

See Figure 7

Delay St to RX

-RX

PStRX

See Figure 7

O
N

O
U

Tone burst duration

BST

DTMF mode

Tone pause duration

DTMF mode

Tone burst duration (extended)

BSTE

100

104

Call Progress mode

Tone pause duration (extended)

PSE

100

104

Call Progress mode

High group output level

HOUT

-15.1

-11.1

dBm

=10k

Low group output level

LOUT

-17.1

-13.1

dBm

=10k

Pre-emphasis

=10k

Output distortion (Single Tone)

THD

-35

25 kHz Bandwidth

=10k

Frequency deviation

±0.7

±1.5

=3.579545 MHz

Output load resistance

X
T
A

Crystal/clock frequency

3.5759

3.5795

3.5831

MHz

Clock input rise and fall time

CLRF

110

Ext. clock

Clock input duty cycle

Ext. clock

Capacitive load (OSC2)

Advance Information

MT88L89

4-141

Characteristics are over recommended operating conditions unless otherwise stated
Typical figures are at 25°C, V

=3V, and for design aid only: not guaranteed and not subject to production testing

NOTES: 1) dBm=decibels above or below a reference power of 1 mW into a 600 ohm load.

2) Digit sequence consists of all 16 DTMF tones.
3) Tone duration=40 ms. Tone pause=40 ms.
4) Nominal DTMF frequencies are used.
5) Both tones in the composite signal have an equal amplitude.
6) The tone pair is deviated by ± 1.5 %±2 Hz.
7) Bandwidth limited (3 kHz) Gaussian noise.
8) The precise dial tone frequencies are 350 and 440 Hz (±2 %).
9) Guaranteed by design and characterization. Not subject to production testing.
10) Referenced to the lowest amplitude tone in the DTMF signal.
11) For guard time calculation purposes.

Figure 15 - DS/RD/WR Clock Pulse

AC Electrical Characteristics

- MPU Interface

- Voltages are with respect to ground (V

), unless otherwise stated.

Characteristics

Sym

Min

Typ

Max

Units

Conditions

DS/RD/WR clock frequency

CYC

4.0

MHz

Figure 15

DS/RD/WR cycle period

CYC

250

Figure 15

DS/RD/WR low pulse width

150

Figure 15

DS/RD/WR high pulse width

100

Figure 15

DS/RD/WR rise and fall time

Figure 15

R/W setup time

RWS

Figures 16 & 17

R/W hold time

RWH

Figures 16 & 17

Address setup time (RS0)

Figures 16 - 19

Address hold time (RS0)

Figures 16 - 19

Data hold time (read)

DHR

Figures 16 - 19

DS/RD to valid data delay (read)

DDR

Figures 16 - 19

Data setup time (write)

DSW

Figures 16 - 19

Data hold time (write)

DHW

Figures 16 - 19

Chip select setup time

CSS

Figures 16 - 19

Chip select hold time

CSH

Figures 16 - 19

CYC

DS/RD/WR

MT88L89

Advance Information

4-142

Figure 16 - MC6800/MC6802/MC6809 Timing Diagram

DSW

is from data to DS falling edge; t

CSH

is from DS rising edge to CS rising edge

Figure 17 - MC68HC11 Bus Timing (with multiplexed address and data buses)

Q clk*

A0-A15
(RS0)

R/W(read)

Read Data
(D3-D0)

R/W (write)

Write data
(D3-D0)

CS = (E + Q).Addr [MC6809]

CS = VMA.Addr [MC6800, MC6802]

*microprocessor pin

RWS

RWH

16 bytes of Addr

DDR

DSW

DHW

CSH

CSS

CSH

DHR

R/W

Read
AD3-AD0
(RS0, D0-D3)

Write
AD3-AD0
(RS0-D0-D3)

Addr *
non-mux

AS *

CS = AS.Addr

* microprocessor pins

RWS

RWH

DDR

DHR

Data

DSW

DHW

CSH

CSS

High Byte of Addr

Addr

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