3-3

�

Features

�

High speed parallel access to the serial ST-BUS

�

Parallel bus optimized for 68000

�

P (mode 1)

�

Fast dual-port RAM access (mode 2)

Access time: 120 nsec

�

Parallel bus controller (mode 3) - no external
controller required

�

Flexible interrupt capabilities - two
independent/programmable interrupt sources
with auto-vectoring

�

Selectable 24 and 32 channel operation

�

Programmable loop-around modes

�

Low power CMOS technology

Applications

�

Parallel control/data access to T1/CEPT digital
trunk interfaces

�

Digital signal processor interface to ST-BUS

�

Computer to Digital PABX link

�

Voice store and forward systems

�

Interprocessor communications

Description

The ST-BUS Parallel Access Circuit (STPA) provides
a simple interface between Mitel's ST-BUS and
parallel system environments.

Ordering Information

MT8920BE

28 Pin Plastic DIP

MT8920BC

28 Pin Ceramic DIP

MT8920BP

28 Pin Plastic J-Lead

MT8920BS

28 Pin SOIC

-40

�

C to 85

�

Figure 1 - Functional Block Diagram

D7-D0

A4-A0

DS, OE

R/W, WE

DTACK,

BUSY, DCS

IRQ, 24/32

IACK, MS1

A5, STCH

MMS

C4i

F0i

STo1

STi0

STo0

Tx0

Dual Port Ram

32 X 8

Rx0

Dual Port Ram

32 X 8

Tx1

Dual Port Ram

32 X 8

Parallel-

to-serial

Converter

Serial-to-

Parallel

Converter

Parallel-
to-Serial

Converter

Comp/

MUX

Address

Generator

Parallel

Port

Interface

Interrupt

Registers

Control

Registers

ISSUE 6

June 1996

MT8920B

ST-BUS Parallel Access Circuit

ISO-CMOS ST-BUS

FAMILY

MT8920B

CMOS

3-4

Figure 2 - Pin Connections

Pin Description

Pin #

Name

Description

C4i

4.096 MHz Clock. The ST-BUS timing clock used to establish bit cell boundaries for the serial
bus.

F0i

Framing Pulse. A low going pulse used to synchronize the STPA to the 2048 kbit/s ST-BUS
stream. The first falling edge of C4i subsequent to the falling edge of F0i identifies the start of
a frame.

IACK

Interrupt Acknowledge (Mode 1). This active low input signals that the current bus cycle is
an interrupt vector fetch cycle. Upon receiving this acknowledgement, the STPA will
output a user-programmed vector number on D

- D

indicating the source of the interrupt.

MS1

Mode Select 1 (Mode 2,3). This input is used to select the device operating modes. A low
applied to this pin will select mode 3 while a high will select mode 2. (Refer to Table 1.)

STi0

ST-BUS Input 0. This is the input for the 2048 kbit/s ST-BUS serial data stream.

Chip Select. This active low input is used to select the STPA for a parallel access .

Data Strobe (Mode 1). This active low input indicates to the STPA that valid data is on the data
bus during a write operation or that the STPA must output valid data on the data bus during a
read operation.

Output Enable (Mode 2). This active low input enables the data bus driver outputs.

Output Enable (Mode 3). This active low output indicates that the selected device is to be
read and that the data bus is available for data transfer.

R/W

Read/Write (Mode 1,2). This input defines the data bus transfer as a read (R/W = 1) or a write
(R/W= 0) cycle.

Write Enable (Mode 3). This active low output indicates the data on the data bus is to be
written into the selected location of an external device.

8-12

A0-A4 Address Bus (Mode 1,2). These inputs are used to select the internal registers and two-port

memories of the STPA.

A0-A4 Address Bus (Mode 3). These address outputs are generated by the STPA and reflect the

position in internal RAM where the information will be fetched from or stored in. Addresses
generated in this mode are used to access external devices for direct memory transfer.

28 PIN J-LEAD

1
2
3
4
5
6
7
8
9

10
11
12
13
14

28
27
26
25
24
23
22
21

C4i

F0i

IACK, MS1

STi0

DS, OE

R/W, WE

A0
A1
A2
A3
A4

A5, STCH

VSS

VDD
MMS
DTACK, BUSY, DCS
IRQ, 24/32
STo1
STo0
D7
D6
D5
D4
D3
D2
D1
D0

28 PIN PDIP/CERDIP/SOIC

5
6
7
8
9
10
11

25
24
23
22
21
20
19

�

F0i

CK, MS1

STi0

C4i

VDD

MMS

CK,

IRQ, 24/32
STo1
STo0
D7
D6
D5
D4

DS, OE

R/W, WE

A0
A1
A2
A3

VSS

USY,

DCS

A5,

STCH

CMOS

MT8920B

3-5

Pin Descriptions pertain to all modes unless otherwise stated.

Table 1. STPA Modes of Operation

Address Bit A5 (Mode 1). This input is used to extend the address range of the STPA. A5
selects internal registers when high and Tx/Rx RAM's when low.

Address Bit A5 (Mode 2). This input is used to extend the address range of the STPA. A5
selects Tx0/Rx0 RAM's when low and Tx1/Rx0 RAM's when high.

STCH Start of Channel (Mode 3). This signal is a low going pulse which indicates the start of an

ST-BUS channel. The pulse is four bits wide and begins at the start of each valid channel.

Ground.

15-22

D0-D7 Bidirectional Data Bus. This bus is used to transfer data to or from the STPA during a write

or read operation.

STo0

ST-BUS Output 0. This output supplies the output ST-BUS 2048 kbit/s serial data stream from
Tx0 two-port RAM.

STo1

ST-BUS Output 1. In modes 1 and 2 this output supplies the output ST-BUS 2048 kbit/s serial
data stream from Tx1 two-port RAM. In mode 3, information arriving at STi0 is output here with
one frame delay.

IRQ

Interrupt Request (Mode 1). This open drain output, when low, indicates when an interrupt
condition has been raised within the STPA.

24/32

24 Channel/32 Channel Select (Mode 2,3). This input is used to select the channel
configuration in modes 2 and 3. A low applied to this pin will select a 24 (T1) channel mode
while a high will select a 32 (CEPT) channel mode.

DTACK Data Transfer Acknowledge (Mode 1). This open drain output is supplied by the STPA to

acknowledge the completion of data transfers back to the

�

P. On a read of the STPA, DTACK

low indicates that the STPA has put valid data on the data bus. On a write, DTACK low
indicates that the STPA has completed latching the

�

P's data from the data bus.

BUSY

BUSY (Mode 2). This open drain output signals that the controller and the ST-BUS are
accessing the same location in the dual-port RAM's. It is intended to delay the controller
access until after the ST-BUS completes its access.

DCS

Delayed Chip Select (Mode 3). This low going pulse, which is four bit cells long, is active
during the last half of a valid channel. This signal is used to daisy-chain together two STPA's in
mode 3 that are accessing devices on the same parallel data bus.

MMS

Master Mode Select (Reset). This Schmitt trigger input selects between either mode 1 (MMS
= 1), or modes 2and 3 (MMS = 0). If MMS is pulsed low in Mode 1 operation the control and
interrupt registers will be reset. (Refer to Table 1.) During power-up, the time constant of the
reset circuit (see Fig. 8) must be a minimum of five times the rise time of the power supply.

Power Supply Input. (+5V).

Mode

MMS

MS1

Mode of

Operation

Function

N/A

�

Peripheral

Mode

The STPA provides parallel-to-serial and serial-to-parallel conversions through a
68000-type interface. Two Tx RAMs and one Rx RAM are available along with full
interrupt capability. 32 channel or 24 channel support is available. Control Register 1, bit
D

(RAMCON) = 0 for 32 channel operation and D

(RAMCON)= 1 for 24 channel

operation.

Fast RAM

Mode

The STPA provides a fast access interface to Tx0, Tx1 and Rx0 RAMs. This mode is
intended for full parallel support of 24 channel T1/ESF trunks and 32 channel CEPT
trunks. Input 24/32 (pin 25) = 0 for 24 channel operation, input 24/32 (pin 25) = 1 for 32
channel operation.

Bus

Controller

Mode

The STPA will synchronously drive the parallel bus using the address generator and
provide all data transfer signals. This mode is intended to support 24 or 32 channel
devices in the absence of a parallel bus controller. Input 24/32 (pin 25) = 0 for 24 channel
operation, input 24/32 (pin 25) = 1 for 32 channel operation.

Pin Description (continued)

Pin #

Name

Description

MT8920B

CMOS

3-6

Functional Description

The STPA (ST-BUS Parallel Access) device provides
a simple interface between Mitel's ST-BUS and
parallel system environments. The ST-BUS is a
synchronous, time division, multiplexed serial
bussing scheme with data streams operating at 2048
kbit/s. The ST-BUS is the primary means of access
for voice, data and control information to Mitel's
family of digital telecommunications components,
including North American and European digital trunk
interfaces, ISDN U and S digital line interfaces, filter
codecs, rate adapters, etc. The STPA provides
several modes of operation optimized according to
the type of information being handled.

For interfacing parallel data and control information
to the ST-BUS, such as signalling and link control for
digital trunks, the STPA provides a

�

P access mode

(Mode 1), and looks like a 68000 type peripheral. In
this mode, the device provides powerful interrupt
features, useful in monitoring digital trunk or line
status (i.e., synchronization, alarms, etc.) or for
setting up message communication links between
microprocessors.

To interface high speed data or multi-channel voice/
data to the ST-BUS for switching or transmission, the
STPA has a high speed synchronous access mode
(Mode 2) and acts like a fast RAM. For voice storage
and forward, bulk data transfer, data buffering and
other similar applications, the STPA has a
controllerless mode (Mode 3) in which it provides
address and control signals to the parallel bus This
is useful for performing direct transfers to the
ST-BUS from external devices such as a RAM buffer.

The STPA is a two port device as shown in the
functional block diagram in Figure 1. The parallel
port provides direct access to three dual port RAM's,
two transmit and one receive. The address, data and

control busses are used to communicate between
the RAM`s and a parallel environment.

Two parallel-to-serial converters, and one
serial-to-parallel converter interface the dual port
RAM's to the ST-BUS port of the STPA. This port
consists of two serial output streams and one serial
input stream operating at 2048 kbit/s. This
configuration of two outputs and one input was
designed to allow a single STPA to form a complete
control interface to Mitel's digital trunk interfaces
(MT8976, MT8978 and MT8979) which have two
serial input and one serial output control streams.

ST-BUS clocking circuitry, address generator and
various control and interrupt registers complete the
STPA's functionality.

Modes of Operation

The three basic modes of operation,

�

P Peripheral

Mode (Mode 1), Fast RAM Mode (Mode 2) and Bus
Controller Mode (Mode 3) are selected using two
external input pins. These inputs are MMS and MS1
and are decoded as shown in Table 1. Whenever
MMS=1 the device resides in Mode 1. In this mode,
MS1 pin is unavailable and is used for a different
function.

When MMS=0, Modes 2 or 3 are selected as
determined by input MS1. If MS1=1, Mode 2 is
selected and if MS1 =0, Mode 3 is selected.

Each of the modes of the STPA provides a different
pinout to ease interfacing requirements of different
parallel environments. These are shown in Figure 3
below. In

�

P Peripheral Mode the device uses

interface signals consistent with a 68000-type

�

bus. Mode 2, Fast RAM Mode, uses signals typical
of standard RAM type interfaces. Mode 3 interface
signals are very similiar to Mode 2 signals except
that the address and control signals are supplied as
outputs by the STPA.

Figure 3 - Modes 1, 2, 3 Pin Connections

�

P Peripheral Mode #1

Fast RAM

1
2
3
4
5
6
7
8
9

10
11
12
13
14

28
27
26
25
24
23
22
21

C4i

F0i

IACK

STi0

CS
DS

R/W

A0
A1
A2
A3
A4
A5

VSS

VDD
MMS
DTACK
IRQ
STo1
STo0
D7
D6
D5
D4
D3
D2
D1
D0

1
2
3
4
5
6
7
8
9

10
11
12
13
14

28
27
26
25
24
23
22
21

C4i

F0i

MS1
STi0

R/W

A0
A1
A2
A3
A4
A5

VSS

VDD
MMS
BUSY
24/32
STo1
STo0
D7
D6
D5
D4
D3
D2
D1
D0

1
2
3
4
5
6
7
8
9

10
11
12
13
14

28
27
26
25
24
23
22
21

C4i

F0i

MS1
STi0

A0
A1
A2
A3
A4

STCH

VSS

VDD
MMS
DCS
24/32
STo1
STo0
D7
D6
D5
D4
D3
D2
D1
D0

Mode #2

Bus Controller Mode #3

CMOS

MT8920B

3-7

24/32 Channel Operation

The STPA may be configured to operate as a 32
channel or 24 channel device. This feature, which is
available in all three modes of operation, is
particularly useful in applications involving data
access to CEPT and T1 digital trunk interfaces.

When used as a data interface to Mitel`s CEPT
digital trunks, the STPA maps the 32 consecutive
bytes of each dual port memory directly to ST-BUS
channels 0-31. This is performed by the address
generator shown in the functional block diagram (see
Figure 1). Figures 4 c & d show the relationship
between relative dual port RAM locations and
corresponding ST-BUS channels, for both input and
output serial streams, when the STPA is configured
as a 32 channel device.

When used as a data interface to Mitel's T1 trunk
devices, however, only the first 24 consecutive RAM
locations are mapped to 24 of the 32 ST-BUS
channels. This mapping follows a specific pattern
which corresponds with the data streams used by
Mitel`s T1 products. Instead of a direct correlation
(as in 32 channel operation), the 24 consecutive
RAM locations are mapped to the ST-BUS with every
fourth channel, beginning at channel 0, set to FF

(ie. channel 0, 4, 8, 12, 16, 20, 24 and 28). Figures
4 a & b show the relationship between RAM
locations and ST-BUS channel configuration. This
feature allows the STPA to be interfaced directly to
Mitel's T1 trunk family.

When the STPA is operated in Mode 1, 24 and 32
channel configurations are selected using bit D

(RAMCON) in Control Register 1. D

= 0 selects 32

channel operation and D

= 1 selects 24 channel

operation. When the STPA is operated in Modes 2 or
3, however, the channel configuration is done
using input

24/32 (pin 25). When 24/32 = 1 the

device uses all 32 channels and when 24/32 = 0 it
uses 24.

Dual Port RAMS

Each of the three serial ST-BUS streams is
interfaced to the parallel bus through a 32 byte dual
port RAM. This allows parallel bus accesses to be
performed asynchronously while accesses at the
ST-BUS port are synchronous with ST-BUS clock.
As with any dual port RAM interface between two
asynchronous systems, the possibility of access
contention exists. The STPA minimizes this
occurrence by recognizing contention only when
accesses are performed at the same time for the
same 8-bit cell within the dual port RAM's.
Furthermore, the probability of contention is

lessened since ST-BUS accesses require only the
last half cycle of C4i of every channel. When
contention does occur, priority is always given to the
ST-BUS access.

The STPA indicates this contention situation in a
different manner for Modes 1 and 2. In Mode 1, the
contention is masked by virtue of the
"handshaking" method used to transfer data on
this 68000-type interface. Data Strobe (DS)
and Data Transfer Acknowledge (DTACK) control
the exchange. If contention should occur the
device will delay returning DTACK and thus stretch
the bus cycle until the

�

P access can be completed.

In Mode 2, if access is attempted during a
"contention window" the STPA will supply the
BUSY signal to delay the start of the bus cycle. This
"contention window" is defined as shown in Figure
16. The window exists during the last cycle of C4i
clock in each channel timeslot. Although ST-BUS
access is only required during the last half of this
clock period, the "contention window" exists for the
entire clock period since a parallel access occurring
just prior to an ST-BUS access will not complete
before the ST-BUS access begins. Figure 16 further
shows four possible situations that may occur when
parallel accesses are attempted in and around the
"contention window". Condition 1 indicates that an
access occurring prior to the contention window but
lasting into the first half of it will complete normally
with no contention arbitration. If the access should
extend past the first half of the contention window
and into the ST-BUS access period, the BUSY signal
will be generated. Conditions 3 and 4 show accesses
occurring inside the contention window. These
accesses will result in BUSY becoming active
immediately after the access is initiated and
remaining active as shown in Figure 16.

Access contention is non-existent in Mode 3 since
the parallel bus signals, driven by the STPA, are
synchronized to the ST-BUS clocks.

Mode 1 -

�

P Peripheral Mode

In Mode 1, the STPA operates as an asynchronous
68000-type microprocessor peripheral. All three
dual-port RAMS (Tx0, Tx1, Rx0) are made available
and may be configured as 32 or 24 byte RAM's. Also
available are the full complement of control and
interrupt registers. The address map for Mode 1 is
shown in Table 2.

The STPA, in Mode 1, uses signals CS, R/W,

(Data Strobe), DTACK (Data Acknowledge) IRQ, and
IACK (Interrupt Acknowledge) at the parallel interface.
The pinout of the device is shown in Figure 3.

MT8920B

CMOS

3-8

Figure 4 a) RELA

TIVE Rx RAM ADDRESS vs. ST

-B

US CHANNEL - 24 CHANNEL MODE

Figure 4 b) RELA

TIVE Tx RAM ADDRESS vs. ST

-B

US CHANNEL - 24 CHANNEL MODE

Figure 4 c) RELA

TIVE Rx RAM ADDRESS vs. ST

-B

US CHANNEL - 32 CHANNEL MODE

Figure 4 d) RELA

TIVE Tx RAM ADDRESS vs. ST

-B

US CHANNEL - 32 CHANNEL MODE

X- un

used channels mar

ed X tr

ansmit FF

STi0

1234

5678

RELA

TIVE

RAM

LOCA

TION

1234

5678

RELA

TIVE

RAM

LOCA

TION

STi0

0123456789

RELA

TIVE

RAM

LOCA

TION

0123456789

RELA

TIVE

RAM

LOCA

TION

0123456789

CMOS

MT8920B

3-9

Table 2. Mode 1 Address Map

NOTES:

X is don't care
A

is bit D

of Control Register 1

Table 3. Control Register 1 Bit Definitions

ADDRESS BITS

REGISTERS

READ

WRITE

�
�
�

Rx0 - Channel 0

�
�
�

Rx0 - Channel 31

Tx0 - Channel 0

�
�
�

Tx0 - Channel 31

Control Register 1

Control Register 2

Interrupt Vector Register

Interrupt Flag Register 1

Interrupt Flag Register 2

Image Register 1

Image Register 2

Interrupt Mask Register 1

Interrupt Mask Register 2

Match Byte Register 1

Match Byte Register 2

Interrupt Channel Address 1

Interrupt Channel Address 2

�
�
�

Rx0 - Channel 0

�
�
�

Rx0 - Channel 31

Tx1 - Channel 0

�
�
�

Tx1 - Channel 31

Bit

Name

Description

(Unused)

IRQRST

Interrupt Reset. This bit, when set high, automatically clears the Interrupt Flag Register
and the Interrupt Image Register without these registers being serviced. This bit
automatically resets to zero after the register clear is completed.

RAMCON

RAM Configuration. This bit configures Tx0, Tx1 and Rx0 RAMS for 32 or 24 byte
operation. D

= 0 for 32 channel; D

= 1 for 24 channel.

Address Bit A6. This bit extends the addressing range for access to Tx1 memory.

IRQ2MODE

Interrupt Source 2 Mode Select. This bit configures the source 2 interrupt generator.
D

= 0 selects "static" interrupt mode; D

= 1 selects "dynamic" interrupt mode.

IRQ1MODE

Interrupt Source 1 Mode Select. This bit configures the source 1 interrupt generator.
D

= 0 selects "static" interrupt mode; D

= 1 selects "dynamic" interrupt mode.

IRQ2EN

Interrupt Source 2 Enable. IRQ2EN = 1 enables interrupts to occur from source 2.

IRQ1EN

Interrupt Source 1 Enable. IRQ1EN = 1 enables interrupts to occur from source 1.

MT8920B

CMOS

3-10

Timing information for data transfers on this interface
is shown in Figure 14. The Mode 1 interface is
designed to operate directly with a 68000-type
asynchronous bus but can easily accommodate most
other popular microprocessors as well.

Control Registers

Two control registers allow control of Mode 1
features. Control Register 1 provides bits to select
the type of interrupt, to enable interrupts from two
different and independent sources and to reset the
interrupt registers. Also contained in Control
Register 1 are bits to configure the device for 24 or
32 channel operation and to expand the address
range for convenient access to the second transmit
RAM Tx1. A description of the bit functions in
Control Register 1 is shown in Table 3.

Mode 1 provides various loopback paths and output
configuration options which are controlled by bits in
Control Register 2. Bits D

, D

of Control Register 2

configure loopbacks using input and output streams
STi0, STo0 as described in Table 4. The input
stream STi0 can be looped back to source the output
stream STo0 as well as receive RAM Rx0. The
transmit RAM Tx0 can be looped to source the
receive RAM Rx0, as well as STo0 and, the transmit
RAM Tx0 can be looped to the receive RAM Rx0
while STi0 sources STo0. The function of these
loopback configurations is shown in Figure 5.

In a similar way, the output STo1 can be reconfigured
for different functionality. Bits D

and D

of Control

Register 2 allow STo1 to be sourced, with a one
frame delay via Tx1 from receive stream STi0. STo1
can also output the result of a comparison of the
contents of Tx1 ram with input stream STi0. These
output configurations of STo1 are shown in Figure 6

a and b. Figure 6 c shows the effect of combining
these two features.

Interrupt Registers

Interrupts can be generated in Mode 1 only. Two
channels of the ST-BUS input stream, STi0, can be
selected to provide an interrupt to the system.
Interrupts can be of two types: Static or Dynamic.
Static interrupts are caused when data within a
selected channel matches a given pattern. Dynamic
interrupts occur when bits in a selected channel
change state (1 to 0, 0 to 1 or toggle). Interrupts are
controlled through two identical paths (1 and 2)
consisting of the following registers:

Interrupt Channel Address (1/2): The address
(0-31) of the channel which will generate the
interrupt is stored in this register.

Image Register (1/2): The contents of the
channel causing the interrupt is stored in this
register. Reading this register will clear its contents.

Match Byte Register (1/2): In static mode this
register is used to store the byte which will be
compared with the contents of the selected channel
causing the interrupt.

In dynamic mode, the bits in this register and the
corresponding bit in the Interrupt Mask Register
define the type of dynamic interrupt (i.e., 0 to 1, 1 to
0, toggle). (Refer to Table 5.)

Table 4. Control Register 2 Bit Definitions

Bit

Name

Description

7-4

(Unused)

3-2

CONFIG

STo1 Output Configuration Bits:
D

= 00-

Normal operation. ST-BUS stream from Tx1 is output on STo1 pin.

01-

STi0 stream is output on STo1 pin delayed one frame (Figure 6 a).

10-

STi0 is compared through XOR (exclusive OR) with ST-BUS stream

from Tx1 and output at STo1 (Figure 6 b).

11-

STi0 stream, delayed one frame (via Tx1), is compared (XOR) with the

next frame arriving at STi0 and the result output at STo1 (Figure 6 c).

1-0

LOOPBACK

Internal Loopback Configuration Bits:
D

= 00-

Normal operation. No internal loops.

01-

Loop STi0 to STo0 while still receiving STi0 in Rx0 (Figure 5 a).

10-

Loop Tx0 output ST-BUS stream to Rx0 input ST-BUS stream while

outputting Tx0 output to STo0. STi0 is not received (Figure 5 b).

11-

Loop Tx0 output ST-BUS stream to Rx0 input ST-BUS stream. Loop

STi0 to STo0 (Figure 5 c).

CMOS

MT8920B

3-11

Figure 5 - Loopback Configurations

Interrupt Mask Register (1/2): In static mode the
contents of this register masks bits in the Match Byte
Register that are 'don't care' bits

1 - bit masked
0 - bit not masked

In dynamic mode, each bit in this register and the
corresponding bit in the Match Byte Register define
what type of dynamic interrupt is selected. (Refer to
Table 5.)

Interrupt Flag Register (1/2): In static mode
the least significant bit in this register is set to 1 to
flag the corresponding path in which the interrupt
occurs.

In dynamic mode this register sets the bits which
reflect the position of the bits in the corresponding
Interrupt Register which caused the interrupt.

Figure 6 - STo1 Configurations

Interrupt Vector Register

This register shown in Figure 7 is common to both
interrupt paths and stores an 8 bit vector number
which will be output on the data bus when
Interrupt Acknowledge (IACK) is asserted. Bits
labelled V

- V

are stored by the controlling

�

Bits IRQ1 and IRQ2 are set by the STPA to indicate
which path caused the interrupt. This creates unique
vectors which are used by the

�

P to vector to

interrupt service routines. This feature may be
bypassed by simply not asserting IACK during
interrupt acknowledged.

Figure 7 - Interrupt Vector Registers

STo0

STi0

Rx0

�

Control Register 2
Bits D

= 0, D

= 1

STo0

STi0

Tx0

Rx0

�

Control Register 2
Bits D

= 1, D

= 0

STo0

STi0

Control Register 2
Bits D

= 1, D

= 1

�

Tx0

Rx0

IRQ2

IRQ1

STo0

STi0

STo1

STo0

STi0

STo1

STo0

STi0

STo1

�

Tx0

Rx0

Tx1

1 Frame Delay

Tx0

Rx0

Tx1

Tx0

Rx0

Tx1

1 Frame Delay

Control Register 2
Bits D

= 0, D

= 1

Control Register 2
Bits D

= 1, D

= 0

Control Register 2
Bits D

= 1, D

= 1

MT8920B

CMOS

3-12

Interrupt Modes and Servicing

Static Interrupt Mode

A static interrupt is caused when an incoming byte
matches a predefined byte. The incoming byte from
a selected channel is stored in Interrupt Image
Register (1/2) where it is compared with the contents
of the corresponding Match Byte Register. The
result of the comparison of individual bits is masked
by the contents of the Mask Register (1/2) before it
is used to generate an IRQ. After a static interrupt
occurs, information in the Interrupt Image Register is
frozen until the

�

P performs a read operation on this

When servicing static interrupts assertion of IACK
will cause the contents of the Vector Register, with
the IRQ1 or IRQ2 bit set, to be output on the data
bus. The service routine can subsequently clear IRQ
by reading the Interrupt Image Register.
Alternatively, the IRQRST bit in Control Register 1
can be set to clear the associated interrupt registers.

Static Interrupts are selected using IRQ1MODE and
IRQ2MODE bits in Control Register 1. Interrupts are
then enabled to the IRQ pin with IRQ1EN and
IRQ2EN bits of the same register.

Dynamic Interrupt Mode

A dynamic interrupt is generated by a change of
state of bits in a selected channel. A 0 to 1 transition
or a 1 to 0 transition or a simple change of state from
the previous state (toggle) can be detected. The
type of transition to be detected is selected using two
bits, one from the Match Byte Register (1/2) and one
from the Interrupt Mask Register (1/2), in the
corresponding bit positions. Table 5 shows how the
two registers are programmed.

Table 5 - Dynamic Interrupt Types

For example, the following steps are required to
generate an interrupt when bit D

of channel 4

changes state from 0 to 1 (all other bits are masked):

(channel 4 of STi0 selected)

(When bit D

toggles 0 to 1)

Dynamic interrupts from interrupt path 1 would then
be enabled using the Control Register 1.

This would cause interrupt 1 path to be enabled
while interrupt 2 path is disabled.

As with static interrupts, upon serving a dynamic
interrupt, assertion of IACK will cause the contents
of the Vector Register, with the appropriate path bit
set, to be output on the data bus. The information
contained in the channel is frozen in the Interrupt
Image Register. To clear a dynamic interrupt,
however, the

�

P must read the Interrupt Flag

Register of the path responsible for the interrupt to
determine which bit caused the interrupt. The bit in
the corresponding position will be set to 1 and
reading this register will clear its contents.

Alternatively, as with static interrupts, the IRQRST bit
in Control Register 1 can be set to clear the Image
Interrupt Register, Flag Register and path bits in the
Vector Register.

Dynamic Interrupts are selected using IRQ1MODE
and IRQ2MODE bits in Control Register 1 and are
enabled using IRQ1EN and IRQ2EN in the same
register.

MMS Pin Reset

The STPA can be RESET in Mode 1 using the MMS
pin (27). Applying a low pulse (0V) to MMS after
power is applied to the device will reset all control
and interrupt registers to 00

. This can be

accomplished on power up with a simple R-C circuit
as shown in Figure 8.

Figure 8 - MMS Reset Function

Match

Byte

bit D

Mask

Byte

bit D

Transition Type Detected

on Incoming bit D

(x = 0 ....7)

0
0
1
1

0
1
0
1

Mask Bit D

0 to 1 transition
1 to 0 transition

Toggle

Channel Address Register 1 =

Match Byte Register 1 =

Interrupt Mask Register 1 =

Control Register 1 =

MMS

STPA

CMOS

MT8920B

3-13

Mode 2 - Fast RAM Mode

Mode 2 operates as a high speed dual port RAM
interface to the ST-BUS. Only the two transmit
RAM's, Tx0 and Tx1, and the receive RAM, Rx0 are
active in this mode (i.e., control registers and
interrupt registers are inactive).

The main feature of this mode is fast access to the
dual-port RAM's. Fast access allows high-speed
controllers to use this device as a data interface to
T1 and CEPT digital links. Timing information is
shown in Figure 15.

Mode 2 can also support 24 channel and 32 channel
operation. The channel configuration is selected
using 24/32 pin. When 24/32=0 the device operates
in 24 channel mode and when 24/32=1, it operates in
32 channel mode.

The physical interface in this mode resembles that of
a simple RAM device. The signals used to read
and write the device are CS, OE, R/W. The pinout of
the STPA in this mode is shown in Figure 3. Address
decoding for Tx0, Tx1, Rx0 is shown in Table 6.

Contention can arise for access to the dual port
RAMS. The occurrence of this is minimized since
the ST-BUS serial-to-parallel and parallel-to-serial
converters require RAM access for only 1/32 of
a channel time (i.e., last half cycle of

C4i for

each channel). For contention to occur the high
speed controller must access the same RAM
location as that of the ST-BUS. For a parallel read
operation this corresponds to the current ST-BUS
channel and for a write operation, the next ST-BUS
channel. Access contention in Mode 2 is arbitrated
with the BUSY signal.

BUSY is intended to hold

off any parallel access cycle until it again goes
inactive. Figure 16 shows how the access is
arbitrated for accesses near the contention window.

Applications using high speed access can easily
avoid generating BUSY by co-ordinating channel

reads and writes with framing and channel boundary
information.

Mode 3 - Parallel Bus Controller

In this mode the STPA outputs all necessary signals
required to drive devices attached to the parallel
port. The STPA can be used to drive devices such
as RAM's, FIFO's, latches, A/D and D/A converters,
and CODECS, directly from the ST-BUS without an
intervening

�

P. As with the other modes, Mode 3 can

operate from 32 channels or 24 channels by
connecting 24/32 high or low, respectively. This
allows devices to be driven remotely via a T1 or
CEPT digital trunk link when used with Mitel's trunk
products.

Referring to Figure 1, the Address Generator block
generates and drives the external address lines
A4-A0. The STPA also generates OE (output
enable) and

WE (write enable) to facilitate data

transfers from Rx0 RAM and to Tx0 RAM. Tx1 RAM
is unavailable in this mode.

The STPA, in Mode 3, generates external addresses
in a particular sequence that minimizes throughput
delay through the device. When channel N is
present on the ST-BUS, the STPA generates address
N+1 on the address bus and asserts OE to output
data from an external device and latch it into the
STPA. During the same channel N, the STPA
will generate address N-1 with WE asserted to
write from the STPA to an external device. Timing for
Mode 3 transfers is shown in Figure 17. All parallel
bus signals are synchronized to the ST- BUS clock.

The device must be selected using CS in order for
the parallel bus drivers to be enabled. CS should
remain active for four ST-BUS bit periods (8 x C4i
cycles) since a read and a write operation require 2
bit periods each. The STPA generates a signal STCH
(start of channel) which becomes active at the start
of each channel and remains active for 1/2 of the
channel time (Figure 18). This signal may be

Table 6. Mode 2 Address Map

ADDRESS BITS

REGISTERS

READ

WRITE

�
�
�

Rx0 - Channel 0

�
�
�

Rx0 - Channel 31

Tx0 - Channel 0

�
�
�

Tx0 - Channel 31

�
�
�

Rx0 - Channel 0

�
�
�

Rx0 - Channel 31

Tx1 - Channel 0

�
�
�

Tx1 - Channel 31

MT8920B

CMOS

3-14

connected directly to

CS to enable the device

appropriately.

Figure 9 - "Daisy-chained" STPA's in 32 Channel

Parallel Bus Controller Mode (Mode 3)

In order to facilitate efficient use of the parallel bus
another signal, similar to STCH, is supplied by the
STPA. Delayed Chip Select (DCS) becomes active
for the last half of each channel (Figure 19). This
may be connected to a second STPA, residing on the
same physical parallel bus, enabling it to perform its
read/write operations in the second half of each
channel. This allows a large number of devices,

connected on a common bus, to be driven by two
ST-BUS streams. Figure 9 shows how this "daisy
chaining" of STPA's is implemented while Figure 10
illustrates the timing on the shared parallel bus.

Applications

Parallel PBX to Digital Trunk Interface

The STPA is an ideal component for interfacing
parallel PBX environments to Mitel's family of digital
trunk devices.

Figure 11 shows a typical interface for both T1/ESF
and CRC-4 CEPT digital trunks to a system utilizing
a parallel bus architecture. Both the MH89760B
T1/ESF and the MH89790B CRC-4 CEPT trunk
modules are shown interfaced to a parallel bus
structure using two STPAs operating in modes 1 and
2.

The first STPA operating in mode 2 (MMS=0,
MS1=1,

24/32=0), routes data and/or voice

information between the parallel telecom bus and the
T1 or CEPT link via DSTi and DSTo. The second
STPA, operating in mode 1 (MMS=1) provides
access from the signalling and link control bus to the
MH89760B or MH89790B status and control
channels. All signalling and link functions may be
controlled easily through the STPA transmit RAM's
Tx0, Tx1, while status information is read at receive
RAM Rx0. In addition, interrupts can be set up to
notify the system in case of slips, loss of sync,
alarms, violations, etc.

Common Bus

OE
WE

A0
A1
A2
A3
A4

DCS

OE
WE

A0
A1
A2
A3
A4

STCH

STi0

STo0

STi0

STo0

MMS MS1 24/32

Figure 10 - Timing Relationship for Mode 3 Daisy Chaining

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

N + 1

N - 1

N + 1

N - 1

OUT

ST-BUS

C4i

Address

Data Bus

STCH

DCS

CHANNEL N

CMOS

MT8920B

3-17

Connecting the STPA to a shared ST-BUS Line

The STPA's STo0 and STo1 outputs cannot be
directly forced into a high impedance state.
However, with some external logic, the STo0 output
can be buffered by a three-state device, controlled by
the STo1 output. This application is only possible if
the Tx1 RAM and associated STo1 output are not
required for some other purpose.

Figure 13 shows an external buffer U1 controlled by
the STo1 output and an external Output Data Enable
(ODE) signal. When FF (hex) is written to the Tx1
RAM, the corresponding STo1 output channel goes
to logic high. This signal, AND-ed together with a
logic high at ODE, enables U1, resulting in the STo0
signal transparently passed to the output of U1.
When 00 (hex) is written to the Tx1 RAM, the STo1
output goes logic low. This disables U1, resulting in

a high impedance state at the output of U1,
corresponding to the selected channel.

This method of three-state buffering permits output
control on a per-channel or per-bit basis.

The ODE input is used to enable the ST-BUS outputs
after all ST-BUS devices are properly configured by
software. This eliminates the possibility of
contention on the ST-BUS lines during the power-up
state.

Figure 13 - Connecting STPA to a Common ST-BUS Line

Parallel Port

ODE

Parallel Port

STo0

STo1

MT8920B

MT8980

STi0
STi1

STi7

STo7

STo1

STo0

ODE

74HC125

74HC00

ST-BUS

MT8920B

CMOS

3-18

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

Typical figures are at 25

�

C and are for design aid only: not guaranteed and not subject to production testing.

Typical figures are at 25

�

C and are for design aid only: not guaranteed and not subject to production testing.

Absolute Maximum Ratings*

- Voltages are with respect to ground (V

) unless otherwise stated.

Parameter

Symbol

Min

Max

Units

Supply Voltage

-0.3

7.0

Voltage on any I/O pin

-0.3

+ 0.3

Current on any I/O pin

I/O

�

Storage Temperature

-55

125

�

Package Power Dissipation

Cerdip
Plastic

1000

600

mW
mW

Recommended Operating Conditions

- Voltages are with respect to ground (V

) unless otherwise stated.

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Supply Voltage

4.75

5.0

5.25

Input High Voltage

2.4

for 400mV noise margin

Input Low Voltage

0.4

for 400mV noise margin

Operating Temperature

-40

�

Operating Clock Frequency

4.096

MHz

DC Electrical Characteristics

- Voltages are with respect to ground (V

) unless otherwise stated.

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Supply Current

Static

Dynamic

CCS

CCD

�

outputs unloaded
@f

= 4.096 MHz

Input High Voltage

2.0

Input Low Voltage

0.8

Input Leakage Current

�

=5.25V,

to V

Input capacitance

Schmitt trigger input high (MMS)

T+

3.8

3.0

Schmitt trigger input low (MMS)

T-

2.0

1.0

Schmitt trigger hysteresis (MMS)

0.8

1.0

Output high current (except IRQ

)

= 2.4V, V

= 4.75V

Output low current (except IRQ)

= 0.4V, V

= 4.75V

IRQ, DTACK, BUSY Sink Current

= 0.4V, V

= 4.75V

Tristate Leakage A

-A

, OE, WE

(mode 3)

�

= 5.25V

OUT

= V

to V

Open drain off-state current
IRQ, DTACK, BUSY

OFF

�

= 5.25V

OUT

= V

Output capacitance

CMOS

MT8920B

3-19

Timing is over recommended temperature & power supply voltages.
Typical figures are at 25

�

C, V

=5V, t

CLK

=244 ns, t

=122 ns and are for design aid only: not guaranteed and not subject to production

testing.

The cycle is initiated by the falling edge of CS or DS, whichever occurs last. Timing is relative to the last falling edge which initiates the cycle.
(1) t

cwm

is equal to t

or t

whichever is smaller (some ST-BUS compatible transceivers may generate C4 clock having t

CHmin

=70ns

or t

CLmin

=70ns.

(2) Worst case access when memory contention occurs.

Figure 14 - Mode 1 Parallel Bus Timing

During Interrupt Acknowledge cycle IACK replaces CS. R/W must remain high.

AC Electrical Characteristics

- Mode 1 Parallel Bus Timing (see Fig. 14)

=5.0V

�

5%,T

=-40 to 85

�

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Address to DS (CS) Low

ARDS

R/W to DS (CS) Low

RWDS

DS (CS) Low to DTACK Low

RDS

1,2

cwm

CLK

2*t

CLK

Load C

Valid Data to DTACK Low (Read)

cwm

-30

Load A, C

=130pF, R

=740

DS High to DTACK High

DAR

Load C, C

=50pF

DS High to Data High Imped.(Read)

DHZ

Load A, C

=130pF, R

=740

DS High to CS High

CSH

Data Hold Time (Write)

DHT

Input Data Valid after DS

DST

cwm

-30

Address Hold Time

ADHT

A0 - A5

CS (IACK

)

R/W

DTACK

D0 - D7

ADHT

ARDS

RWDS

RDS

DST

DHT

DATA IN

DATA OUT

DHZ

DAR

CSH

MT8920B

CMOS

3-20

Timing is over recommended temperature & power supply voltages.
Typical figures are at 25

�

C, V

=5V, t

CLK

=244 ns, t

=122 ns and are for design aid only: not guaranteed and not subject to production

testing.

Figure 15 - Mode 2 Timing Diagram (No Contention)

AC Electrical Characteristics

- Mode 2 Parallel Bus Timing - (see Figures 15 and 16)

=5.0V

�

5%,T

=-40 to 85

�

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

OE Low to Valid Data

EVD

Load A, C

=130pF, R

=740

Address Access Time

120

Load A, C

=130pF, R

= 740

CS Low to Valid Data

CSD

Load A, C

=130pF, R

=740

Output Disable

OHZ

Load A, C

=130pF, R

=740

Address Setup Time

ASF

Data Setup Time

DST

Data Hold Time

DHT

Address Hold Time

Write Pulse Width

OE, R/W High to C4i High

EC4H

-10

OE, R/W Low to C4i Low

EC4L

C4i High to Busy Low

C4BL

Load C

C4i Low to Busy High

C4BH

Load C

OE, R/W High to Busy Low

EBL

Load C

ASF

OHZ

DST

DHT

EVD

CSD

DATA IN

DATA OUT

A0 - A5

R/W

D0 - D7

MT8920B

CMOS

3-22

Timing is over recommended temperature & power supply voltages.
Typical figures are at 25

�

C, V

=5V,t

CLK

=244ns, t

=122ns and are for design aid only: not guaranteed and not subject to production

testing.

Figure 17 - Mode 3 Timing Diagram

AC Electrical Characteristics

- Mode 3 Timing (see Fig.17, 18 and 19)

((V

=5.0V

�

5%,TA=-40 to 85

�

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

CS to OE, WE, Address Enabled

Load A, C

= 130pF, R

= 740

C4i Low to Address Change

ACS

110

Load A, C

= 130pF, R

= 740

CS to OE, WE, Address Disabled

Load A, C

= 130pF, R

= 740

C4i Low to Output Enable Low

OED

Load A, C

= 130pF, R

= 740

C4i Low to Output Enable High

OEH

Load A, C

= 130pF, R

= 740

OE, WE, Pulse Width

ENPW

2*t

CLK

Load A, C

= 130pF, R

= 740

C4i Low to Write Enable Low

WED

Load A, C

= 130pF, R

= 740

C4i Low to Write Enable High

WEH

Load A, C

= 130pF, R

= 740

Read Data Valid from OE

RST

(2*t

CLK

)

-60

10 Read Data Hold Time

RHT

11 Write Data Setup Time

WST

100

Load A, C

= 130pF, R

= 740

12 Write Data Hold Time

WHT

100

Load A, C

= 130pF, R

= 740

13 C4i Transition to STCH, DCS Trans.

STC

120

Load A, C

= 70pF, R

= 1.22K

14 STCH Pulse Width

SCPW

1830

Load A, C

= 70pF, R

= 1.22K

15 DCS Pulse Width

CSPW

1830

Load A, C

= 70pF, R

= 1.22K

CHANNEL N

BIT 7 (BIT 3)

BIT 6 (BIT 2)

BIT 5 (BIT 1)

BIT 4 (BIT 0)

C4i

A4 - A0

D7 - D0

N + 1

N - 1

DATA IN

DATA OUT

ACS

OED

OEH

ENPW

WED

WEH

ENPW

WHT

WST

RHT

RST

MT8920B

CMOS

3-24

Timing is over recommended temperature & power supply voltages.
Typical figures are at 25

�

C, V

=5V and are for design aid only: not guaranteed and not subject to production testing.

Figure 20 - ST-BUS Timing Diagram

AC Electrical Characteristics

- ST-BUS Timing (see Figure 20)

= 5.0V

�

5%, T

= -40 to 85

�

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Clock C4i Period

CLK

244

Clock C4i Period High

122

Clock C4i Period Low

122

C4i Rise Time

C4i Fall Time

Frame Pulse Setup Time

FPS

Frame Pulse Hold Time

FPH

STo0/1 Delay from C4i

SOD

100

Load B

STi0 Setup Time

STS

STi0 Hold Time

STH

Bit Cell

C4i

F0i

STo0

STo1

STi0

CLK

FPS

FPH

SOD

STS

STH

协谢械泻褌褉芯薪薪褘泄泻芯屑锌芯薪械薪褌: MT8920BP

Document Outline

协谢械泻褌褉芯薪薪褘泄 泻芯屑锌芯薪械薪褌: MT8920BP

Document Outline

协谢械泻褌褉芯薪薪褘泄泻芯屑锌芯薪械薪褌: MT8920BP