9-107

Features

Full duplex transmission over a single twisted
pair

Selectable 80 or 160 kbit/s line rate

Adaptive echo cancellation

Up to 3km (8971B) and 4 km (8972B)

ISDN compatible (2B+D) data format

Transparent modem capability

Frame synchronization and clock extraction

MITEL ST-BUS compatible

Low power (typically 50 mW), single 5V supply

Applications

Digital subscriber lines

High speed data transmission over twisted
wires

Digital PABX line cards and telephone sets

80 or 160 kbit/s single chip modem

Figure 1 - Functional Block Diagram

DSTi/Di

CDSTi/

F0/CLD

C4/TCK

F0o/RCK

MS0

MS1

MS2

RegC

DSTo/Do

CDSTo/

CDo

Transmit
Interface

Prescrambler

Scrambler

Control
Register

Transmit/
Clock
Receive
Timing &
Control

Status

Transmit

Timing

Master Clock

Phase Locked

Sync Detect

Receive

DPLL

Receive

Interface

De-

Prescrambler

Descrambler

Differentially

Encoded Biphase

Receiver

Differentially

Encoded Biphase

Transmitter

Transmit

Filter &

Line Driver

Receive

Filter

-1

MUX

Address

Echo Canceller

Error
Signal

Echo Estimate

Bias

Ref

OUT

DIS

Precan

OSC2

OSC1

CDi

ISSUE 7

May 1995

Description

The MT8971B (DSIC) and MT8972B (DNIC) are
multi-function devices capable of providing high
speed, full duplex digital transmission up to 160
kbit/s over a twisted wire pair. They use adaptive
echo-cancelling techniques and transfer data in
(2B+D) format compatible to the ISDN basic rate.
Several modes of operation allow an easy interface
to digital telecommunication networks including use
as a high speed limited distance modem with data
rates up to 160 kbit/s. Both devices function
identically but with the DSIC having a shorter
maximum loop reach specification. The generic
"DNIC" will be used to reference both devices unless
otherwise noted.

The MT8971B/72B is fabricated in Mitel's ISO

CMOS process.

Ordering Information

MT8971BE

22 Pin Plastic DIP

MT8972BE

22 Pin Plastic DIP

MT8972BC

22 Pin Ceramic DIP

MT8971BP

28 Pin PLCC

MT8972BP

28 Pin PLCC

-40°C to

85°C

MT8971B/72B

Digital Subscriber Interface Circuit

Digital Network Interface Circuit

ISO

-CMOS ST-BUS

FAMILY

MT8971B/72B

9-108

Figure 2 - Pin Connections

Pin Description

Pin #

Name

Description

DIP PLCC

OUT

Line Out. Transmit Signal output (Analog). Referenced to V

Bias

Internal Bias Voltage output. Connect via 0.33 µF decoupling capacitor to V

Ref

Internal Reference Voltage output. Connect via 0.33 µF decoupling capacitor to V

4,5,

5,7,

MS2-MS0 Mode Select inputs (Digital). The logic levels present on these pins select the various

operating modes for a particular application. See Table 1 for the operating modes.

RegC

Regulator Control output (Digital). A 512 kHz clock used for switch mode power
supplies. Unused in MAS/MOD mode and should be left open circuit.

F0/CLD

Frame Pulse/C-Channel Load (Digital). In DN mode a 244 ns wide negative pulse input
for the MASTER indicating the start of the active channel times of the device. Output for
the SLAVE indicating the start of the active channel times of the device. Output in MOD
mode providing a pulse indicating the start of the C-channel.

CDSTi/

CDi

Control/Data ST-BUS In/Control/Data In (Digital). A 2.048 Mbit/s serial control &
signalling input in DN mode. In MOD mode this is a continuous bit stream at the bit rate
selected.

CDSTo/

CDo

Control/Data ST-BUS Out/Control/Data Out (Digital). A 2.048 Mbit/s serial control &
signalling output in DN mode. In MOD mode this is a continuous bit stream at the bit rate
selected.

Negative Power Supply (0V).

DSTo/Do Data ST-BUS Out/Data Out (Digital). A 2.048 Mbit/s serial PCM/data output in DN mode.

In MOD mode this is a continuous bit stream at the bit rate selected.

DSTi/Di

Data ST-BUS In/Data In (Digital). A 2.048 Mbit/s serial PCM/data input in DN mode. In
MOD mode this is a continuous bit stream at the bit rate selected.

F0o/RCK Frame Pulse Out/Receive Bit Rate Clock output (Digital). In DN mode a 244 ns wide

negative pulse indicating the end of the active channel times of the device to allow daisy
chaining. In MOD mode provides the receive bit rate clock to the system.

C4/TCK

Data Clock/Transmit Baud Rate Clock (Digital). A 4.096 MHz TTL compatible clock
input for the MASTER and output for the SLAVE in DN mode. For MOD mode this pin
provides the transmit bit rate clock to the system.

OSC2

Oscillator Output. CMOS Output.

1
2
3
4
5
6
7
8
9

10
11

22
21
20
19
18
17
16
15

22 PIN PDIP/CERDIP

LOUT

VBias

VRef

MS2
MS1
MS0

RegC

F0/CLD

CDSTi/CDi

CDSTo/CDo

VSS

VDD
LIN
TEST
LOUT DIS
Precan
OSC1
OSC2
C4/TCK
F0o/RCK
DSTi/Di
DSTo/Do

28 PIN PLCC

5
6
7
8
9
10
11

25
24
23
22
21
20
19

i
a

VRe

VDD

EST

NC
LOUT DIS
Precan
OSC1
OSC2

C4/TCK

MS2

MS1
MS0

RegC

F0/CLD

CDST

i
/
CDi

CDST

/
CDo

VSS

/
RCK

Ti/D

MT8971B/72B

9-109

Figure 3 - DV Port - 80 kbit/s (Modes 2, 3, 6)

Figure 4 - DV Port - 160 kbit/s (Modes 2, 3, 6)

OSC1

Oscillator Input. CMOS Input. D.C. couple signals to this pin. Refer to D.C. Electrical
Characteristics for OSC1 input requirements.

Precan

Precanceller Disable. When held to Logic '1'

the internal path from L

OUT

to the

precanceller is forced to V

Bias

thus bypassing the precanceller section. When logic '0', the

OUT

to the precanceller path is enabled and functions normally. An internal pulldown (50

) is provided on this pin.

1,6,

11,
18,
20,

No Connection. Leave open circuit.

OUT

DIS L

OUT

Disable. When held to logic "1", L

OUT

is disabled (i.e., output = V

Bias

). When logic

"0", L

OUT

functions normally. An internal pulldown (50 k

) is provided on this pin.

TEST

Test Pin. Connect to V

for normal operation.

Receive Signal input (Analog).

Positive Power Supply (+5V) input.

Pin Description (continued)

Pin #

Name

Description

DIP PLCC

AAAA

AAAAA

AAAA

DSTi

DSTo

F0o

Channel Time 0

AAAA

AAA

AAAA

AAA

AAAA

AAAAA

AAAA

AAAAA

AAAA

DSTi

DSTo

F0o

Channel Time 0

Channel Time 16

MT8971B/72B

9-110

Functional Description

The MT8971B/72B is a device which has been
designed primarily as an interface for the Integrated
Services Digital Network (ISDN). However, it may be
used in practically any application that requires high
speed data transmission over two wires, including
smart telephone sets, workstations, data terminals
and computers.

In the ISDN, the DNIC is ideal for providing the
interface at the U reference point. The device
supports the 2B+D channel format (two 64 kbit/s B-
channels and one 16 kbit/s D-channel) over two
wires as recommended by the CCITT. The line data
is converted to and from the ST-BUS format on the
system side of the network to allow for easy
interfacing with other components such as the S-
interface device in an NT1 arrangement, or to digital
PABX components.

Smart telephone sets with data and voice capability
can be easily implemented using the MT8971B/72B
as a line interface. The device's high bandwidth and
long loop length capability allows its use in a wide
variety of sets. This can be extended to provide full
data and voice capability to the private subscriber by
the installation of equipment in both the home and
central office or remote concentration equipment.
Within the subscriber equipment the MT8971B/72B
would terminate the line and encode/ decode the
data and voice for transmission while additional
electronics could provide interfaces for a standard
telephone set and any number of data ports
supporting standard data rates for such things as
computer communications and telemetry for remote
meter reading. Digital workstations with a high
degree of networking capability can be designed
using the DNIC for the line interface, offering up to
160 kbit/s data transmission over existing telephone
lines. The MT8971B/72B could also be valuable
within existing computer networks for connecting a
large number of terminals to a computer or for
intercomputer links. The highest data rates existing
for terminal to computer links is 19.2 kbit/s over
conventional analog modems. With the DNIC, this
can be increased up to 160 kbit/s at a very low cost
per line for terminal to computer links and in many
cases this bandwidth would be sufficient for
computer to computer links.

Figure 1 shows the block diagram of the MT8971B/
72B. The DNIC provides a bidirectional interface
between the DV (data/voice) port and a full duplex
line operating at 80 or 160 kbit/s over a single pair of
twisted wires. The DNIC has three serial ports. The
DV port (DSTi/Di, DSTo/Do), the CD (control/data)
port (CDSTi/CDi, CDSTo/CDo) and a line port (L

OUT

). The data on the line is made up of information

from the DV and CD ports. The DNIC must combine
information received from both the DV and CD ports
and put it onto the line. At the same time, the data
received from the line must be split into the various
channels and directed to the proper ports. The
usable data rates are 72 and

144 kbit/s as required

for the basic rate interface in ISDN. Full duplex
transmission is made possible through on board
adaptive echo cancellation.

The DNIC has various modes of operation which are
selected through the mode select pins MS0-2. The
two major modes of operation are the MODEM
(MOD) and DIGITAL NETWORK (DN) modes. MOD
mode is a transparent 80 or 160 kbit/s modem. In
DN mode the line carries the B and D channels
formatted for the ISDN at either 80 or 160 kbit/s. In
the DN mode the DV and CD ports are standard ST-
BUS and in MOD mode they are transparent serial
data streams at 80 or 160 kbit/s. Other modes
include: MASTER (MAS) or SLAVE (SLV) mode,
where the timebase and frame synchronization are
provided externally or are extracted from the line and
DUAL or SINGLE (SINGL) port modes, where both
the DV and CD ports are active or where the CD port
is inactive and all information is passed through the
DV port. For a detailed description of the modes

see

"Operating Modes" section.

In DIGITAL NETWORK (DN) mode there are three
channels transferred by the DV and CD ports. They
are the B, C and D channels. The B1 and B2
channels each have a bandwidth of 64 kbit/s and are
used for carrying PCM encoded voice or data. These
channels are always transmitted and received
through the DV port (Figures 3, 4, 5, 6). The C-
channel, having a bandwidth of 64 kbit/s, provides a
means for the system to control the DNIC and for the
DNIC to pass status information back to the system.
The C-channel has a Housekeeping (HK) bit which is
the only bit of the C-channel transmitted and
received on the line. The 2B+D channel bits and the
HK bit are double-buffered. The D-channel can be
transmitted or received on the line with either an 8,
16 or 64 kbit/s bandwidth depending on the DNIC's
mode of operation. Both the HK bit and the D-
channel can be used for end-to-end signalling or low
speed data transfer. In DUAL port mode the C and D
channels are accessed via the CD port (Figure 7)
while in SINGL port mode they are transferred
through the DV port (Figures 5, 6) along with the B1
and B2 channels.

MT8971B/72B

9-111

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g

r
e

DV Po

r
t

-
8

(

,
4

)

i
g

r
e

DV Po

r
t
-

(

,
4

)

AAAA

l T

i
me

-
C

nel

l T

i
me

-
C

ann

l T

i
m

-
C

.
7

DST

AAAA

l T

i
m

D-Ch

i
m

C-Ch

l T

i
me

-
C

.
6

DST

i
m

-
C

han

MT8971B/72B

9-112

In DIGITAL NETWORK (DN) mode, upon entering
the DNIC from the DV and CD ports, the B-channel
data, D-channel D0 (and D1 for 160 kbit/s), the HK
bit of the C-channel (160kbit/s only) and a SYNC bit
are combined in a serial format to be sent out on the
line by the Transmit Interface (Figures 11, 12). The
SYNC bit produces an alternating 1-0 pattern each
frame in order for the remote end to extract the frame
alignment from the line. It is possible for the remote
end to lock on to a data bit pattern which simulates
this alternating 1-0 pattern that is not the true SYNC.
To decrease the probability of this happening the
DNIC may be programmed to put the data through a
prescrambler that scrambles the data according to a
predetermined polynomial with respect to the SYNC
bit. This greatly decreases the probability that the
SYNC pattern can be reproduced by any data on the
line. In order for the echo canceller to function
correctly, a dedicated scrambler is used with a
scrambling algorithm which is different for the SLV
and MAS modes. These algorithms are calculated in
such a way as to provide orthogonality between the

near and far end data streams such that the
correlation between the two signals is very low.

For any two DNICs on a link, one must be in SLV
mode with the other in MAS mode. The scrambled
data is differentially encoded which serves to make
the data on the line polarity-independent. It is then
biphase encoded as shown in Figure 10. See "Line
Interface" section for more details on the encoding.
Before leaving the DNIC the differentially encoded
biphase data is passed through a pulse-shaping
bandpass transmit filter that filters out the high and
low frequency components and conditions the signal
for transmission on the line.

The composite transmit and receive signal is
received at L

On entering the DNIC this signal

passes through a Precanceller which is a summing
amplifier and lowpass filter that partially cancels the
near-end signal and provides first order antialiasing
for the received signal. Internal, partial cancellation
of the near end signal may be disabled by holding

Figure 7 - CD Port (Modes 2,6)

Figure 8 - CD Port (Modes 1,5)

AAAA

AAAAAAAAAA

AAAA

AAAAAAAAAAAAAA

AAAA

AAA

AAAA

AAA

AAAA

AAAAAAAAAAA

AAAA

AAA

AAAA

AAAAAAAAAAAA

AAAA

AAAAA

AAAA

CDSTo

CDSTi

F0o

3.9

sec

62.5

sec

125

sec

Channel Time 0

Channel Time 16

CLD

TCK

CDi

CDo

MT8971B/72B

9-113

the Precan pin high. This mode simplifies the design
of external line transceivers used for loop extension
applications. The Precan pin features an internal
pull-down which allows this pin to be left
unconnected in applications where this function is
not required. The resultant signal passes through
a receive filter to bandlimit and equalize it. At this
point, the echo estimate from the echo canceller is
subtracted from the precancelled received signal.
This difference signal is then input to the echo
canceller as an error signal and also squared up by a
comparator and passed to the biphase receiver.
Within the echo canceller, the sign of this error signal
is determined. Depending on the sign, the echo
estimate is either incremented or decremented and
this new estimate is stored back in RAM.

The timebase in both SLV and MAS modes
(generated internally in SLV mode and externally in
MAS mode) is phase-locked to the received data
stream. This phase-locked clock operates the
Biphase Decoder, Descrambler and Deprescrambler
in MAS mode and the entire chip in SLV mode. The
Biphase Decoder decodes the received encoded bit
stream resulting in the original NRZ data which is
passed onto the Descrambler and Deprescrambler
where the data is restored to its original content by
performing the reverse polynomials. The SYNC bits
are extracted and the Receive Interface separates
the channels and outputs them to the proper ports in
the proper channel times. The destination of the
various channels is the same as that received on the
input DV and CD ports.

The Transmit/Receive Timing and Control block
generates all the clocks for the transmit and receive
functions and controls the entire chip according to
the control register. In order that more than one
DNIC may be connected to the same DV and
CD ports an F0o signal is generated which signals
the next device in a daisy chain that its channel
times are now active. In this arrangement only
the first DNIC in the chain receives the system F0
with the following devices receiving its predecessor's
F0o.

In MOD mode, all the ports have a different format.
The line port again operates at 80 or 160 kbit/s,
however, there is no synchronization overhead, only
transparent data. The DV and CD ports carry serial
data at 80 or 160 kbit/s with the DV port transferring
all the data for the line and the CD port carrying the
C-channel only. In this mode the transfer of data at
both ports is synchronized to the TCK and RCK
clocks for transmit and receive data, respectively.

The CLD signal goes low to indicate the start of the
C-channel data on the CD port. It is used to load and
latch the input and output C-channel but has no
relationship to the data on the DV port.

Operating Modes (MS0-2)

The logic levels

present on the mode select pins

MS0, MS1 and MS2 program the DNIC for different
operating modes and configure the DV and CD ports
accordingly. Table 1 shows the modes
corresponding to the state of MS0-2. These pins
select the DNIC to operate as a MASTER or SLAVE,
in DUAL or SINGLE port operation, in MODEM or
DIGITAL NETWORK mode and the order of the C
and D channels on the CD port. Table 2 provides a
description of each mode and Table 3 gives a pin
configuration according to the mode selected for all
pins that have variable functions. These functions
vary depending on whether it is in MAS or SLV, and
whether DN or MOD mode is used.

The overall mode of operation of the DNIC can be
programmed to be either a baseband modem
(MOD mode) or a digital network transceiver (DN
mode). As a baseband modem, transmit/receive
data is passed transparently through the device at 80
or 160 kbit/s by the DV port. The CD port transfers
the C-channel and D-Channel also at 80 or 160
kbit/s.

In DN mode, both the DV and CD ports operate as
ST-BUS streams at 2.048 Mbit/s. The DV port
transfers data over pins DSTi and DSTo while on the

Table 1. Mode Select Pins

E=Enabled

X=Not Applicable

Blanks are disabled

Mode Select Pins

Mode

Operating Mode

MS2

MS1

MS0

SLV

MAS

DUAL

SINGL

MOD

D-C

C-D

ODE

MT8971B/72B

9-114

CD port, the CDSTi and CDSTo pins are used. The
SINGL port option only exists in DN mode.

In MOD mode, DUAL port operation must be used
and the D, B1 and B2 channel designations no
longer exist. The selection of SLV or MAS will
determine which of the DNICs is using the externally
supplied clock and which is phase locking to the data
on the line. Due to jitter and end to end delay, one
end must be the master to generate all the timing for
the link and the other must extract the timing from
the receive data and synchronize itself to this timing
in order to recover the synchronous data. DUAL port
mode allows the user to use two separate serial

busses: the DV port for PCM/data (B channels) and
the CD port for control and signalling information (C
and D channels). In the SINGL port mode, all four
channels are concatenated into one serial stream
and input to the DNIC via the DV port. The order of
the C and D channels may be changed only in DN/
DUAL mode. The DNIC may be configured to
transfer the D-channel in channel 0 and the C-
channel in channel 16 or vice versa. One other
feature exists; ODE, where both the DV and CD
ports are tristated in order that no devices are
damaged due to excessive loading while all DNICs
are in a random state on power up in a daisy chain
arrangement.

Table 2. Mode Definitions

Table 3. Pin Configurations

Mode

Function

SLV

SLAVE

The chip timebase is extracted from the received line data and the external 10.24 MHz

crystal is phase locked to it to provide clocks for the entire device and are output for the external
system to synchronize to.

MAS

MASTER

The timebase is derived from the externally supplied data clocks and 10.24 MHz clock

which must be frequency locked. The transmit data is synchronized to the system timing with the
receive data recovered by a clock extracted from the receive data and resynchronized to the system
timing.

DUAL

DUAL PORT

Both the CD and DV ports are active with the CD port transferring the C&D channels

and the DV port transferring the B1& B2 channels.

SINGL

SINGLE PORT - The B1& B2, C and D channels are all transferred through the DV port. The CD
port is disabled and CDSTi should be pulled high.

MOD

MODEM

Baseband operation at 80 or 160 kbits/s. The line data is received and transmitted

through the DV port at the baud rate selected. The C-channel is transferred through the CD port
also at the baud rate and is synchronized to the CLD output.

DIGITAL NETWORK

Intended for use in the digital network with the DV and CD ports operating at

2.048 Mbits/s and the line at 80 or 160 kbits/s configured according to the applicable ISDN
recommendation.

D-C

D BEFORE C-CHANNEL

The D-channel is transferred before the C-channel following F0.

C-D

C BEFORE D-CHANNEL

The C-channel is transferred before the D-channel following F0.

ODE

OUTPUT DATA ENABLE

When mode 7 is selected, the DV and CD ports are put in high

impedance state. This is intended for power-up reset to avoid bus contention and possible damage
to the device during the initial random state in a daisy chain configuration of DNICs. In all the other
modes of operation DV and CD ports are enabled during the appropriate channel times.

Mode

F0/CLD

F0o/RCK

C4/TCK

Name

Input/Output

Name

Input/Output

Name

Input/Output

Input

F0o

Output

Input

CLD

Output

RCK

Output

TCK

Output

Input

F0o

Output

Input

F0o

Output

Input

Output

F0o

Output

CLD

Output

RCK

Output

TCK

Output

F0o

Output

Input

F0o

Output

Input

MT8971B/72B

9-115

DV Port (DSTi/Di, DSTo/Do)

The DV port transfers data or PCM encoded voice to
and from the line according to the particular mode
selected by the mode select pins. The modes
affecting the configuration of the DV port are MOD or
DN and DUAL or SINGL. In DN mode the DV port
operates as an ST-BUS at 2.048 Mbit/s with 32, 8 bit
channels per frame as shown in Figure 9. In this
mode the DV port channel configuration depends
upon whether DUAL or SINGL port is selected.
When DUAL port mode is used, the C and D
channels are passed through the CD port and the B1
and B2 channels are passed through the DV port. At
80 kbit/s only one channel of the available 32 at the
DV port is utilized, this being channel 0 which carries
the B1-channel. This is shown in

Figure 3. At 160

kbit/s, two channels are used, these

being 0 and 16

carrying the B1 and B2 channels, respectively. This
is shown in Figure 4. When SINGL port mode is
used, channels B1, B2, C and D are all passed via
the DV port and the CD port is disabled. See CD port
description for an explanation of the C and D
channels.

The D-channel is always passed during channel time
0 followed by the C and B1 channels in channel
times 1 and 2, respectively for 80 kbit/s. See Figure
5. For 160 kbit/s the B2 channel is added and
occupies channel time 3 of the DV port. See Figure
6. For all of the various configurations the bit orders
are shown by the respective diagram. In MOD mode
the DV and CD ports no longer operate at 2.048
Mbits/s but are continuous serial bit streams
operating at the bit rate selected of 80 or 160 kbit/s.
While in the MOD mode only DUAL port operation
can be used.

In order for more than one DNIC to be connected to
any one DV and CD port, making more efficient use
of the busses, the DSTo and CDSTo outputs are put
into high impedance during the inactive channel
times of the DNIC. This allows additional DNICs to
be cascaded onto the same DV and CD ports. When
used in this way a signal called F0o is used as an

indication to the next DNIC in a daisy chain that its
channel time is now active. Only the first DNIC in the
chain receives the system frame pulse and all
others receive the F0o from its predecessor in
the chain. This allows up to 16 DNICs to be
cascaded.

CD Port (CDSTi/CDi, CDSTo/CDo)

The CD port is a serial bidirectional port used only in
DUAL port mode. It is a means by which the DNIC
receives its control information for things such as
setting the bit rate, enabling internal loopback tests,
sending status information back to the system and
transferring low speed signalling data to and from
the line.

The CD port is composed of the C and D-Channels.
The C-channel is used for transferring control and
status information between the DNIC and the
system. The D-channel is used for sending and
receiving signalling information and lower speed
data between the line and the system. In DN/DUAL
mode the DNIC receives a C-channel on CDSTi
while transmitting a C-channel on

CDSTo.

ifteen

channel times later (halfway through the frame) a D-
channel is received on CDSTi while a D-channel is
transmitted on CDSTo. This is shown in Figure 7.
The order of the C and D bytes in DUAL port mode
can be reversed by the mode select pins. See Table
1 for a listing of the byte orientations.

The D-channel exists only in DN mode and may be
used for transferring low speed data or signalling
information over the line at 8, 16 or 64 kbit/s (by
using the DINB feature). The information passes
transparently through the DNIC and is transmitted to
or received from the line at the bit rate selected in
the Control Register.

If the bit rate is 80 kbit/s, only D0 is transmitted and
received. At 160 kbit/s, D0 and D1 are transmitted
and received. When the DINB bit is set in the Control
Register the entire D-channel is transmitted and
received in the B1-channel timeslot.

Figure 9 - ST-BUS Format

Channel

· · · · · · · ·

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

125

sec

Channel

ST-BUS

Most

Significant

Bit (First)

Least
Significant
Bit (Last)

3.9

sec

MT8971B/72B

9-116

The C-channel is used for transferring control and
status information between the DNIC and the
system. The Control and Diagnostics Registers are
accessed through the C-channel. They contain
information to control the

DNIC and carry out the

diagnostics as well as the HK bit to be transmitted on
the line as described in Tables 4 and 5. Bits 0 and 1
of the C-channel select between the Control and
Diagnostics Register. If these bits are 0, 0 then the
C-channel information is written to the Control
Register (Table 4). If they are 0, 1 the C-

hannel is

written to the Diagnostics Register (Table 5).

The Diagnostics Register Reset bit (bit 2) of the
Control Register determines the reset state of the
Diagnostics Register. If, on writing to the Control

Register, this bit is set to logic "0", the Diagnostics
Register will be reset coincident with the frame
pulse. When this bit is logic "1", the Diagnostics
Register will not be reset. In order to use the
diagnostic features, the Diagnostics Register must
be continuously written to. The output C-channel
sends status information from the Status Register to
the system along with the received HK bit as shown
in Table 6.

In MOD mode, the CD port is no longer an ST-BUS
but is a serial bit stream operating at the bit rate
selected. It continues to transfer the C-channel but
the D-channel and the HK bit no longer exist. DUAL
port operation must be used in MOD mode. The C-
channel is clocked in and out of the CD port by TCK

Table 4. Control Register

Notes:

Suggested use of ATTACK:
-At 160 kbit/s full convergence requires 850 ms with ATTACK held high for the first 240 frames or 30 ms.
-At 80 kbit/s full convergence requires 1.75 s with ATTACK held high for the first 480 frames or 60 ms.

When bits 4-7 of the Control Register are all set to one, the DNIC operates in one of the default modes as defined in Table 4a,

depending upon the status of bit-3.

Bit

Name

Description

Reg Sel-1

Reg Sel-2

DRR

Diagnostics Register Reset. Writing a "0" to this bit will cause a diagnostics register reset
to occur coincident with the next frame pulse as in the MT8972A. When this bit is a logic
"1", the Diagnostics Register will not be reset.

BRS

Bit Rate Select. When set to '0' selects 80 kbit/s. When set to '1', selects 160 kbit/s.

DINB

D-Channel in B Timeslot. When '0', the D-channel bits (D0 or D0 and D1) corresponding
to the selected bit rate (80 or 160 kbit/s) are transmitted during the normal D-channel bit
times. When set to '1', the entire D-channel (D0-D7) is transmitted during the B1-channel
timeslot on the line providing a 64 kbit/s D-channel link.

PSEN

Prescrambler/Deprescrambler Enable. When set to '1', the data prescrambler and
deprescrambler are enabled. When set to '0', the data prescrambler and deprescrambler
are disabled.

ATTACK

Convergence Speedup. When set to '1', the echo canceller will converge to the reflection
coefficient much faster. Used on power-up for fast convergence.

When '0', the echo

canceller will require the normal amount of time to converge to a reflection coefficient.

TxHK

Transmit Housekeeping. When set to '0', logic zero is transmitted over the line as
Housekeeping Bit. When set to '1', logic one is transmitted over the line as
Housekeeping Bit.

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

Reg Sel-1

Reg Sel-2

DRR

BRS

DINB

PSEN

ATTACK

TxHK

Default Mode Selection (Refer to Table 4a)

MT8971B/72B

9-117

Table 4a. Default Mode Selection

Notes:

Default Mode 1 can also be selected by tying CDSTi/CDi pin low when DNIC is operating in dual mode.

Default Mode 2 can also be selected by tying CDSTi/CDi pin high when DNIC is operating in dual mode.

Table 5. Diagnostic Register

Notes:

When bits 4-7 of the Diagnostic Register are all set to one, the DNIC operates in one of the default modes as defined in Table 4a,

depending upon the status of bit-3.

Do not use L

OUT

to L

loopback in DN/SLV mode.

Do not use DSTo to DSTi loopback in MOD/MAS mode.

C-Channel

(Bit 0-7)

Internal Control

Register

Internal Diagnostic

Register

Description

XXX01111

00000000

01000000

Default Mode-1

: Bit rate is 80 kbit/s. ATTACK,

PSEN, DINB, DRR and all diagnostics are disabled.
TxHK=0.

XXX11111

00010000

01000000

Default Mode-2

Bit rate is 160 kbit/s. ATTACK,

PSEN, DINB, DRR and all diagnostics are disabled.
TxHK=0.

Bit

Name

Description

Reg Sel-1

Reg Sel-2

2,3

Loopback

Bit 2

Bit 3

All loopback testing functions disabled. Normal operation.

DSTi internally looped back into DSTo for system diagnostics.

OUT

is internally looped back into L

for system diagnostics.

DSTo is internally looped back into DSTi for end-to-end testing.

FUN

Force Unsync. When set to '1', the DNIC is forced out-of-sync to test the SYNC
recovery circuitry. When set to '0', the operation continues in synchronization.

PSWAP

Polynomial Swap. When set to '1', the scrambling and descrambling polynomials
are interchanged (use for MAS mode only). When set to '0', the polynomials retain
their normal designations.

DLO

Disable Line Out. When set to '1', the signal on L

OUT

is set set to V

Bias

. When set to

'0', L

OUT

pin functions normally.

Not Used

Must be set to '0' for normal operation.

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

Reg Sel-1

Reg Sel-2

Loopback

FUN

PSWAP

DLO

Not Used

Default Mode Selection

(Refer to Table 4a)

and CLD with TCK defining the bits and CLD the
channel boundaries of the data stream as shown in
Figure 8.

Line Port (L

, L

OUT

)

The line interface is made up of L

OUT

and L

with

OUT

driving the transmit signal onto the line and L

receiving the composite transmit and receive signal

from the line. The line code used in the DNIC is
Biphase and is shown in Figure 10. The scrambled
NRZ data is differentially encoded meaning the
previous differential encoded output is XOR'd with
the current data bit which produces the current
output. This is then biphase encoded where
transitions occur midway through the bit cell with a
negative going transition indicating a logic "0" and a
positive going transition indicating a logic "1".

MT8971B/72B

9-118

Table 6. Status Register

Status

Register

Name

Function

SYNC

Synchronization - When set this bit indicates that synchronization to the received
line data sync pattern has been acquired. For DN mode only.

1-2

CHQual

Channel Quality - These bits provide an estimate of the receiver's margin against
noise. The farther this 2 bit value is from 0 the better the SNR.

Housekeeping - This bit is the received housekeeping (HK) bit from the far end.

4-6

Future

Future Functionality. These bits return Logic 1 when read.

This bit provides a hardware identifier for the DNIC revision. The MT8972B will return
a logic "0" for this bit. (Logic "1" returned for MT8972A.)

SYNC

CHQual

Rx HK

Future Functionality

There are some major reasons for using a biphase
line code. The power density is concentrated in a
spectral region that minimizes dispersion and
differential attenuation. This can shorten the line
response and reduce the intersymbol interference
which are critical for adaptive echo cancellation.
There are regular zero crossings halfway through
every bit cell or baud which allows simple clock
extraction at the receiving end. There is no D.C.
content in the code so that phantom power feed may
be applied to the line and simple transformer
coupling may be used with no effect on the data. It is
bipolar, making data reception simple and providing
a high signal to noise ratio. The signal is then passed
through a bandpass filter which conditions the signal
for the line by limiting the spectral content from
0.2f

Baud

to 1.6f

Baud

and on to a line driver where it is

made available to be put onto the line biased at
V

Bias

. The resulting transmit signal will have a

distributed spectrum with a peak at 3/4f

Baud

. The

transmit signal (L

OUT

) may be disabled by holding the

OUT

DIS pin high or by writing DLO (bit 6) of the

Diagnostics Register to logic "1". When disabled,
L

OUT

is forced to the V

Bias

level. L

OUT

DIS has an

internal pull-down to allow this pin to be left not
connected in applications where this function is not
required. The receive signal is the above transmit
signal superimposed on the signal from the remote
end and any reflections or delayed symbols of the
near end signal.

The frame format of the transmit data on the line is
shown in Figures 11 and 12 for the DN mode at 80
and 160 kbit/s. At 80 kbit/s a SYNC bit for frame
recovery, one bit of the D-channel and the B1-
channel are transmitted. At 160 kbit/s a SYNC bit,
the HK bit, two bits of the D-channel and both B1 and
B2 channels are transmitted.

If the DINB bit of the Control Register is set, the
entire D-channel is transmitted during the B1-
channel timeslot. In MOD mode the SYNC, HK and
D-channel bits are not transmitted or received but
rather a continuous data stream at 80 or 160 kbit/s is
present. No frame recovery information is present on
the line in MOD mode.

MT8971B/72B

9-119

Figure 10 - Data & Line Encoding

Figure 11 - Frame Format - 80 kbit/s (Modes 0, 2, 3, 4, 6)

Figure 12 - Frame Format - 160 kbit/s (Modes 0, 2, 3, 4, 6)

Bits

Data

NRZ Data

Differential

Encoded

Differential

Encoded

Biphase

Transmit

Line Signal

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bias

Note:

Last bit sent was a logic 0

OUT

SYNC

OUT

SYNC

HK0

SYNC

MT8971B/72B

9-120

Applications

Typical connection diagrams are shown in Figures
13 and 14 for the DN mode as a MASTER and
SLAVE, respectively. L

OUT

is connected to the

coupling transformer through a resistor R2 and
capacitors C2 and C2' to match the line
characteristic impedance. Suggested values of R2,
C2 and C2' for 80 and 160 kbit/s operation are
provided in Figures 13 and 14. Overvoltage
protection is provided by R1, D1 and D2. C1 is
present to properly bias the received line signal for
the L

input. A 2:1 coupling transformer is used to

couple to the line with a secondary center tap for
optional phantom power feed. Varistors have been
shown for surge protection against such things as
lightning strikes.

If the scramblers power up with all zeros in them,
they are not capable of randomizing all-zeros data
sequence. This increases the correlation between
the transmit and receive data which may cause loss
of convergence in the echo canceller and high bit
error rates.

In DN mode the insertion of the SYNC pattern will
provide enough pseudo-random activity to maintain
convergence. In MOD mode the SYNC pattern is not
inserted. For this reason, at least one "1" must be fed
into the DNIC on power up to ensure that the
scramblers will randomize any subsequent all-zeros
sequence.

Figure 13 - Typical Connection Diagram - MAS/DN Mode, 160 kbit/s

Figure 14 - Typical Connection Diagram - SLV/DN Mode, 160 kbit/s

DV Port ST-BUS

CD Port ST-BUS

Master Clocks

Mode Select

Lines

{

+5V

0.33

DSTi

DSTo

CDSTi

CDSTo

MS0

MS1

MS2

Ref

Bias

OUT

OSC1

OSC2

F0o

D.C. coupled,
Frequency locked
10.24 MHz clock.

R2 = 390

R1 = 47

C2' = 1.5 nF

C2 = 22 nF

+5V

D1 = D2 = MUR405

2 : 1

1.0

Line Feed
Voltage

For 80 kbit/s: C2' = 3.3 nF

C1 = 0.33

68 Volts
(Typ)
2.5 Joules
0.02 Watt

Note: Low leakage diodes (1 & 2) are required so
that the DC voltage at L

Bias

To Next DNIC

MT8971B/72B

Refer to AC Electrical
Characteristics

DN Mode

Clock Timing

DV Port ST-BUS

CD Port ST-BUS

Master Clocks

Mode Select

Lines

+5V

0.33

DSTi

DSTo

CDSTi

CDSTo

MS0

MS1

MS2

Ref

Bias

OUT

OSC1

OSC2

R2 = 390

R1 = 47

C2' = 1.5 nF

C2 = 22 nF

+5V

D1 = D2 = MUR405

2:1

{

1.0

For 80 kbit/s: C2' = 3.3 nF

C1 = 0.33

68 Volts
(Typ)

0.02 Watt

Note: Low leakage diodes (1 & 2) are required so

2.5 Joules

that the DC voltage at L

Bias

10.24 MHz XTAL

C3=33pF=C4

Supply

MT8971B/72B

MT8971B/72B

9-121

** Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

* Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Parameters over recommended temperature & power supply voltage ranges.

Absolute Maximum Ratings

- Voltages are with respect to ground (V

) unless otherwise stated.

Parameter

Symbol

Min

Max

Units

Supply Voltage

-0.3

Voltage on any pin (other than supply)

Max

-0.3

+0.3

Current on any pin (other than supply)

Max

Storage Temperature

-65

+150

°C

Package Power Dissipation

(Derate 16mW/°C above 75°C)

Diss

750

Recommended Operating Conditions

- Voltages are with respect to ground (V

) unless otherwise stated.

Characteristics

Sym

Min

Typ*

Max

Units

Test Conditions

Operating Supply Voltage

4.75

5.00

5.25

Operating Temperature

-40

+85

°C

Input High Voltage (except OSC1)

2.4

for 400 mV noise margin

Input Low Voltage (except OSC1)

0.4

for 400 mV noise margin

DC Electrical Characteristics

- Voltages are with respect to ground (V

) unless otherwise stated.

Characteristics

Sym

Min

Typ*

Max

Units

Test Conditions

T
P

T
S

Operating Supply Current

Output High Voltage (ex OSC2)

2.4

=10mA

Output High Current
(except OSC2)

Output High Current - OSC2

Source current. V

=2.4V

Source current. V

=3.0V

Source current V

=3.5V

Output Low Voltage (ex OSC2)

0.4

=5mA

Output Low Current
(except OSC2)

Output Low Current - OSC2

7.5

Sink current. V

=0.4V

Sink current. V

=2.0V

Sink current. V

=1.5V

High Imped. Output Leakage

to V

Output Voltage

Ref

)

Bias

)

Bias

1.8

V
V

N
P
U

T
S

Input High Voltage (ex OSC1)

2.0

Input Low Voltage (ex OSC1)

0.8

Input High Voltage (OSC1)

IHo

4.0

Input Low Voltage (OSC1)

ILo

1.0

Input Leakage Current

to V

Input Pulldown Impedance
L

OUT

DIS and Precan

Input Leakage Current for
OSC1 Input

IOSC

MT8971B/72B

9-122

Timing is over recommended temperature & power supply voltages.
* Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

Duty cycle is measured at V

/2 volts.

Timing is over recommended temperature & power supply voltages.
* Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Notes:

When operating as a SLAVE the C4 clock has a 40% duty cycle.

When operating in MAS/DN Mode, the C4 and Oscillator clocks must be externally frequency-locked (i.e.,
F

=2.5xf

). The relative phase between these two clocks (

in Fig. 17) is not critical and may vary from

0 ns to t

C4P

. However, the relative jitter must be less than J

(see Figure 17).

Figure 15 - C4 Clock & Frame Pulse Alignment for ST-BUS Streams

AC Electrical Characteristics

- Voltages are with respect to ground (V

) unless otherwise stated.

Characteristics

Sym

Min

Typ*

Max

Units

Test Conditions

N
P
U

Input Voltage

IN)

5.0

Input Current

)

-10

+10

Baud

=160 kHz

Input Impedance

)

Baud

=160 kHz

Crystal/Clock Frequency

10.24

MHz

Crystal/Clock Tolerance

-100

+100

ppm

Crystal/Clock Duty Cycle

Normal temp. & V

Crystal/Clock Duty Cycle

Recommended at max./
min. temp. & V

Crystal/Clock Loading

From OSC1 & OSC2 to V

O
U

P
U

Output Capacitance

OUT

)

Load Resistance

OUT

)

Bias

, V

Ref

)

Lout

500
100

Load Capacitance

OUT

)

Bias

, V

Ref

)

Lout

0.1

pF
µF

Capacitance to V

Bias

Output Voltage

OUT

)

3.2

4.3

4.6

Lout

= 500

, C

Lout

= 20pF

AC Electrical Characteristics

- Clock Timing - DN Mode (Figures 16 & 17)

Characteristics

Sym

Min

Typ*

Max

Units

Test Conditions

C4 Clock Period

C4P

244

C4 Clock Width High or Low

C4W

122

150

In Master Mode - Note 1

Frame Pulse Setup Time

F0S

Frame Pulse Hold Time

F0H

Frame Pulse Width

F0W

172

244

10.24 MHz Clock Jitter (wrt C4)

-15

+15

Note 2

Channel 31

Bit 0

Channel 0

Bit 7

Channel 0

Bit 6

F0b

ST-BUS
BIT CELLS

MT8971B/72B

9-123

Figure 16 - C4 Clock & Frame Pulse Alignment for ST-BUS Streams in DN Mode

Figure 17 - Frequency Locking for the C4 and OSC1 Clocks in MAS/DN Mode

Timing is over recommended temperature & power supply voltage ranges.
* Typical figures are at 25°C, for design aid only: not guaranteed and not subject to production testing.

Figure 18 - RCK, TCK & CLD Timing For MOD Mode

AC Electrical Characteristics

- Clock Timing - MOD Mode (Figure 18)

Characteristics

Sym

80 kbit/s

160 kbit/s

Units

Test

Conditions

Min

Typ*

Max Min

Typ*

Max

1 TCK/RCK Clock Period

12.5

6.25

µs

2 TCK/RCK Clock Width

6.25

3.125

µs

3 TCK/RCK Clock Transition Time

=40pF

4 CLD to TCK Setup Time

CLDS

3.125

1.56

µs

5 CLD to TCK Hold Time

CLDH

3.125

1.56

µs

6 CLD Width Low

CLDW

6.05

2.925

µs

7 CLD Period

CLDP

µs

2.0V

0.8V

2.0V

0.8V

C4P

C4W

F0S

F0H

F0W

C4W

OSC1

2.0V

0.8V

3.0V

2.0V

RCK

TCK

CLD

CLDS

CLDH

CLDW

2.4V

0.4V

2.4V

0.4V

2.4V

0.4V

Note 1: TCK and CLD are generated on chip and provide the data clocks for the CD port and the transmit section of the

DV port. RCK, also generated on chip, is extracted from the receive data and only clocks out the data at the D

output

and may be skewed with respect to TCK due to end-to-end delay.

Note 2: At the slave end TCK is phase locked to RCK.

The rising edge of TCK will lead the rising edge of RCK by approximately 90

MT8971B/72B

9-124

Timing is over recommended temperature & power supply voltage ranges.
* Typical figures are at 25°C, for design aid only: not guaranteed and not subject to production testing.

Figure 19 - Data Timing For DN Mode

Timing is over recommended temperature & power supply voltage ranges.
* Typical figures are at 25°C, for design aid only: not guaranteed and not subject to production testing.

Note 1: Attenuation measured from Master L

OUT

to Slave L

at 3/4baud frequency.

* Typical figures are at 25°C, for design aid only: not guaranteed and not subject to production testing.

AC Electrical Characteristics

- Data Timing - DN Mode (Figure 19)

Characteristics

Sym

Min

Typ*

Max

Units

Test Conditions

DSTi/CDSTi Data Setup Time

DSTi/CDSTi Data Hold Time

DSTo/CDSTo Data Delay

120

=40pF

DSTo/CDSTo High Z to Data Delay

ZTD

100

140

=40pF

AC Electrical Characteristics

- Data Timing - MOD Mode (Figure 20)

Characteristics

Sym

80 kbit/s

160 kbit/s

Units

Test

Conditions

Min

Typ*

Max Min

Typ*

Max

Di/CDi Data Setup Time

150

Di/CDi Data Hold Time

4.5

2.5

µs

Do Data Delay Time

100

=40pF

CDo Data Delay Time

100

=40pF

Performance Characteristics of the MT8971B DSIC

Characteristics

Sym

Min

Typ*

Max

Units

Test Conditions

Allowable Attenuation for Bit Error
Rate of 10

-6

(Note 1)

SNR

16.5dB (300kHz

bandlimited noise)

Line Length at 80 kbit/s

-24 AWG
-26 AWG

3.0
2.2

attenuation - 6.9 dB/km
attenuation - 10.0 dB/km

Line Length at 160 kbit/s -24 AWG

-26 AWG

160

3.0
2.2

attenuation - 8.0 dB/km
attenuation - 11.5 dB/km

Performance Characteristics of the MT8972B DNIC

Characteristics

Sym

Min

Typ*

Max

Units

Test Conditions

Allowable Attenuation for Bit Error
Rate of 10

-6

(Note 1)

SNR

16.5dB (300kHz

bandlimited noise)

Line Length at 80 kbit/s

-24 AWG
-26 AWG

5.0
3.4

attenuation - 6.9 dB/km
attenuation - 10.0 dB/km

Line Length at 160 kbit/s -24 AWG

-26 AWG

160

4.0
3.0

attenuation - 8.0 dB/km
attenuation - 11.5 dB/km

2.0V

0.8V

2.4V

0.4V

2.0V

0.8V

Bit

Stream

DSTi

CDSTi

DSTo

CDSTo

Bit Cell

ZTD

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