5-3

MT90710

High-Speed Isochronous Multiplexer

Features

Multiplexes eight 2.048 Mbit/s, ST-BUS links
onto one serial high-speed 20.48 Mbit/s link

15.808 Mbit/s clear bandwidth transport

Two 8 kbit/s and one 32 kbit/s oversampled
signalling channels

Embedded system timing and frame
synchronization

Frame buffer control signals generated on-chip

Check-sum generated on multiplexed frame

Remote synchronization indication

Both master and slave timing mode operation

On-chip reference generation for slave mode
synchronization

4B/5B data encoding/decoding

Applications

Fibre distributed sytems

Backplane concentrators

Local Area Networks (LANs)

Description

The High-Speed Isochronous Multiplexer integrated
circuit multiplexes up to eight Serial Telecom
(ST-BUS) links onto a single 20 MHz loop to facilitate
point-to-point data transport requirements. The
MT90710 connects easily with standard Fiber Optic
interfaces to form a complete electric to photonic
conversion circuit. Optical transmission allows large
bandwidth inter-shelf or, in distributed systems,
inter-node communication by eliminating multiple
data buses, cable inter-connect and attendant driver
interfaces. The final result is a simple physical
interface free of the radiated emissions and
background noise susceptibility problems
encountered in copper-wired environments.

Ordering Information

MT90710AP 84 Pin PLCC

0 °C to +70 °C

BADDR

FBW

STi0

STi5

STi6A
STi6B

STi7

DIN8K0
DIN8K1
DIN32K

MUX

STo0

STo5

STo6A
STo6B

STo7

DOUT8K0
DOUT8K1
DOUT32K

DEMUX

Overhead

Checksum

Frame Sync

4B/5B &

NRZI

Encode

Overhead

Extract &

Insert

Error Check

Frame Alignment & Buffer

External Memory Control

Control

RECEIVE

TRANSMIT

MODE0
MODE1
MODE2
F0b
C4b
E20i
RLED
LLED
C20o
POR
RESET
C4REFo

C4o
C40i

NRZI Decode

Sync Detect

4B/5B Decode

SIP

TxDATA

From Receive Pin Diode,

Pre-amp and Post-amp

Circuits

To Transmit Driver

Amplifier and Fiber

Driver Transducer

Signals to

External PLL

ISSUE 1

January 1995

Figure 1 - Functional Block Diagram

CMOS

Preliminary Information

MT90710

Preliminary Information

5-4

Figure 2 - Pin Connections

Pin Description

Pin #

Name

Description

Power Supply Ground. Nominally 0 volts.

Positive Power Supply. Nominally 5 volts.

STo7

Serial, 32 Channel, 2.048 Mb/s Link 7 (Output Type 3). Only channels 9 - 31 are
available for user data transfer (1.474 Mb/s). Channels 0 - 8 (0.576 Mb/s) are reserved
for access to fiber overhead information. Output is active only when the receiver
detects the synchronization pattern on RxDATA input stream; output is high impedance
during loss of synchronization.

DOUT8K0

Asynchronous 8 kHz Signal 0 (Output Type 3). Sourced from the far-end DIN8K0
input.

DOUT8K1

Asynchronous 8 kHz Signal 1 (Output Type 3). Sourced from the far-end DIN8K1
input.

C20o

20.48 MHz Clock (Output Type 3). Derived from transmit PLL 40.96 MHz clock divided
by 2 (see pin 18). Made available for system use.

No Internal Connection.

FBADDR7

Frame Buffer RAM Address Bit 7 (Output Type 2).

STo6A

Serial, 32 Channel, 2.048 Mb/s Link 6A (Output Type 3). Output is active only when
the receiver detects the synchronization pattern on RxDATA input stream; output is high
impedance during loss of synchronization.

VSS

DDR0

DDR1

DDR2

DDR3

DDR4

DDR5

DDR6

o6B

VSS

C20

DDR7

o6A

VSS

E20i

STi7

STi6B

STi6A

STi5

STi4

STi3

VDD

STi2

C40i

C4REFo

C4o

VSS

VDD

POR

FBDATA7

C4b

DIN8K0

FBDATA4

DIN32K

VDD

STi0

FBDATA2

VSS

FBDATA3

DIN8K1

FBDATA1

LLED

FBDATA0

RESET

VDD

32K

RLE

84 PIN PLCC

VSS

STi1

FBDATA6

FBDATA5

Preliminary Information

MT90710

5-5

STo5

Serial, 32 Channel, 2.048 Mb/s Link 5 (Output Type 3). Output is active only when
the receiver detects the synchronization pattern on RxDATA input stream; output is high
impedance during loss of synchronization.

Positive Power Supply. Nominally 5 volts.

Power Supply Ground. Nominally 0 volts.

C4o

4.096 MHz Clock (Output Type 3). Used by the transmit PLL. This clock is the input
C40i (40.96MHz, see pin 18) master clock divided by 10 (inverted) and is fed back to
the external PLL circuit as a reference.

C4REFo

4.096 MHz Reference Clock (Output Type 3). Used by transmit PLL. When in control-
ler mode this clock is derived from the system C4b (4.096 MHz) clock input (see pin
57). When in peripheral mode this clock is extracted from the receive data on the fiber
port.

15,16,

No Internal Connection.

C40i

Transmit 40.96 MHz Clock (Input Type 2). Derived from the transmit PLL. This is the
master clock used by the device.

STi1

Serial, 32 Channel, 2.048 Mb/s Link 1 (Input Type 1).

STi2

Serial, 32 Channel, 2.048 Mb/s Link 2 (Input Type 1).

Power Supply Ground. Nominally 0 volts.

Positive Power Supply. Nominally 5 volts.

STi3

Serial, 32 Channel, 2.048 Mb/s Link 3 (Input Type 1).

STi4

Serial, 32 Channel, 2.048 Mb/s Link 4 (Input Type 1).

STi5

Serial, 32 Channel, 2.048 Mb/s Link 5 (Input Type 1).

STi6A

Serial, 32 Channel, 2.048 Mb/s Link 6A (Input Type 1).

STi6B

Serial, 32 Channel, 2.048 Mb/s Link 6B (Input Type 1).

STi7

Serial, 32 Channel, 2.048 Mb/s Link 7 (Input Type 1). Only channels 9 - 31 are avail-
able for user data transfer (1.472 Mb/s). Data input on channels 0 - 8 (0.576 Mb/s) is
ignored by the device. This bandwidth is reserved for fiber overhead information.

E20i

Receiver 20.96 MHz Clock (Input Type 2). Extracted clock from the receive data
stream. Divided internally by 5 and phase corrected to frame synch pattern to produce
internal 2.048 MHz data clock for parsing the receive STi streams.

No Internal Connection.

Power Supply Ground. Nominally 0 volts.

No Internal Connection.

Positive Power Supply. Nominally 5 volts.

No Internal Connection.

RxDATA

Receive 4B/5B, NRZI Encoded Serial Data (Input Type 1).

RLED

"Remote Sync" LED Driver (Open Collector, Output Type 3). Drives the "Remote
Sync" LED on/off at approximately a 4 Hz rate when the remote interface is not syn-
chronized. Active only when the local interface is synchronized.

FBOE

Frame Buffer Ram Enable (Output Type 2). Generates a low going strobe during
valid RAM read access.

Pin Description

Pin #

Name

Description

MT90710

Preliminary Information

5-6

MODE2

Operating Mode Select 2 (Input Type 1). See Table 1.

MODE1

Operating Mode Select 1 (Input Type 1). See Table 1.

MODE0

Operating Mode Select 0 (Input Type 1). See Table 1.

STo0

Serial, 32 Channel, 2.048 Mb/s link 0 (Output Type 3). Output is active only when
receiver detects the synchronization pattern on RxDATA input stream; output is high
impedance during loss of synchronization.

Positive Power Supply. Nominally 5 volts.

Power Supply Ground. Nominally 0 volts.

STo2

Serial, 32 Channel, 2.048 Mb/s link 2 (Output Type 3). Output active only when
receiver detects the synchronization pattern on RxDATA input stream; high impedance
output during loss of synchronization.

STo3

Serial, 32 Channel, 2.048 Mb/s link 3 (Output Type 3). Output active only when
receiver detects the synchronization pattern on RxDATA input stream; high impedance
output during loss of synchronization.

STo4

Serial, 32 Channel, 2.048 Mb/s link 4 (Output Type 3). Output active only when
receiver detects the synchronization pattern on RxDATA input stream; high impedance
output during loss of synchronization.

FBWE

Frame Buffer RAM Write Enable (Output Type 2). Generates a low going strobe dur-
ing valid RAM write access.

STo1

Serial, 32 Channel, 2.048 Mb/s link 1 (Output Type 3). Output active only when
receiver detects the synchronization pattern on RxDATA input stream; high impedance
output during loss of synchronization.

F0b

System 8 kHz Reference Frame Pulse (Bi-directional; Input and Output Types 3).
When in controller mode this is an input accepting the system reference pulse. In
peripheral mode this is an output supplying the system an 8 kHz reference frame pulse.

DOUT32K

Asynchronous 32 kHz Signal 1 (Open Collector, Output Type 3). Sourced from the
far-end DIN32K input.

TxDATA

Transmit 4B/5B, NRZI Encoded Serial Data (Output Type 3).

Power Supply Ground. Nominally 0 volts.

Internally Connected (Output Type 1). Drives continuous logic 1. Leave open circuit.

Positive Power Supply. Nominally 5 volts.

POR

Power On Reset (Input Type 2). Active low.

FBDATA7

Frame Buffer Data Bit 7 (Bidirectional; Input Type 1 and Output Type 2). Data bit 7.

C4b

4.096 MHz Reference Clock (Bidirectional; Input and Output Types 3). Input used
by PLL in controller mode and derived from the system. In peripheral mode this is an
output supplying the system 4.096 MHz reference clock.

FBDATA6

Frame Buffer Data Bit 6 (Bidirectional; Input Type 1 and Output Type 2). Data bit 6.

FBDATA5

Frame Buffer Data Bit 5 (Bidirectional; Input Type 1 and Output Type 2). Data bit 5.

DIN8K0

Asynchronous 8 kHz Signal 0 (Input Type 1). Transmitted to the far-end DOUT8K0
output.

FBDATA4

Frame Buffer Data Bit 4 (Bidirectional; Input Type 1 and Output Type 2). Data bit 4.

Pin Description

Pin #

Name

Description

Preliminary Information

MT90710

5-7

Notes:

All unused inputs should be connected to logic high or low unless otherwise stated. All outputs should be left open circuit when not used.

All output types are CMOS with CMOS logic levels (see DC Electrical Characteristics for Type drive capability).

Input Type 1 has TTL compatible logic levels, Type 2 has CMOS compatible logic levels and Type 3 has TTL Schmitt trigger compatible
logic levels (see DC Electrical Characteristics).

DIN32K

Asynchronous 32 kHz Signal (Input Type 1). Transmitted to the far-end DOUT32K
output.

Positive Power Supply. Nominally 5 volts.

Power Supply Ground. Nominally 0 volts.

FBDATA3

Frame Buffer Data Bit 3 (Bidirectional; Input Type 1 and Output Type 2). Data bit 3.

STi0

Serial, 32 Channel, 2.048 Mb/s Link 0 (Input Type 1).

FBDATA2

Frame Buffer Data Bit 2 (Bidirectional; Input Type 1 and Output Type 2). Data bit 2.

DIN8K1

Asynchronous 8 kHz Signal 1 (Input Type 1). Transmitted to the far-end DOUT8K1
output.

FBDATA1

Frame Buffer Data Bit 1 (Bidirectional; Input Type 1 and Output Type 2). Data bit 1.

LLED

"Local Sync" LED Driver (Open Collector, Output Type 2). Drives the "Local Sync"
LED on/off at approximately a 4 Hz rate when the local interface is not in
synchronization.

FBDATA0

Frame Buffer Data Bit 0 (Bidirectional; Input Type 1 and Output Type 2). Data bit 0.

RESET

Reset Control (Input Type 1).

Internally Connected.

Positive Power Supply. Nominally 5 volts.

No Internal Connection.

Power Supply Ground. Nominally 0 volts.

FBADDR0

Frame Buffer RAM Address Bit 0 (Output Type 2).

FBADDR1

Frame Buffer RAM Address Bit 1 (Output Type 2).

FBADDR2

Frame Buffer RAM Address Bit 2 (Output Type 2).

FBADDR3

Frame Buffer RAM Address Bit 3 (Output Type 2).

FBADDR4

Frame Buffer RAM Address Bit 4 (Output Type 2).

FBADDR5

Frame Buffer RAM Address Bit 5 (Output Type 2).

FBADDR6

Frame Buffer RAM Address Bit 6 (Output Type 2).

STo6B

Serial, 32 Channel, 2.048 Mb/s Link 6B (Output Type 3). Output active only when
receiver detects the synchronization pattern on RxDATA input stream; high impedance
output during loss of synchronization.

Pin Description

Pin #

Name

Description

Overview

The MT90710 multiplexes multiple Serial Telecom
(ST-BUS timing, Figure 7) links onto a single 20 MHz
loop to facilitate point-to-point data transport
requirements. The MT90710 connects easily with
standard Fiber Optic interfaces to form a complete
electric to photonic conversion circuit. Optical

transmission allows large bandwidth inter-shelf or, in
distributed systems, inter-node communication by
eliminating multiple data busses, cable inter-connect
and the attendant driver interfaces. The final result is
a simple physical interface free of the radiated
emissions and background noise susceptibility
problems encountered in copper-wired
environments.

MT90710

Preliminary Information

5-8

The MT90710 provides 15.808 Mb/s clear channel,
user bandwidth in both transmit and receive
directions. In addition, two 8 kHz sampled signals
and one 32 kHz sampled signal are encoded and
transported over the loop as additional user
bandwidth. These asynchronous signals, in
combination with overhead information and clear
channel bandwidth produce an aggregate data rate
of 16.384 Mb/s. After encoding (4B/5B) the final
transmitted baud rate is 20.48 Mbaud.

Transmit

The transmit data interface consists of nine ST-BUS
input links and three asynchronously sampled input
signals. These are STi0 - STi5, STi6A and STi6B,
STi7, DIN8K0, DIN8K1 and DIN32K. Six ST-BUS
input links, STi0-5, each provide 2.048 Mb/s
transparent transmission bandwidth. With ST6MUX
Mode disabled STi6A is also a 2.048 Mb/s link while
STi6B is not used (see ST6MUX description). The
first nine channels of the STi7 input are ignored
leaving the remaining 23 channels for user
bandwidth. This allows a total of 15.808 Mb/s clear
bandwidth for application use. The first nine (576
kb/s) channels of STi7 are made available for
transmitting the three asynchronous signals
combined with fiber overhead information. This
overhead is automatically compiled in the transmit
interface and inserted into these timeslots for
transmission over the fiber interface.

Overhead information includes a frame
synchronization byte, an error count and a checksum
calculated on the previous frame of transmitted data.

Once compiled, the contents of the transmit data
bandwidth is first 4B/5B encoded, then NRZI
encoded before it is applied to the transmit fiber
interface driver via TxDATA. 4B/5B ensures that the
NRZI encoded data will contain a minimum of two
transitions per baud. This is sufficient to allow the far
end to extract the embedded clock information. As a
result of 4B/5B encoding the information bandwidth
of 16.384 Mb/s increases to a total baud rate of
20.48 MBaud/s at the fiber interface.

Incoming ST-BUS link data is latched at the mid-bit
position of the internal timeslot. Since there is a
phase difference between the internal and external
timeslots, due to the operation of the PLL, latching
occurs at approximately the 3/4 bit position of the
external timeslot when in Controller mode. In
Peripheral mode data is latched at the midpoint of
the timeslot. Asynchronous signals DIN8K0-1 are
sampled once per frame (8,000 times per second)
and are intended to convey relatively static
information where a state transition is not time
critical enough that a resolution of one frame is
detrimental. Asynchronous signal DIN32K is
sampled four times per frame (32,000 times per
second) and may be used to transport data at a
higher rate than the other two asynchronous inputs.
As an example, this sampling rate is sufficient to
support 19.2K Baud RS-232 signals (TTL levels) so
that remote programming or loop maintenance may
be performed.

255 0 1 2 3 4 5 6 7 8 9 .......... 246 247 248 249 250 251 252 2

Fiber Timeslot

Channel Assignment

Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

4B/5B Encoded Data Bit Assignment

Frame Pulse

ST6 Ch0 ST5 Ch0 ST4 Ch0 ST3 Ch0 ST2 Ch0 ST1 Ch0 ST0 Ch0 ST6 Ch1

ST7 Ch0

ST7 Ch1

Figure 3 - Fiber Timeslot Assignment

Preliminary Information

MT90710

5-9

Receive

The 4B/5B and NRZI encoded data from the receive
fiber interface is NRZI decoded and the frame
synchronization information is extracted. After 4B/5B
decoding the remaining data is frame aligned either
to the system frame pulse (when in Controller Mode)
or to the extracted frame pulse (when in Peripheral
Mode). After alignment, the received data package is
disassembled into the clear channel ST-BUS
streams, the asynchronous signals and the
overhead/status information. When ST6MUX mode
is disabled, received 15.808 Mb/s bandwidth is made
available on STo0-STo6A and the last 23 channels of
STo7. The asynchronous signals are presented on
DOUT8K0, DOUT8K1 and DOUT32K while the
received overhead information, as well as local
status information, is presented on ST07 in channels
0 to 7.

Control

An external, 40.96 MHz PLL provides the master
clock (C40i) for the MT90710. This PLL uses either
the system's C4b clock (pin 57) for reference when
it's in controller mode or the extracted clock from the

receive data interface when it's in peripheral mode.
Switching between these two primary references is
automatic and under the control of the MODE0-2
pins. The selected reference is fed to the external
PLL from the C4REFo output pin. The MT90710 also
divides the 40.96 MHz master clock by ten and
supplies this secondary reference to the external
PLL on C4o for comparison to the primary reference.
The PLL creates a 40.96 MHz master clock from a
4.096 MHz reference by multiplying by 10 and
attenuates jitter present on the extracted reference.

The master clock is divided down to create internal
clocks, external ST-BUS clocks (when in peripheral
mode) and timeslot counters.

Control signals are also created for the transmitter
and receiver. The transmitter timeslot counter is
synchronized to the backplane frame pulse while the
receiver timeslot counter is sync to the extracted
synchronization pulse.

Frame Buffer

To re-align the received data from the fiber interface
to the system, or node, a frame reference buffer is

C4o

(Pin 13)

ST-BUS input data latched here

122 ns

48.8ns

ADDR

RD ADDR

WR ADDR

RD ADDR

FBDATA

FBADDR

FBWE

FBOE

C20o

(Pin 6)

170.8ns

Bit Cell

Figure 4 - Frame Buffer Memory Typical Timing

MT90710

Preliminary Information

5-10

required. This is implemented using an external 8x8
static RAM (35 ns). Only 256 bytes are used of the
8K total. RAM address and data (FBADDR0-7 and
FBDATA0-7) signals are generated along with an
output enable strobe (FBOE) and a write enable
strobe (FBWE).

Table 1 - Operational Mode Select

Overhead Information

Fiber Interface

Eight of the 256 fiber channels are reserved for
overhead information. These are fiber channels:

Channel #

Function

Frame Alignment

Asynchronous signal transfer and
synchronization detect

Checksum of previous frame

Reserved

Remote error count most significant byte

Remote error count least significant byte

Mode # Mode 2 Mode 1 Mode 0

ST6MUX

Configuration

ENABLED

CONTROLLER

ENABLED

PERIPHERAL

not used

DISABLED CONTROLLER

not used

DISABLED

PERIPHERAL

ST-BUS Interface

The first nine STo7 channels are reserved for
overhead information:

STo7 Channel

Function

not available

Reserved

Local error count

(most significant byte)

Local error count

(least significant byte)

Reserved

Remote error count

(most significant byte)

Remote error count

(least significant byte)

synchronization detect

(see STo7 channel 8 definition)

STo7 Channel 8 Definition:

remote receiver is in frame synch
when logic 1

Local receiver is in frame synch
when logic 1

B5, B4, B3

Reserved

B2, B1, B0

Reserved

ST6MUX

ST-BUS to Fiber

When ST6MUX is enabled the STi6A and STi6B
input streams are alternately multiplexed onto the
fiber link. (i.e., only half of the bandwidth of each link
is utilized). The transmit pattern at the fiber interface
is:

STi6A-Chan0,STi6B-Chan1,STi6A-Chan2,STi6B-Chan3,...,

STi6B-Chan29,STi6A-Chan30,STi6B-Chan31

Multiplexed Stream

Chan 0

Chan 1

Chan 2

Chan 3

Chan 4

Chan 5

.....

Chan 28

Chan 29

Chan 30

Chan 31

STo6A Data from STi6A

Chan 0

Chan 2

Chan 4

.....

Chan 28

Chan 30

STo6B Data from STi6B

Chan 1

Chan 3

Chan 5

.....

Chan 29

Chan 31

Table 2 - ST6MUX Channel Assignment

Preliminary Information

MT90710

5-11

Fiber to ST-BUS

When ST6MUX is enabled the STo6A and STo6B
output streams are comprised of the demultiplexed
information received from the fiber link. The received
data is duplicated on two channels since the ST-BUS
channels support twice the bandwidth of the data
from the incoming fiber link. See Table 2.

When ST6MUX is disabled the STi6B and STo6B
ports are not operational. The STi6A and STo6A
ports operate as clear 2.048 MHz links in the same
manner as STi/o links 0 to 5.

Fiber Loop Synchronization

A receiver is declared in synchronization after
detection of three consecutive frames containing a
valid sync pattern. Once synchronized a receiver will
lose sync if a valid sync pattern is not detected in two
of four consecutive frames (refer to Figure 5).

LED Control

The open collector RLED output (pin 36) will cause
an LED, pulled up to +5 volts, to flash at

approximately a 4 Hz rate when the far-end is out of
synchronization but the near-end is synchronized. If
the near-end is not synchronized this output is
inactive.

The open collector LLED output (pin 70) will cause
an LED, pulled up to +5 volts, to flash at
approximately a 4 Hz rate when the near-end is out
of synchronization.

Checksum Generator

Checksum =

Where i-1 is the carry out from the previous
operation. The checksum is calculated on all 255
channels except on channel 0 where the frame
synchronization code is transported. During this
channel the previous checksum is stored and the
register initialized for the next calculation.

DATAi Ci 1

255

INCORRECT SYNC

SET SYNC = FALSE

CORRECT SYNC
SET SYNC = FALSE

CORRECT SYNC
SET SYNC = LAST STATE

INCORRECT SYNC

SET SYNC = LAST STATE

CORRECT SYNC

SET SYNC = TRUE

CORRECT SYNC
SET SYNC = TRUE

INCORRECT SYNC
SET SYNC = TRUE

INCORRECT SYNC

SET SYNC = FALSE

STATE 0

STATE 1

STATE 2

STATE 3

Figure 5 - State Diagram

MT90710

Preliminary Information

5-12

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Preliminary Information

MT90710

5-13

Exceeding these figures may cause permanent damage. Functional operation under these conditions is not guaranteed.

Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

Absolute Maximum Ratings*

Parameter

Symbol

Min

Max

Units

DC Supply Voltage

- 0.3

Input Voltage

- 0.3

+ 0.3

DC Input Current

+/- 50

Storage Temperature

stg

- 65

+ 150

Recommended Operating Conditions

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Input

Voltage

4.5

5.5

Operating Temperature

+70

DC Electrical Characteristics

- Voltages are with respect to ground (V

) unless otherwise stated.

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Supply Current operating

230

276

Input HIGH voltage (TTL)

IHT

2.0

Input Type 1

Input LOW voltage (TTL)

ILT

0.8

Input Type 1

Input HIGH voltage (CMOS)

IHC

0.7V

Input Type 2

Input LOW voltage (CMOS)

ILC

0.3V

Input Type 2

Positive threshold (schmitt)

2.0

Input Type 3

Negative threshold (schmitt)

0.8

Input Type 3

Hysteresis

0.5

Input Type 3

Input leakage current

150

=5.5V,

to V

High level output voltage

3.7

All output types @ max I

Low level output voltage

0.4

All output types @ max I

Output Current

O12

1
4

mA
mA
mA

Output Type 1
Output Type 2
Output Type 3

High impedance leakage

=5.5V,

to V

Output capacitance

Input capacitance

MT90710

Preliminary Information

5-14

Timing is over recommended temperature & power supply voltages (V

=5V±10%, V

=0V, T

=0 to 70°C).

Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

Figure 7 - ST-BUS Timing

AC Electrical Characteristics

- ST-BUS Timing

Voltages are with respect to ground (V

) unless otherwise stated.

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Frame Pulse width

F0iW

244

Frame Pulse setup time

F0iS

190

Frame Pulse hold time

F0iH

190

STo delay Active to Active

DAA

100

=150 pF

STi setup time

STiS

STi hold time

STiH

Clock period

C4i

200

244

300

CK Input Low

122

150

CK Input High

122

150

10 Clock Rise/Fall Time

2.0V

0.8V

STi

2.0V

0.8V

2.0V

0.8V

STo

2.0V

0.8V

F0i

F0iW

C4i

F0iS

DAA

STiS

STiH

F0iH

Ch. 31
Bit 0

Ch. 0
Bit 7

Ch. 0
Bit 6

Ch. 31
Bit 0

Ch. 0
Bit 7

Ch. 0
Bit 6

Ch. 0
Bit 5

C4i

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