8-17
Description
The MT9122 Voice Echo Canceller implements a
cost effective solution for telephony voice-band echo
cancellation conforming to ITU-T G.165
requirements. The MT9122 architecture contains two
echo cancellers which can be configured to provide
dual channel 64 millisecond echo cancellation or
single channel 128 millisecond echo cancellation.
The MT9122 supports ITU-T G.165 or G.164 tone
disable requirements.
The MT9122 operates in two major modes:
Controller or Controllerless. Controller mode allows
access to an array of features for customizing the
MT9122 operation. Controllerless mode is for
applications where default register settings are
sufficient.
Features
Dual channel 64ms or single channel 128ms
echo cancellation
Conforms to ITU-T G.165 requirements
ITU-T G.165/G.164 disable tone detection
supported on all audio paths
Narrow-band signal detection
Programmable double-talk detection threshold
Non-linear processor with adaptive suppression
threshold and comfort noise insertion
Offset nulling of all PCM channels
Controllerless mode or Controller mode with
serial interface
ST-BUS or variable-rate SSI PCM interfaces
Selectable
/A-Law ITU-T G.711;
/A-Law Sign
Mag; linear 2's complement
Per channel selectable 12 dB attenuator
Transparent data transfer and mute option
19.2 MHz master clock operation
Applications
Wireless Telephony
Trunk echo cancellers
Figure 1 - Functional Block Diagram
Linear/
/A-Law
+
Non-Linear
Processor
Offset
Null
Linear/
/A-Law
Linear/
/A-Law
Microprocessor
Interface
Double-Talk
Detector
Disable Tone
Detector
Adaptive
Filter
Control
Narrow-Band
Detector
Linear/
/A-Law
Offset
Null
12dB
Attenuator
Echo Canceller A
Echo Canceller B
VDD
VSS
PWRDN
IC
F0od
F0i
BCLK/C4i
MCLK
Sout
Rin
ENA1
ENB1
CONFIG1
CONFIG2
S1/DATA1
S2/DATA2
S3/CS
S4/SCLK
Sin
Rout
ENA2
ENB2
NLP
REV
LAW
FORMAT
TD1
TD2
-
Programmable
Bypass
Disable Tone
Detector
ISSUE 5
September 1996
Ordering Information
MT9122AP
28 Pin PLCC
MT9122AE
28 Pin PDIP
-40
C to + 85
C
MT9122
Dual Voice Echo Canceller
with Tone Detection
CMOS
Preliminary Information
MT9122
Preliminary Information
8-18
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
1
ENA1
SSI Enable Strobe / ST-BUS Mode for Rin/Sout (Input). This pin has dual functions
depending on whether SSI or ST-BUS is selected.
For SSI, this strobe must be present for frame synchronization. This is an active high channel
enable strobe, 8 or 16 data bits wide, enabling serial PCM data transfer for Echo Canceller A
on Rin/Sout pins. Strobe period is 125 microseconds.
For ST-BUS, this pin, in conjunction with the ENB1 pin, will select the proper ST-BUS mode for
Rin/Sout pins (see ST-BUS Operation description). The selected mode applies to both Echo
Canceller A and B.
2
ENB1
SSI Enable Strobe / ST-BUS Mode for Rin/Sout (Input).This pin has dual functions
depending on whether SSI or ST-BUS is selected.
For SSI, this is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial
PCM data transfer for Echo Canceller B on Rin/Sout pins. Strobe period is 125 microseconds.
For ST-BUS, this pin, in conjunction with the ENA1 pin, will select the proper ST-BUS mode for
Rin/Sout pins (see ST-BUS Operation description). The selected mode applies to both Echo
Canceller A and B.
3
ENA2
SSI Enable Strobe / ST-BUS Mode for Sin/Rout (Input).This pin has dual functions
depending on whether SSI or ST-BUS is selected.
For SSI, this is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial
PCM data transfer for Echo Canceller A on Sin/Rout pins. Strobe period is 125 microseconds.
For ST-BUS, this pin, in conjunction with the ENB2 pin, will select the proper ST-BUS mode for
Sin/Rout pins (see ST-BUS Operation description). The selected mode applies to both Echo
Canceller A and B.
4
ENB2
SSI Enable Strobe / ST-BUS Mode for Sin/Rout (Input).This pin has dual functions
depending on whether SSI or ST-BUS is selected.
For SSI, this is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial
PCM data transfer for Echo Canceller B on Sin/Rout pins. Strobe period is 125 microseconds.
For ST-BUS, this pin, in conjunction with the ENA2 pin, will select the proper ST-BUS mode for
Sin/Rout pins (see ST-BUS Operation description). The selected mode applies to both Echo
Canceller A and B.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
28
27
26
25
24
23
22
21
S2/DATA2
VDD
F0od
IC
TD1
S1/DATA1
S4/SCLK
Sout
Rout
BCLK/C4i
CONFIG1
CONFIG2
Sin
Rin
NLP
VSS
ENB2
ENB1
F0i
FORMAT
REV
LAW
ENA1
PWRDN
TD2
ENA2
MCLK
S3/CS
ENB2
ENB1
ENA1
ENA2
BCLK/
C4i
CONFIG1
CONFIG2
IC
Sin
Rin
NLP
VSS
REV
MCLK
FORMA
T
LA
W
PWRDN
TD2
TD1
S4/SCLK
S3/
CS
S2/DATA2
VDD
F0od
S1/DATA1
Sout
Rout
F0i
PLCC
4
5
6
7
8
9
10
11
25
24
23
22
21
20
19
3
2
1
28
27
26
12
13
14
15
16
17
18
PDIP
Preliminary Information
MT9122
8-19
5
Rin
Receive PCM Signal Input (Input). 128 kbit/s to 4096 kbit/s serial PCM input stream. Data
may be in either companded or 2's complement linear format. Two PCM channels are time-
multiplexed on this pin. These are the Receive Input reference channels for Echo Cancellers
A and B. Data bits are clocked in following SSI or ST-BUS timing requirements.
6
Sin
Send PCM Signal Input (Input). 128 kbit/s to 4096 kbit/s serial PCM input stream. Data
may be in either companded or 2's complement linear format. Two PCM channels are time-
multiplexed on this pin. These are the Send Input channels (after echo path) for Echo
Cancellers A and B. Data bits are clocked in following SSI or ST-BUS timing requirements.
7
VSS
Digital Ground: Nominally 0 volts.
8
MCLK
Master Clock (Input): Nominal 20 MHz Master Clock input. May be connected to an
asynchronous (relative to frame signal) clock source.
9
IC
Internal Connection (Input): Must be tied to Vss.
10
NLP
Non-Linear Processor Control (Input):
Controllerless Mode: An active high enables the Non-Linear Processors in Echo Cancellers A
and B. Both NLP's are disabled when low. Intended for conformance testing to G.165 and it is
usually tied to Vdd for normal operation.
Controller Mode: This pin is ignored (tie to Vdd or Vss). The non-linear processor operation is
controlled by the NLPDis bit in Control Register 2. Refer to the Register Summary.
11
REV
Reversal Detection (Input):
Controllerless Mode: An active high configures all the tone detectors to trigger only when a
2100Hz disable tone with periodic phase reversal is present (per G.165). When low, the tone
detectors will trigger upon detection of any 2100Hz disable tone, with or without periodic
phase reversal (per G.164).
Controller Mode: This pin is ignored (tie to VDD or VSS). The operation is controlled by the
PHDis bit in Control Register 2. Refer to the Register Summary.
12
LAW
A/
Law Select (Input):
An active low selects
-
Law companded PCM. When high, selects A-Law companded PCM.
This control is for both echo cancellers and is valid for both controller and controllerless
modes.
13
FORMAT ITU-T/Sign Mag (Input):
An active low selects sign-magnitude PCM code. When high, selects ITU-T (G.711) PCM
code. This control is for both echo cancellers and is valid for both controller and controllerless
modes.
14
PWRDN
Power-down (Input): An active low resets the device and puts the MT9122 into a low-power
stand-by mode.
15
TD2
Tone Detect 2 (Output):
An active low output occurs when Echo Canceller B detects the presence of a valid 2100Hz
disabling tone (G.164 or G.165) on Rin or Sin pins. This output returns to a logic high once the
release criteria are met. The behavior of this pin is identical in both controller and
controllerless modes.
16
TD1
Tone Detect 1 (Output):
An active low output occurs when Echo Canceller A detects the presence of a valid 2100Hz
disabling tone (G.164 or G.165) on Rin or Sin pins. This output returns to a logic high once the
release criteria are met. The behavior of this pin is identical in both controller and
controllerless modes.
Pin Description (continued)
Pin #
Name
Description
MT9122
Preliminary Information
8-20
Notes:
1. All unused inputs should be connected to logic low or high unless otherwise stated. All outputs should be left open circuit when not used.
2. All inputs have TTL compatible logic levels except for MCLK, Sin and Rin pins which have CMOS compatible logic levels and PWRDN
pin which has Schmitt trigger compatible logic levels.
3. All outputs are CMOS pins with CMOS logic levels.
17/18
17
18
S4/S3
SCLK
CS
Selection of Echo Canceller B Functional States (Input):
Controllerless Mode: Selects Echo Canceller B functional states according to Table 2.
Controller Mode: S4 and S3 pins become SCLK and CS pins respectively.
Serial Port Synchronous Clock (Input): Data clock for the serial microport interface.
Chip Select (Input): Enables serial microport interface data transfers. Active low.
19/20
19
20
S2/S1
DATA2
DATA1
Selection of Echo Canceller A Functional States (Input):
Controllerless Mode: Selects Echo Canceller A functional states according to Table 2.
Controller Mode: S2 and S1 pins become DATA2 and DATA1 pins respectively.
Serial Data Receive (Input):
In Motorola/National serial microport operation, the DATA2 pin is used for receiving data. In
Intel serial microport operation, the DATA2 pin is not used and must be tied to Vss or Vdd.
Serial Data Port (Bidirectional):
In Motorola/National serial microport operation, the DATA1 pin is used for transmitting data. In
Intel serial microport operation, the DATA1 pin is used for transmitting and receiving data.
21
F0od
Delayed Frame Pulse Output (Output):
In ST-BUS operation, this pin generates a delayed frame pulse after the 4th channel time slot
and is used for daisy-chaining multiple ST-BUS devices. See Figures 5 to 8.
In SSI operation, this pin outputs logic low.
22
VDD
Positive Power Supply: Nominally 5 volts.
23
Sout
Send PCM Signal Output (Output):
128 kbit/s to 4096 kbit/s serial PCM output stream. Data may be in either companded or 2's
complement linear PCM format. Two PCM channels are time-multiplexed on this pin. These
are the Send Out signals after echo cancellation and Non-linear processing. Data bits are
clocked out following SSI or ST-BUS timing requirements.
24
Rout
Receive PCM Signal Output (Output):
128 kbit/s to 4096 kbit/s serial PCM output stream. Data may be in either companded or 2's
complement linear PCM format. Two PCM channels are time-multiplexed on this pin. This
output pin is provided for convenience in some applications and may not always be required.
Data bits are clocked out following SSI or ST-BUS timing requirements.
25
F0i
Frame Pulse (input):
In ST-BUS operation, this is a frame alignment low going pulse. SSI operation is enabled by
connecting this pin to Vss.
26
BCLK/C4i Bit Clock/ST-BUS Clock (Input):
In SSI operation, BCLK pin is a 128 kHz to 4.096 MHz bit clock. This clock must be
synchronous with ENA1, ENA2, ENB1 and ENB2 enable strobes.
In ST-BUS operation, C4i pin must be connected to the 4.096MHz (C4) system clock.
27/28 CONFIG1/
CONFIG2
Device Configuration Pins (Inputs).
When CONFIG1 and CONFIG2 pins are both logic 0, the MT9122 serial microport is enabled.
This configuration is defined as Controller Mode. When CONFIG1 and CONFIG2 pins are in
any other logic combination, the MT9122 is configured in Controllerless Mode. See Table 3.
Pin Description (continued)
Pin #
Name
Description
Preliminary Information
MT9122
8-21
Functional Description
The MT9122 architecture contains two individually
controlled echo cancellers (Echo Canceller A and B).
They can be set in three distinct configurations:
Normal, Back-to-Back and Extended Delay (see
Figure 3). Under Normal configuration, the two echo
cancellers are positioned in parallel providing 64
millisecond echo cancellation in two channels
simultaneously. In Back-to-Back configuration, the
two echo cancellers are positioned to cancel echo
coming from both directions in a single channel. In
Extended-Delay configuration, the two echo
cancellers are internally cascaded into one 128
millisecond echo canceller.
Each echo canceller contains the following main
elements (see Figure 1).
Adaptive Filter for estimating the echo channel
Subtracter for cancelling the echo
Double-Talk detector for disabling the filter
adaptation during periods of double-talk
Non-Linear Processor for suppression of
residual echo
Disable Tone Detectors for detecting valid
disable tones at the input of receive and send
paths
Narrow-Band Detector for preventing Adaptive
Filter divergence caused by narrow-band
signals
Offset Null filters for removing the DC
component in PCM channels
12dB attenuator for signal attenuation
Serial controller interface compatible with
Motorola, National and Intel microcontrollers
PCM encoder/decoder compatible with
/A-
Law ITU-T G.711,
/A-Law Sign-Mag or linear
2's complement coding
The MT9122 has two modes of operation:
Controllerless and Controller. Controllerless mode is
intended for applications where customization is not
required. Controller mode allows access to all
registers for customizing the MT9122 operation.
Refer to Table 7 for a complete list. Controller mode
is selected when CONFIG1 and CONFIG2 pins are
both connected to Vss.
Each echo canceller in the MT9122 has four
functional states:
Mute, Bypass, Disable Adaptation
and
Enable Adaptation. These are explained in the
section entitled Echo Canceller Functional States.
Figure 3 - Device Configuration
Rin
Rout
Sout
Sin
echo
path A
Optional -12dB pad
PORT 2
PORT 1
echo
path B
+
-
channel A
channel A
+
-
channel B
channel B
E.C.A
E.C.B
a) Normal Configuration (64ms)
+
-
channel A
channel A
E.C.A
Sin
Sout
Rout
Rin
b) Extended Delay Configuration (128ms)
PORT 2
PORT 1
+
E.C.A
Sin
Sout
Rout
Rin
c) Back-to-Back Configuration (64ms)
-
E.C.B
+
-
echo
echo
path
path
PORT 2
PORT 1
echo
path A
Adaptive
Filter (64ms)
Adaptive
Filter (64ms)
Optional -12dB pad
Adaptive
Filter (64ms)
Optional -12dB pad
Adaptive
Filter (64ms)
Optional -12dB pad
Adaptive Filter
(128 ms)
Optional -12dB pad
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