PDSP16488A MA

FEATURES

Pixel

3x3

5x5

7x7

9x9

11x11 15x15 23x23

Size

10MHz

20MHz

40MHz

Max Pixel

Rate

Window size

* Maximum rate is limited to 30 MHz by line store expansion delays

Table 2 Devices needed to implement typical window sizes

Table 1 Single Device Configurations

40MHz
20MHz
10MHz
20MHz
10MHz

8
8
8

16
16

4
8
8
4
8

4
4
8
4
4

4x1024
4x1024
8x512
4x512
4x512

Data
Size

Window Size

Width X Depth

Max Pixel

Rate

Line
Delays

The PDSP16488A is a fully integrated, application spe-

cific, image processing device. It performs a two dimensional
convolution between the pixels within a video window and a
set of stored coefficients. An internal multiplier accumulator
array can be multi-cycled at double or quadruple the pixel
clock rate. This then gives the window size options listed in
Table 1.

An internal 32k bit RAM can be configured to provide

either four or eight line delays. The length of each delay can
be programmed to the users requirement, up to a maximum of
1024 pixels per line. The line delays are arranged in two
groups,which may be internally connected in series or may be
configured to accept separate pixel inputs. This allows inter-
laced video or frame to frame operations to be supported.

The 8 bit coefficients are also stored internally and can

be downloaded from a host computer or from an EPROM. No
additional logic is required to support the EPROM and a single
device can support up to 16 convolvers.

The PDSP16488A contains an expansion adder and

delay network which allows several devices to be cascaded.
Convolvers with larger windows can then be fabricated as
shown in Table 2.

Intermediate 32 bit precision is provided to avoid any

danger of overflow, but the final result will not normally occupy
all bits. The PDSP16488A thus provides a multiplier in the
output path, which allows the user to align the result to the
most significant end of the 32 bit word.

Fig. 1 Typical , Stand Alone, Real Time System

DELAYED

SYNC

PIXEL

CLOCK

GENERATOR

SYNC

EXTRACT

ADDR DATA

CLK

SYNC

BYPASS

AUX
DATA

EPROM

OUTPUT

DATA

POWER ON

RESET

RES

A/D

CONVERTER

OPTIONAL

FIELD

STORE

COMPOSITE

DATA
IN

PDSP

16488A

CONVOLVER

The PDSP16488A is a fully compatible replacement
for the PDSP16488

8 or 16 bit pixels with rates up to 40 MHz

Window sizes up to 8 x 8 with a single device

Eight internal line delays

Supports interlace and frame to frame operations

Coefficients supplied from an EPROM or remote host

Expandable in both X and Y for larger windows

Gain control and pixel output manipulation

132 pin QFP

Rev

C D

Date

MAR 1993 JUL 1996 JAN1997

NOTE

Polyimide is used as an inter-layer dielectric and as
glassivation.

Polymeric material is also used for die attach which according
to the requirement in paragraph 1.2.1.b. (2) precludes
catagorising this device as fully compliant. In every other
respect this device has been manufactured and screened in full
accordance with the requirements of Mil-Std 883 (latest revi-
sion).

CHANGE NOTIFICATION

The change notification requirements of MIL-PRF-38535 will
be implemented on this device type. Known customers will be
notified of any changes since the last buy when ordering further
parts if significant changes have been made.

PDSP16488A MA

Single Chip 2D Convolver with Integral Line Delays

Supersedes January 1997 version, DS3742 - 3.1

DS3742 - 4.0 January 2000

PDSP16488A MA

TYPE

INPUT

I/O

INPUT

DUAL
FUNCTION

OUTPUT

INPUT

OUTPUT

I/O

INPUT

I/O

INPUT

OUTPUT

INPUT

OUTPUTS

SUPPLY

DESCRIPTION

Pixel data input to the first line delay. [most significant byte in 16 bit mode]

Pixel data input to the second group of line delays. [least significant byte in 16bit mode]. Alternatively
an output from the last line delay when the appropriate mode bit is set.

The first line delay in the first group is bypassed when this input is active. (High). No internal pull up.

Resets the line delay address pointers when high. Normally the composite sync signal in real time
applications. In non real time systems it defines a frame store update period, when low.

Address/data connections from a MASTER or SINGLE device to the external coefficient source, with
X15 defining EPROM or Host support. Otherwise they provide the expansion data input.

Signed 16 bit scaled data or multiplexed 32 bit intermediate data. During intermediate transfers the
most significant half is valid when the clock is low, and the least significant half when clock is high.

During programming a MASTER device outputs a timing strobe on this pin. This is passed down the
chain in a multiple device system, using the

PC0 input on the next device.

This pin is used in conjunction with

PC1 in multiple device systems. It terminates the write strobe from

a MASTER device which is EPROM supported.

This output provides a version of the HRES input which has been delayed by an amount defined by
the user.

The data strobe from a host computer. Active low. This pin will be an output from an EPROM supported
MASTER device which provides strobes to the remaining devices.

An active low enable which is internally gated with R/

W and DS to perform reads or writes to the

internal registers. In a SINGLE or MASTER device, which is supported from an EPROM, the bottom
72 addresses are always used and CE is not needed.

CE can then be used to initiate a new register

load sequence after the power on load sequence.

Read / not write line from the host CPU. When an EPROM is used this pin should be tied low.

This pin is normally an input which signifies that registers are to be changed or examined. It is,
however, an output from an EPROM supported SINGLE or MASTER device indicating to the rest of
the system that registers are being updated.

Clock. All events are triggered on the rising edge of the clock, except the latching of least significant
expansion inputs . Internally the clock can be multiplied by two or four in order to increase the effective
number of multipliers.

This output indicates the result from the internal comparison. A high value indicates that the pixel
was greater than the internal threshold. The output is only valid from the last device in a chain.

When high this output indicates that there has been a gain control overflow.

Active low power on reset signal.

Tied to ground to indicate a SINGLE device system. Internal pull up resistor.

Tied to ground to indicate the MASTER device in a multiple device system. Must be left open circuit
in a SINGLE device system. Internal pull up.

Output enable signal. Active low.

Four address bits from a MASTER specifying one of sixteen devices in a multiple device system. Must
be externally decoded to provide chip enables for the additional devices.

These bits indicate the field selection given by the auto select logic. The same coding as that used
for Control Register bits C5:4 is used.

Four Power and ground pairs. All must be connected.

NAME

IP7:0

L7:0

BYPASS

HRES

X15:0

D15:0

PC1

PC0

DELOP

R/ W

PROG

CLK

BIN

RES

SINGLE

MASTER

OEN

CS3:0

F1:0

VCC / GND

PDSP16488A MA

BASIC OPERATION

The PDSP16488A convolver performs a weighted

sum of all the pixels within an N x N two dimensional window.
Each pixel value is multiplied by a signed coefficient, or weight,
and the products are summed together. In practice positive
weights would be used to produce averaging effects, with
various distribution laws, and negative weights would be used
for edge enhancement. The window is moved continuously
over the video frame, and for real time operation a new result
must be obtained for every pixel clock. In most applications
odd sized windows will be used, resulting in a centre pixel
whose value is modified by the surrounding pixels.

OUTPUT ACCURACY

With 8 bit pixels, and an 8 x 8 window, it is possible for

the accumulated sum to grow to 22 bits within a single device.
With 16 bit pixels, and an 8 x 4 window ( the maximum
possible ), the sum can grow to 29 bits. The PDSP16488A
actually allows for word growth up to 32 bits, and thus allows
several devices to be cascaded without any danger of over-
flow. Since coefficients can be negative, the final result is a 32
bit signed two's complement number.

In a particular application the desired output will lie

somewhere within these 32 bits, the actual position being
dependent on the coefficient values used. This causes prob-
lems in physically choosing which output pins to connect to the
rest of the system. To overcome this problem the
PDSP16488A contains an output multiplier, or gain control,
which allows the final result to be aligned to the most signifi-
cant end of the 32 bit internal result.The provision of a
multiplier, rather than a simple shifter, allows the gain to be
defined more accurately.

The sixteen most significant bits of the adjusted result are

available on output pins, and contain a sign bit.

OUTPUT SATURATION

If the output from the convolver is driving a display,

negative pixels will give erroneous results. An option is thus
provided which forces all negative results to zero, which are
then interpreted as black by the display. At the same time
positive results, which overflow the gain control, are forced to
saturate at the most positive number ie peak white. In this
mode the output sign bit is always zero,and should not be
connected to an A/D converter.

A separate option forces both negative and positive

overflows to saturate at their respective maximum values, but
in scale negative results remain valid. A gain control overflow
warning flag is also available, which can be used in a host CPU
supported system to change the gain parameters if overflows
are not acceptable.

BINARY OUTPUT

The PDSP16488A contains a 16 bit arithmetic com-

parator which allows the output from the gain control to be
compared with a previously programmed value. An output
flag allows the user to detemine if the result was above or
below a value contained within an internal register.

MULTIPLIER ARRAY

The PDSP16488A contains sixteen 8x8 multipliers

each producing a 16 bit result. Internally the pixel clock
supplied by the user can be multiplied by two or four, which
together with the proprietary architecture, allows each multi-
plier to be used several times within a pixel clock period. This
increases the effective number of multipliers, which are avail-
able to the user, from 16 to 32 or 64 respectively. This
architecture produces a very efficient utilization of chip area,
and allows the line delays to be accommodated on the same
device.

The sixteen multipliers are arranged in a 4 deep by 4

wide array, resulting in effective arrays of 4 by 8 or 8 by 8 with
the multi-cycling options. The multiplier array can also be
configured to handle 16 bit signed pixels; the effective number
of available multipliers is then halved.

LINE DELAY OPERATION

Internal RAM is arranged in two separate groups, and

can be configured to provide line delays to match the chosen
size of the convolver. When a four deep arrangement is used,
with 8 bit pixels, four line delays are available, and each can
be programmed to contain up to 1024 pixels. In an eight deep
array, or if16 bit pixels are needed, each line can contain up
to 512 pixels. Figure 4 illustrates the options available.

The first line delay in one of the groups can optionally

be switched in or out under the control of an input pin. It is used
to delay the pixel input when data is obtained from another
convolver in a multiple device system, or it is used to support
interlaced video.

Signals L7:0 may be used as pixel inputs or outputs.

They are configured as inputs at power-on to avoid possible
bus conflicts, but by setting a mode control bit can become
outputs. They can then be used to drive another device when
multiple PDSP16488A's are required.

INTERLACED VIDEO

When using real time interlaced video, a picture or

frame is composed from two fields, with odd lines in one field
and even lines in the other. An external field delay is thus
required to gather information from adjacent lines, and the
convolver needs two input busses. The bus providing the
delayed pixels has an extra internal line delay. This is only
used in the field containing the upper line in any pair of lines,
and must be bypassed in the other field. It ensures that data
from the previous field always corresponds to the line above
the present active line, and avoids the need to change the
position of the coefficients from one field to the next.

Figure 3 shows the translation from physical to internal

line positions, for single device interlaced systems. Line N is
the line presently being convolved, which is either one or two
lines previous to the line presently being produced.

When windows requiring four or more lines are to be

implemented, the first line delay, in the group supplied from
the L7:0 pins, must always be by-passed. This by-pass option
is controlled by Register B, bit 7 and is not effected by the
BYPASS input pin.. The coefficients must be loaded into the
locations shown, which match the translated line positions,
with unused coefficients, shown shaded, loaded with zero's.

PDSP16488A MA

Figure 3. Line Delay Allocations in Single Device Interlaced Systems

ODD
FIELD

N+4

512

8 X 8

ARRAY

Output is shifted

by 1 line in

every field

FIELD

DELAY

VIDEO

LINE N+2

ODD

FIELD

N+1

N-1

N-2

Delay is By-Passed

[REG B,BIT 7 IS SET]

N+2

IP7:0

L7:0

512

8 X 8

ARRAY

Output is shifted

by 2 lines in

every field

FIELD

DELAY

VIDEO

LINE N+4

N+3

N+1

N-2

N-1

N-3

N+2

IP7:0

L7:0

1024

4 X 4

8 X 4

ARRAY

FIELD

DELAY

VIDEO

LINE N+2

N+1

N - 1

Output is shifted

by 1 line in

every field

LINE N-2

LINE N-1

LINE N

LINE N+1

LINE N+2

5 X 5 WINDOW

C32

C33

C34

C35

C36

C40

C41

C42

C43

C44

C10

C11

C12

C48

C49

C50

C51

C52

LINE N-3

LINE N-2

LINE N-1

LINE N

LINE N+1

LINE N+2

LINE N+3

C48

C49

C50

C51

C52

C53

C54

C40

C41

C42

C43

C44

C45

C46

C10

C11

C12

C13

C14

C16

C17

C18

C19

C20

C21

C22

C32

C33

C34

C35

C36

C37

C38

C30

C29

C28

C27

C26

C25

C24

8 X 8 WINDOW

LINE N-1

LINE N

LINE N+1

3 X 3 WINDOW

C10

IP7:0

L7:0

Delay is By-Passed

[REG B,BIT 7 IS SET]

C31

C56

C57

C58

C59

C60

C61

C62

C63

C23

C55

C15

C47

C39

LINE N+4

ODD

FIELD

PDSP16488A MA

DEFINING THE LENGTH OF THE LINE DELAY

Figure 4 defines the maximum line lengths available in

each of the window size options. The actual line lengths can
be defined in one of three ways, to support both real time
applications, taking pixels directly from a camera, and also
use in systems supported by a frame store. In the former case
the line delays must be referenced to video synchronization
pulses. In the latter case the line lengths are well defined, and
the horizontal flyback 'dead times' will have been removed.

To support real time applications an option is provided

in which the length of the line delay is defined by the number
of clocks obtained whilst an input pin ( HRES ) is in-active.
HRES would normally be composite sync when the convolver
is directly attached to an NTSC or PAL video camera.

Conceptually, the line delay is achieved by reading the

previous contents of a RAM based line store, and then writing
new information to the same address. When HRES is active
write operations are inhibited, and the address counter is
reset. During an active line the counter is incremented by the
pixel clock. If the maximum count is reached before the end of
a line, then write operations are terminated and wrap-around
effects avoided.

The active going edge of HRES, marking the end of a

line, is normally asynchronous to the pixel clock, and it is
possible for an additional pixel to be stored on some lines. This
has no effect on the convolver operation, and will not cause a
cumulative shift in the pixel position from line to line.

Fig. 4. Line Delay Configurations

An alternative means of defining the line length is,

however, provided when an exact number of pixels is needed.
HRES going in-active then starts the delay operation for every
line, but it ceases when the 10 bit value contained in two
registers is reached. This method can avoid the need to store
blank pixels at the end of a line before sync goes active. With
this method the line must contain an even number of pixels,
but the value loaded into the control registers defining the line
length, must be one less than the even number needed.

In an image processing system, the pixel clock is often

re-synchronized, or even inhibited, during blanking or sync.
The next line is then started with a precise time interval from
the end of sync to the first pixel clock edge. This avoids any
visible pixel jitter at the beginning of the line, which would
otherwise be present since pixel clock is asynchronous with
respect to video sync pulses.

When using the PDSP16488A the pixel clock should

not be inhibited, or re-synchronized, until the delayed version
of the HRES input goes active. This is present on the DELOP
output pin. This will ensure that no pixels on the right hand
edge are lost due to the internal pipeline delay.

If the pixel clock is a continuous signal, the user must

ensure that the HRES in-active transition meets the timing
requirements defined in Figure 10. The active going edge at
the end of a line need not be synchronized.

When pixels are read/written to a frame store, an

alternative line delay configuration is needed. Within the
frame store lines would be stored in contiguous locations,
with no gaps caused by the flyback period between the lines.
This method of use makes the HRES defined line delay
operation difficult to use, and an alternative mode of operation
is provided. The HRES input is then driven by a system
provided signal, which defines a complete frame store update
period. It is not a line defining signal. The high to low transition
of this signal will initiate the line store update sequence and
allow the internal address pointers to increment. These point-
ers will be synchronously reset at the end of a line, when they
reach the pre-programmed value. They will then immediately
start a new operation using address zero. The actual line delay
must be pre-loaded into two control registers as described
previously.

Write operations back to the frame store must allow for

the total pipeline delay. This can be achieved by inhibiting
write operations until the delayed version of HRES goes low
at the DELOP output pin. Write operations then continue until
it goes back high. The PDSP16488A assumes that data is
valid when a clock signal is applied, and that it also meets the
set up and hold requirements given in Figure 10. If data is not
valid, due for example to a frame store DRAM refresh cycle,
then the user must externally inhibit the clock. The clock
supplied to the convolver will in this mode be a signal which
defines a frame store cycle time.

The use of the convolver in a line scan system is similar

to its use with a frame store. These systems have no flyback
period, and the address counter must be synchronously reset
at the end of the line and then allowed to continue.

GAIN CONTROL

The gain control is provided as an aid to locating the

bits of interest in the 32 bit internal result. The magnitude of the
largest convolved output will depend on the size of the

512

4X4

8X4

512

L7:0

IP7:0

1024

4 X 4

8 X 4

ARRAY

BYPASS

IP7:0

L7:0

512

BYPASS

IP7:0

L7:0

512

8X8

ARRAY

BYPASS

L7:0

IP7:0

512

1024

512

8x8

ARRAY

BYPASS

1024

4 X 4

8 X 4

ARRAY

BYPASS

IP7:0

L7:0

PDSP16488A MA

window, and the coefficient values used. The function of the
gain control is then to produce an output, which is accurate to
16 bits, and which is aligned to the most significant end of this
32 bit word. The sixteen most significant bits of the word are
available on output pins, and the largest number need only
have one sign bit if the gain control is correctly adjusted.

Fiigure 5 indicates the mechanism employed with the

required function implemented in two steps. Two mode control
bits allow one of four 20 bit fields to be selected from the final
32 bit value. These four fields are positioned with the first at
the most significant end, and then at four bit displacements
down to the least significant end.

By setting an enabling bit, the field selection can

optionally be done automatically. This feature should only be
used in the real time operating mode, when HRES defines
video lines. Internal logic examines the most significant 13, 9,
or 5 bits from the 32 bit result, and makes a field selection
dependent on which group does not contain identical sign bits.
If less than five sign bits are obtained, the logic will select the
field containing the most significant 20 bits.

The automatic selection is particularly useful when a

fixed scene is being processed. The selection is reset when
any internal register is updated ( ie PROG has been active )
and is then held in-active for ten further occurances of the
HRES input. This allows the internal multiplier/ accumulator
array to be completely flushed before a field selection is made.
As convolver outputs of greater magnitude are produced the
field selection logic will respond by selecting a more significant
field. The most significant field found necessary remains
selected until

PROG again goes active. Even if the automatic

field selection is not enabled, two outputs, F1:0, will still
indicate which field would have been selected. These are
coded in the same way as Register C, bits 5:4.

Having chosen a field, either manually or automati-

cally, it is then multiplied by a 4 bit unsigned integer. This is
contained within a user programmed register, and the multi-
plication will produce a 24 bit result . The middle 16 bits of this
result contain the required output bits. The gain control multi-
plier can overflow in to the unused most significant four bits if
the parameters are chosen wrongly. This condition is indi-
cated by an overflow flag .

By setting appropriate mode control bits, further ma-

nipulation of the gain control output is possible. One option
allows all negative outputs to be forced to zero, and at the
same time positive gain control overflows will saturate at the
maximum positive number. A different option will saturate
positive and negative overflows at their respective maximum
values, but otherwise leaves them unchanged. Occasional

overflows can be tolerated in some systems, and this option
prevents any gross errors.

EXPANSION

Multiple devices can be connected in cascade in order

to fabricate window sizes larger than those provided by a
single device. This requires an additional adder in each device
which is fed from expansion data inputs. This adder is not
used by a single device or the first device in a cascaded
system, and can be disabled by a mode control bit.

The first device in the cascaded system must be

designated as a MASTER device by tying an input pin low. Its
expansion input bus is then used as the source of data for the
coefficient and control registers in all devices in the system.

In order to reduce the pin count required for 32 bit

busses, both expansion in and data out are time multiplexed
with the phases of the pixel clock. When the clock is high the
least significant half will be valid, and when the clock is low the
most significant half will be valid.

In practice this multiplexing is only possible with pixel

clocks up to 20MHz. Above these frequencies the multiplexing
must be inhibited by setting a Mode Control bit ( Register A,
Bit 7 ). The intermediate data accuracy will then be reduced,
since only the lower 16 bits of the internal 32 bit intermediate
sum are available on the output pins. In such systems the
coefficients must be scaled down in order to keep the
intermediate and final results down to 16 bits. The final device
should not use the gain control, and instead should simply
output the non-multiplexed 16 bit result. The overflow flag and
pixel saturation options will not be available.

PIXEL INPUT AND OUTPUT DELAYS

In a real time system, when line delays are referenced

to video sync pulses present on the HRES input, the first pixel
from the last line delay does not appear on the L7:0 pins until
the fifth active pixel clock edge after HRES has gone low. This
is illustrated in Figure 7. In a vertically expanded system, this
output provides the input to the first line delays in the vertically
displaced devices. The internal logic is thus designed to
always expect this five clock delay. Compensation must thus
be applied to the devices which are directly connected to the
video source, such that the first pixel is not valid until the fifth
clock edge.

For this reason the PDSP16488A contains an optional

four clock pipeline delay on each of the pixel data inputs.
When the delay is used the first pixel in a video line must be
available on the input pins after the first pixel clock edge. This
would be so if the device were connected to an A/D converter,
since that would introduce a one pixel pipeline delay. If the
system introduces any further external pipeline delays, then
the internal delay should be bypassed, and the user should
ensure that the first pixel is valid after the fifth clock edge.

The use of this four clock delay is controlled by Bit 3,

in Control Register B. This delay is in addition to the delays
which are provided to support expansion in both the X and Y
directions, and are controlled by Register D, Bits 3:2. Both
delays are in fact simply added together in the device, but are
provided for conceptually different reasons.

Fig. 5. Gain Control Operation

MSB

LSB

D15:0

FROM EXPANSION ADDER

32 BITS

SATURATE

LOGIC

MUX

GAIN

REGISTER

PDSP16488A MA

DELAY COMPENSATION FOR LARGE WINDOWS

A large window is composed of several partial windows

each of which is implemented in an individual device. If
necessary the partial window must be padded with zero
coefficients to become one of the standard sizes. When
constructing a large window it is necessary to delay the
expansion data inputs in order to compensate for growth in the
horizontal direction. Delays in the partial sums are also
necessary to compensate for the total pipeline delay needed
to produce the previous complete horizontal stripe.

Within each device in a horizontal stripe, apart from

the first, the expansion input must be delayed by the width of
the partial window, before it is added to the internal sum. Since
partial windows can only be 4 or 8 pixels wide,a delay of 4 or
8 pixel clocks is needed. There is, however, an in-built delay

Fig. 6. Multi-Device Delay Paths

delays

line

delays

4 clock

delay

4 clock

delay

delays

B3 = 1

D3:2 = 00

D0 = 0

0/4

delays

line

delays

4 clock

delay

delays

B3 = 1

D3:2 = 00

D0 = 0 or 1

ZERO

WIDTH = S

0 IF S = 4, 4 IF S = 8

WIDTH = S

N th DEVICE IN THE ROW

INPUT

0/4

delays

line

delays

4 clock

delay

delays

B3 = 0

delays

line

delays

4 clock

delay

4 clock

delay

delays

B3 = 0

D0 = 0

D = 4+S(N-1) Defined by D3:2

WIDTH = S

0 IF S = 4, 4 IF S = 8

WIDTH = S

N th DEVICE IN THE ROW

0/4

delays

line

delays

4 clock

delay

delays

B3 = 0

D0 = 0 OR 1

delays

line

delays

4 clock

delay

delays

B3 = 0

D0 = 0

WIDTH = S

0 IF S = 4,4 IF S = 8

WIDTH = S

N th DEVICE IN THE ROW

OUTPUT

D = 4+S(N-1) Defined by D3:2

D0 = 0 OR 1

of 4 pixels in the inter device connection, and the
PDSP16488A thus only needs an option to delay the
expansion input by an additional four pixels.

The data from the last device in a horizontal row of

convolvers feeds the expansion input of the first device in the
next row. This is shown in Figure 6. With this arrangement, the
position of the partial window as illustrated, is the inverse of
its vertical position on a normal TV screen. Thus the top, left
hand, device corresponds to the bottom, left hand, portion of
the complete window.

The output from the last device in the row is delayed

with respect to the original data input by an amount given by
the formula;

DELAY = 4 + [N-1].S where N is the number of devices in

a row and S is the partial window width, ie 4 or 8.

PDSP16488A MA

Fig.7 Pixel Input Delays

Table 3 Internal Register Addressing

ble 4 Pipe line dalays

Function

Mode Reg A
Mode Reg B
Mode Reg C
Mode Reg D
Comparator LSB
Comparator MSB
Scale Value
Pixels / Line LSB
Pixels / Line MSB

Hex. Addr

00
01
02
03
04
05
06
07
08

C0 - C15
C16 - C31
C32 - C47
C48 - C63
Unused

40 - 4F
50 - 5F
60 - 6F
70 - 7F
09 - 3F

last 2

pixels

intern-

ally

stored

LINE STORE

WRITES INHIBITED

ACTIVE LINE PERIOD

ASYNCHRONOUS BACK EDGE

HRES

CLOCK

Set Up

Time

[SYNC]

First

pixel
valid

[B3 set]

First

pixel

from

line

store

valid

configurations when the gain control is used. These delays
are the the internal processing delays and do not include the
delays needed to move a given size window completely into
a field of interest. When multiple devices are needed, addi-
tional delays are produced which must be calculated for the
particular application. These delays are discussed in the
applications section.

The PDSP16488A contains facilities for outputing a

delayed version of HRES to match any processing delay.
Control register bits allow this delay to be selected from any
value between 29 and 92 pixel clocks.

The internal convolver sums, in each of the devices in

the next row, must be delayed by this amount before they are
added to results from the previous row. This is more conven-
iently achieved by delaying data going into the line stores. The
required cumulative delay with respect to the first horizontal
stripe is then automatically obtained when more than two rows
of devices are needed.

Two bits in Control Register D are used to define one

of four delay options. These delays have been selected to
support systems needing from two to eight devices and are
described in the applications section.

COEFFICIENTS

Sixty-four coefficients are stored internally and must

be initially loaded from an external source. Table 3 gives the
coefficient addresses within a device, with coefficent C0
specified by the least significant address and C63 by the most
significant address. Table 5 shows the physical window posi-
tion within the device which is allocated to each coefficient in
the various modes of operation. Horizontally the coefficient
positions correspond to the convolution process as if it were
conceptually observed on a viewing screen, ie the left hand
pixel is multiplied with C0. In the vertical direction the lines of
coefficients are inverted with respect to a visual screen, ie the
line starting with C0 is actually at the bottom of the visualized
window.

The coefficients may be provided from a Host CPU

using conventional addressing, a read/write line, data strobe,
and a chip enable. Alternatively, in stand alone systems, an
EPROM may be used. A single EPROM can support up to 16
devices with no additional hardware.

When windows are to be fabricated which are smaller

than the maximum size that the device will provide in the
required configuration, then the areas which are not to be used
must contain zero coefficients. The pipeline delay will then be
that of a completely filled window.

TOTAL PIPELINE DELAY

The total pipeline delay is dependent on the device

configuration and the number of devices in the system. Table
4 gives the delays obtained with the various single device

Data

size

Window

Size

Pipeline

Delay

8
8
8

16
16

34
30
26
28
26

4x4
8x4
8x8
4x4
8x4

PDSP16488A MA

Table 5 Physical Coefficient Position

NOTE
Two coefficients occuring in the same box have identical values

1024

C15

C23

C31

C16

C24

C10

C11

C12

C13

C14

C17

C18

C19

C20

C21

C22

C25

C26

C27

C28

C29

C30

8X4, 8 Bit Data

512

C16

C20

C24

C12

C28

C17

C18

C19

C21

C22

C23

C25

C10

C26

C11

C27

C13

C29

C14

C30

C15

C31

4X4, 16 Bit Data

C12

C10

C11

C13

C14

C15

4X4, 8 Bit Data

C32

C33

C34

C35

C36

C37

C38

C39

C15
C47

C23
C55

C31
C63

C40

C16
C48

C24
C56

512

C41

C10
C42

C11
C43

C12
C44

C13
C45

C14
C46

C17
C49

C18
C50

C19
C51

C20
C52

C21
C53

C22
C54

C25
C57

C26
C58

C27
C59

C28
C60

C29
C61

C30
C62

8X4, 16 Bit Data

C16

C24

C32

C40

C48

C56

C15

C23

C31

C39

C47

C55

C63

C10

C11

C12

C13

C14

C17

C18

C19

C20

C22

C21

C25

C26

C27

C28

C29

C30

C38

C37

C36

C35

C34

C33

C41

C42

C43

C44

C45

C46

C54

C53

C52

C49

C50

C51

C57

C58

C59

C60

C61

C62

8X8, 8 Bit Data

512

1024

MSB

LSB

MSB

LSB

IP7:0

L7:0

IP7:0

L7:0

IP7:0

L7:0

IP7:0

L7:0

PDSP16488A MA

LOADING REGISTERS FROM A HOST CPU

The expansion data inputs [X14:0] on a single or

master device are connected to the host bus to provide
address and data for the internal registers. In a multiple device
system the remaining devices receive addresses and data
which have been passed through the expansion connection
between earlier devices in the cascade chain. Each device
needs an individual chip enable plus a global data strobe,
read/write line, and

PROG signal from the host.

Registers are individually addressed and can be

loaded in any sequence once the global

PROG signal has

been produced by the host. The latter would normally be
produced from an address decode encompassing all the
necessary device addresses.

If a self timed system is to be implemented, a timing

strobe must be passed down the expansion chain through the
PC1/PC0 connections. The PC0 output from the final device
is used as a host REPLY signal, and indicates that the last
device has received data after the propogation delay of
previous devices. The timing strobe is produced in the
MASTER device from the host data strobe, and will appear on
the

PC0 output. This feature allows the user to cascade any

number of devices without knowing the propogation delay
through each device. The timing information for this mode of
operation is given in Figure 8.

The host can also read the data contained in the

internal registers. The required device is selected using chip
enable with the R/

W line indicating a read operation. Single

device systems output the data read on X7:0, but in multiple
device systems data is read from the D7:0 outputs on the final
device in the chain. These must be connected back to the host
data bus through three-state drivers. When earlier devices in
the chain are addressed, the register contents are transferred
through the expansion connections down to the final device.
In the self timed configuration the data will be valid when the
REPLY goes active, as shown in Figure 8.

If the

REPLY signal is not to be used , the PC0/PC1

connections are not necessary, and the host data strobe for a
write operation must be wide enough to allow for the worst
case propogation delay through all the devices ( TDEL ). If the
data or address from the host does not meet the set up time
given in Fugure 8, the width of the data strobe can be simply
extended to compensate for the additional delay. When read-
ing data the access time required is: TACC + ( N - 1 ).TDEL
using the maximum times obtained from Figure 8.

HOST CONTROL LINES

X7:0

8 bit data bus. In a single device system this bus is
bi-directional; in other configurations it is an input.
Only a SINGLE or MASTER device is connected
directly to the host. Other devices receive data from
the output of the previous device in the chain.

X14:8

7 bit address bus which is used to identify one of
the 73 internal registers. Connected in the same
manner as X7:0.

X15

X15 must be open circuit on the MASTER device

PC0

An input from the previous PC1 output in a multiple
device chain. Not needed on a SINGLE device or
if the self timed feature is not used.

PC1

Reply to the host from a SINGLE device or from the
last device in a cascade chain. It indicates that the
write strobe can be terminated. Connected to PC0
input of the next device at intermediate points in the
chain if the self timed feature is used.

Read/Not Write line from the host CPU which is
connected to all devices in the system.

An active low enable which is normally produced
from a global address decode for the particular
device. This must encompass all internal register
addresses.

An active low host data strobe which is connected
to all devices. in the system.

PROG

An active low global signal, produced by the host,
which is connected to all devices in the system.
Together with a unique chip enable for every de-
vice, it allows the internal registers to be updated
or examined by the host. PROG and CE should be
tied together in a single device system.

LOADING REGISTERS FROM AN EPROM

In the EPROM supported mode, one device has to

assume the role of a host computer. If more than one device
is present, this must be the first component in the chain,
which must have its

MASTER pin tied low.

The MASTER device contains internal address count-

ers which allow the registers in up to 16 cascaded devices to
be specified. It also generates the

PROG signal and a data

strobe on the pins which were previously inputs. These
outputs must be connected to the other devices in the system,
which still use them as inputs. The R/W input should be tied
low on all devices.

The width of the data strobe is determined by the

feedback connection from the PC1 output on the last device
to the

PC0 input on the MASTER. The PC0/PC1 connections

must be made between devices in a multiple device system;
in a single device system the connection is made internally.

The available EPROM access time is determined by

an internal oscillator and does not require the pixel clock to be
present during the programming sequence. Any pixel clock re-
synchronization in a real time system will thus not effect the
coefficient load operation. The relevent EPROM timing infor-
mation is shown in figure 9.

The load procedure will commence after reset has

gone from active to in-active, and will be indicated by the
PROG output going active. The data from 73 EPROM loca-
tions will be loaded into the internal registers using addresses
corresponding to those in Table 3. Within a particular page of
128 EPROM locations, the first nine locations supply control
register information, and the top 64 supply coefficients. The
middle 55 locations are not used. If the window size is 8 x 4,
the top 32 locations will also contain redundant data, and if
the size is 4 x 4 the top 48 will be redundant.

PDSP16488A MA

In a multiple device system the load sequence will be

repeated for every device, and four additional address bits will
be generated on the CS3:0 pins. These address bits provide
the EPROM with a page address, with one page allocated to
each device in the system. Within each page only 73 locations
provide data for a convolver, the remainder are redundant as
in the single device system. The CS3:0 outputs must also be
decoded in order to provide individual chip enables for each
device. These can readily be derived by using an AS138 TTL
decoder. Bits in an internal control register determine the
number of times that the sequence is repeated.

If changes to the convolver operation are to be made

after power-on, activating the

CE input on the MASTER or

SINGLE device will instigate the load procedure. Additional
EPROM address bits supplied from the system will allow
different filter coefficients to be used.

EPROM CONTROL LINES

X7:0

8 bit data from the EPROM to the MASTER or
SINGLE device. Otherwise data is received from
the previous device in the chain.

X14:8

Lower 7 address bits to the EPROM from a MAS-
TER or SINGLE device. Otherwise an input from
the data outs of the previous device.

X15

Tied to ground on a MASTER device to indicate the
EPROM mode.

Tied low on all devices.

An output from a MASTER or SINGLE device
which provides a data strobe for the other devices.

CS3: 0

Four additional address bits for the EPROM which
are provided by the MASTER device. They allow
16 additional devices to be used and must be
externally decoded to provide chip enables.

.
PC0

An input on the MASTER device which is driven
from the

PC1 output of the last device in the chain.

Used internally to terminate the write strobe. Con-
nected to previous

PC1 outputs at intermediate

points in the chain. Not needed for a SINGLE
device.

PC1

An output connected to the

PC0 input of the next

device in the chain. The last device feeds back to
the MASTER. Not needed for a SINGLE device.

An enable which is produced by decoding CS3:0
from the MASTER. It is not needed for a MASTER
or SINGLE device which will always use the
bottom block of addresses with internally gener-
ated write strobes. It can however be used on
these devices to initiate a new load procedure
after the initial power on sequence.

PROG

An active low going signal produced by an
EPROM supported MASTER or SINGLE device.
An input to all other devices. It indicates that a

register load sequence is occuring, either after
power on, or as the result of CE as explained above.
It remains active until register 73 in the final device
has been loaded. Four bits in a control register
define the number of cascaded devices.

SYSTEM CONFIGURATION

The device is configured using a combination of the state of

the

SINGLE and MASTER pins, and the contents of the four

Mode Control registers. In a MASTER or SINGLE device the
state of the X15 pin is used to define whether the system is
EPROM or host supported.

MODE CONTROL REGISTERS

REGISTER A Bit Allocation

BITS 3:0 These bits are 'don't care' when using a host

computer but to a MASTER device, in an EPROM
supported system, they define the number of inter-
connected chips. The EPROM must contain con-
tiguous 128 byte blocks for each of the devices in
the system and a 4 bit counter in the MASTER
device will sequence through up to 16 block reads.
An internal comparator in the MASTER causes the
loading of the internal registers to cease when the
value in the counter equals that contained in these
bits. The bits are redundant in a SINGLE device
which only uses one 128 byte block.

BITS 6:4 These bits define one of the five basic configura-

tions. The line delays will automatically be config-
ured to match the chosen window size and pixel
accuracy. The maximum clock rate that is avail-
able to the user reflects the internal mutiplication
factor.

BIT

3:0

6:4

7
7

CODE

XXXX

000

001

010

011

101

0
1

FUNCTION

Number of extra devices from1-15

8 bit, 8x8 window, 10MHz max,
8x512 line delays.
16 bit, 8x4 window, 10MHz max,
4x512 line delays.
16 bit, 4x4 window, 20MHz max,
4x512 line delays.
8 bit, 8x4 window, 20MHz max,
4x1024 line delays.
8 bit, 4x4 window, 40MHz max,
4x1024 line delays
Multiplexed exp. data
Non-mux. exp. data

PDSP16488A MA

REGISTER C Bit Allocation

FUNCTION

Field selection defined by C5:4

Automatic field selection

DELOP = 29 + 0 clks

DELOP = 29 + 8 clks

DELOP = 29 + 16 clks

DELOP = 29 + 24 clks

DELOP = 29 + 32 clks

DELOP = 29 + 40 clks

DELOP = 29 + 48 clks

DELOP = 29 + 56 clks

Select upper 20 bits

Select next 20 bits

Select bottom 20 bits

By-pass the gain control

Normal gain control O/P

Saturate at max + and -ve values.

Force -ve to zero.Sat.+ve values.

CODE

000

001

010

011

100

101

110

111

BIT

3:1

5:4

7:6

BIT 7

This bit must be set if the pixel clock is greater than
20MHz. It disables the output and input time
multiplexing, and instead outputs the least signifi-
cant half of the 32 bit intermediate sum for the
complete clock cycle. When the gain control is
used, the output multiplexing will automatically be
disabled.

BIT 0

This bit defines the input for the second group of
line delays. It must be set in the 16 bit pixel modes,
and is set by power on reset.

BIT 2:1

These bits control the mode of operation of the line
stores. In real time systems pixels can be stored
either until HRES [ SYNC ] goes active , or until a
pre-determined count is reached. In the frame
store mode line store operations are continuous,
with a pre-determined line length.

BIT 3 When this bit is set four pipeline delays are added

to the pixel inputs to compensate for the internal/
external delays between line stores. The extra
delay is only necessary when a device supplied
with system video in which the first pixel in a line
is valid in the period following the first active clock
edge. See Fig 7. The delay is not necessary if the
device is fed from the output of another convolver.
When set this bit will add four additional delays to
those defined by Register D, bits 4: 2.

BIT 4

When this bit is set the expansion adder will not be
used. It is automatically set in a MASTER or SIN-
GLE device.

BIT 7

This bit controls the bypass option on the first line
delay on the L7:0 inputs. It is only effective when
an 8 bit pixel mode is selected, which also needs
more than four line delays. When L7:0 are used as
outputs it should always be reset. In the 16 bit
modes the bypass function is only controlled by the
BYPASS pin, and the bit is redundant.

FUNCTION

Second line delay group fed from the
first group
Second line delay group fed from L7:0
which become inputs
Store pixels to end of line
Store pixels till count is reached
Frame store operation
Not Used
No delays on pixel inputs
4 delays on both pixel inputs
Use expansion adder
Expansion adder disabled
Not used
Use first delay in second group
Bypass first delay in second group

BIT

2:1
2:1
2:1
2:1
3
3
4
4
6:5
7
7

CODE

00
01
10
11
0
1
0
1

0
1

REGISTER B Bit Allocation

BIT 0

If this bit is set, the 20 bit field selected from the 32
bit result, is defined automatically by internal logic.

BITS 3:1 These bits are in conjunction with Register D, bits

7:5 to define the pixel delay from the HRES input
to the DELOP pin. They are used to match the
appropriate processing delay in a particular sys-
tem. The minimum delay is 29 pixel clocks.

BITS 5:4 These bits define which of the four 20 bit fields out

of the 32 bit final result is selected as the input to
the gain control. They are redundant when the gain
control is not used, or if Register C, bit0, is set.

BITS 7:6 These bits define the use of the gain control as

given in the table. Intermediate devices in a mul-
tiple device system MUST by-pass the gain con-
trol, otherwise the additional pipeline delays will
effect the result. Disabling the scaler will reduce
the device pipeline by 13 PCLK cycles from the
delays shown in Table 4.

PDSP16488A MA

FUNCTION

X15:0 Not delayed

X15:0 Delayed

Internal sum not shifted

Internal sum multiplied by 256

I/P to line stores not delayed

I/P to line stores delayed by 4

I/P to line stores delayed by 8

I/P to line stores delayed by 12

Un-signed pixel data input

2's complement pixel data input

Add 0 to 7 clock delays to DELOP

output.

CODE

XXX

BIT

3:2

7:5

REGISTER D Bit Allocation

BIT 0 If this bit is set the expansion data input is delayed

by four pixel clocks before it is added to the present
convolver output. It is used in multiple device
systems when the partial window width is 8 pixels.

BIT 1

When this bit is set the internal sum is shifted to the
left by 8 places before being added to the expan-
sion input. It is used when two devices are used,
each in an 8 bit pixel mode, to fabricate a 16 bit
pixel mode.

BITS 3::2 These bits define the delays on both sets of pixel

inputs before entering the line stores. The delays
are always identical on both sets.

BIT 4

When this bit is set the convolver interprets 8 or 16
bit pixels as 2's complement signed numbers

BIT 7:5

These bits add 0 to 7 additional clock delays to
those selected by Register C, bits 3:1.

ABSOLUTE MAXIMUM RATINGS [See Notes]

Supply voltage Vcc

-0.5V to 7.0V

Input voltage V

-0.5V to Vcc + 0.5V

Output voltage V

OUT

-0.5V to Vcc + 0.5V

Clamp diode current per pin I

(see note 2)

18mA

Static discharge voltage (HMB)

500V

Storage temperature T

-65

�C to 150�C

Max. junction temperature Military

150

�C

Package power dissipation

3000mW

Thermal resistances, junction to case �

�C/W

NOTES ON MAXIMUM RATINGS
1. Exceeding these ratings may cause permanent damage.
Functional operation under these conditions is not implied.
2. Maximum dissipation or 1 second should not be exceeded,
only one output to be tested at any one time.
3. Exposure to absolute maximum ratings for extended
periods may affect device reliablity.
4. Current is defined as negative into the device.

Characteristic

Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input leakage current
Input capacitance
Output leakage current
Output S/C current

STATIC ELECTRICAL CHARACTERISTICS

Operating Conditions (unless otherwise stated)

amb

=-55

�C to +125�C. V

= 5.0v

� 10%

NOTE: Signal pins

PC0, X15, MASTER, SINGLE, BYPASS and 0V have pull-up resistors in the range 15k

to 200k.

Signal pins

PROG and DS require external pull-up resistors in EPROM mode.

Conditions

= 4mA

= -4mA

Except CLK,

RES = 4V

GND < V

< V

.No internal pull up

GND < V

OUT

< V

.No internal pull up

= Max

Min.

2.4

2.0

-10

-50

Value

Typ.

Symbol

Max.

0.4

0.8

+10

+50
300

Units

V
V
V
V

�A
pF
�A

Subgroup

1,2,3
1,2,3
1,2,3
1,2,3
1,2,3

1,2,3

*
*
*
*
*

*

Delay from output
high to output
high impedance

Test

Waveform - measurement level

Delay from output
low to output
high impedance

0.5V

1.5V

0.5V

1.5V

0.5V

Delay from output
high impedance to
output low

Delay from output
high impedance to
output high

V - Voltage reached when output driven high
V - Voltage reached when output driven low

PDSP16488A MA

FIG. 8. Host Timing

PCH

EXP

T DSH

PC1 from
MASTER or SINGLE device

PC1 from last
device (REPLY)

HSU

VALID

Address/data
from the Host

Host Data O/P
from First Device

DEL

VALID

Host Data Strobe

Chip Enable

DATUM

PROG

PSU

Wait

PCH

csu

ACC

RSU

R/W from the Host

Coefficient
Output

RSU

PC1 In-active Delay after DS in-active

Symbol

Characteristic

Value

Units

Notes

Min.

Max.

DS Hold Time after REPLY active

Host Address/data Set Up Time

T
T

DSH
HSU

Host Signal Hold Time

Expansion in to Data Out in PROG mode
Delay from strobe to PC1

Chip Enable Set Up Time

PROG Set Up Time

T
T

DEL

EXP

CSU

PSU

PCH

[Equivalent to PC0 to PC1 delay ]

Greater than TDEL under all conditions

PROG Hold Time

Chip Enable Hold Time

T PH

Coefficient Read Time

Coefficients valid Time before REPLY

ACC

Only applicable if REPLY is used. Otherwise
time is referenced to risng edge of strobe
when set up must be N xTDEL, for N devices

Read Set UpTime to prevent Write

Only applicable for read ops & if REPLY is used.

Must always be guaranteed.

No clocks are needed in PROG mode

Defines Data Strobe in-active time

From MASTER or SINGLE device

All parameters marked * are tested during production.
Parameters marked are guaranteed by design and characterisation

PDSP16488A MA

APPLICATIONS INFORMATION

DEVICE REQUIREMENTS

The number of devices required to implement a given

convolver window depends on the size of the window, the
required pixel rate, and whether the pixel accuracy is to be 8
or 16 bits. In practice the PDSP16488A supports windows
requiring one, two, four, six, or eight devices without addi-
tional logic. Table 2 gives typical window sizes which may be
obtained with the above number of devices.

Figures 11 through 18 show system interconnections

for these arrangements. Other configurations are possible but
may need the support of additional pixel/line delays and/or
expansion adders. Although not necessarily shown, all con-
figurations can be supported by either an EPROM or a Host
Computer . Interlaced or non-interlaced video may also be
used, unless explicitly stated otherwise in the text.

Expansion with 8 bit pixels is a straightforward process

and the number of devices needed is easily deduced from the
window sizes available in a single device. At pixel rates above
20MHz it may not be practical to use more than four devices.
since the full 32 bit intermediate precision is not available. The
lack of expansion multiplexing reduces the intermediate pre-
cision to 16 bits. The partial sum outputs must thus not
overflow these 16 bits; this will require the coefficients to be
scaled down appropriately with a resulting loss in accuracy.

Expansion with 16 bit pixels can be achieved in several

ways. The simplest way is to use two devices, each working
with 8 bit pixels. One device handles the least significant part
of the data, and its output feeds the expansion input of a
second device. This performs the most significant half of the
calculation. The least significant half is then added to the most
significant sum, after the latter has been multiplied by 256 ie
shifted by eight places. This shift is done internally and
controlled by Register D, bit 1. The internal 32 bit accuracy
prevents any loss in precision due the shift and add operation.

The window size with this arrangement is restricted to

that available in a single device, at the required pixel rate but
with 8 bit pixels. Thus two devices can be used , for example,
to provide an 8 x 8 window with 16 bit pixels and 10 MHz rates.

If a larger extended precision window is needed, it is

possible to use four devices. Each device is then programmed
to be in a 16 bit data mode, but should be restricted to rates
below 20 MHz, if the 32 bit intermediate precision is to be
maintained. In the 16 bit modes, however, the output from the
last line delay is not available due to pin limitations. This is not
a problem in a four device interlaced system, since half of the
devices will be fed from an external field delay. In non
interlaced systems additional external line delays would be
needed. An alternative approach would be to configure all the
devices in the appropriate 8 bit mode, do separate least
significant and most significant calculations, and then com-
bine the results in an external adder after a wired in shift.

SINGLE DEVICE SYSTEMS

Figures 11 illustrates both EPROM and Host sup-

ported single device systems, with or without interlaced video.
In both cases the

SINGLE and X15 pins must be tied tied low,

and the

PC0, PC1, and DS pins are redundant. The PROG pin

becomes an output and indicates that a register load se-
quence is occuring. The first line delay must always be
bypassed in a non interlaced system, however, since an
internal pull up is not provided, the BYPASS pin should be tied
to VCC for the correct operation. With interlaced video the
BYPASS input is used to distinguish between the odd and
even fields.

The CE input may be left open circuit if coefficients are

to be simply loaded after a power on reset signal; the latter
being applied to the

RES input. Alternatively the CE input may

be used to change the coefficients at any time after power on
reset; the EPROM would then need additional address bits for
the extra sets of coefficients that are to be stored.

In an interlaced system the pixels from the previous

field must use the IP7:0 inputs, and the live pixels must use the
L7:0 inputs. Interlaced sysytems requiring extended precision
pixels are non supported with a single device, since the L7:0
inputs are then use for the least significant 8 bits, and the IP7:0
inputs for any more significant bits.

If the X15 pin is left open circuit, an internal pull up will

configure the device in the host supported mode. The host
must then supply a data strobe and a R/

W control line. The

X7:0 pins must be connected to the host data bus, and are
used to both load and read back register values. The

PROG

and CE pins may be connected together, and then driven by
a host address decode. The output on

PC1, which provides a

REPLY to the host, need not be used if the width of the data
strobe is greater than the maximum TEXP value given in
Figure 7.

The configuration bits 6:4 in REGISTER A define the

window size, maximum pixel rate, and pixel resolution. Win-
dow sizes smaller than the maximum in any configuration are
implemented by filling in the window with `zero' coefficients.
Bits 3:0 are irrelevent in the SINGLE mode, as is bit 7 if the gain
contol is used.

The result would be expected to lie in either the bottom 20

bits of the 32 bit result , or possibly in the next 20 bit field
displaced by four bits. Register C, bits 5:4, must thus select
one of these fields for subsequent use by the gain control. The
gain is then adjusted such that the 16 outputs available on
pins are in fact the 16 most significant bits of the result. The
gain needed is application specific, but if too much gain is used
the OV pin will indicate an overflow.

method of defining the length of the line delays, and the use
of bit 3 is dependent on any external pixel delays before the
convolver input. No additional delays are needed on the pixel
inputs in a single device system, and REGISTER D, bits 4:2,
should be reset. The pipeline delay in the DELOP output path
should match one of those in Table 4, and is window size
dependent.

DUAL DEVICE CONFIGURATIONS

Two devices, each configured with 8 bit pixels and 8W

x 4D windows, can be used to provide an 8 x 8 window at up
to 20 MHz pixel rates. Figure 12 shows both the non interlaced
and interlaced arrangements.

Video lines containing up to 1024 pixels are possible

in both configurations, since each device only needs four line
delays. One device is configured as the MASTER by ground-
ing the

MASTER pin; the other then receives control signals in

PDSP16488A MA

the normal way and has its

MASTER and SINGLE pins left

open circuit.

The internal convolver sum, in the device producing

the final result, must be delayed by 4 pixels to match the
inherent delay in the expansion output from the other device.
This is actually achieved by delaying the pixel inputs to the line
stores [ Register D bits 3:2 = 01 ]. No additional delay in the
expansion input is needed, but the pipeline delay used to
produce DELOP must be four clocks greater than that given
in Table 4 for a single device. The DELOP output is redundant
in one of the two devices.

Two devices can also be used to support systems

requiring 16 bit pixels. With this approach the 16 x 8 multipli-
cation is mechanized as two 8 x 8 operations, with the results
added together after the most significant half has been shifted
by 8 places to the most significant end. This shift operation is
controlled by Register D, Bit 1. Both convolvers are pro-
grammed to contain the same coefficients. The convolved
output can theoretically grow to 30 bits, and the appropriate
field must be selected before using the gain control.

Examples of this operating mode are shown in Figure

13. Each device must be configured in the same 8 bit pixel
operating mode, but the device producing the final result must
use the 8 place shift option on its internal sum.

The least significant 8 bits of the pixel are connected to

the MASTER device and the most significant 8 bits are
connected to the device producing the final result.. The
internal sum in this device must be delayed by four pixels to
match the delay in the expansion output from the first device.
This is actually achieved by delaying the pixel inputs to the line
stores( Register D, bits 4:2, = 001 ]. The expansion input
needs no additional delay [ Register D bits 1:0 = 10 ].

The actual pixel precision can be any number of pixels

between 8 and 16, and may be a signed or unsigned number.
Any unused, more significant bits, must respectively be either
sign extended or be tied low.

DELOP must have four additional pipeline delays in order

to match the total processing delay. This output can be
obtained from either device.

FOUR DEVICE SYSTEMS

Four devices, each in the 8x8 mode, can be used to provide

a 16 x 16 window, with 8 bit pixel resolution and 10 MHz clock
rates. The partial sum from the first device in each row must
be delayed by eight pixel clocks before it is added to the result
from the next device. This provides the eight pixel displace-
ment to match the width of the window. The delay is actually
provided by four additional delays in the expansion input to the
next device, plus the inherent four clock delays in outputing
results from the first device. Register D, Bit 0 controls the
additional delay.

The internal convolver sums, in the two devices in the

second row, must be delayed by 12 clocks before they are
added to the result from the first row. This twelve clock delay
is necessary because of the combination of the eight pixel
horizontal displacement delay , and the four clock delay in
outputing the result from the last device in the top row. It is
actually achieved by delaying the pixel inputs to the line stores.
(Register D, bits 3:2 = 11 ].

The DELOP output must have 20 delays additional to

those in a single device. This compensates for the twelve
delays added to the convolver sums in the second row, plus
an additional eight delays to compensate for the partial width
of the first device in the secind row.

Four devices can also be used to give an 8x8 window,

but with a 30 MHz pixel clock. Each device is configured to
provide a 4x4 partial window, but the maximum pixel rate is
reduced from 40 to 30 MHz because of the response of the line
delay expansion circuitry. Intermediate precision is restricted
to 16 bits, since time multiplexed data outputs cannot be used
above 20 MHz.

This configuration requires no additional delay in the

expansion inputs, and the inputs to the line stores in both
devices in the second row must be delayed by 8 clock cycles
[ Register D bits 3:2 = 10 ]. The DELOP output needs twelve
additional clock delays to match the processing delay.

Figures 14 and 15 show non-interlaced and interlaced

versions of the above 8 x 8 and 4 x 4 arrangements

Figure 16 shows how four devices can also be used to

provide an 8x8 window, with 16 bit pixels and 20MHz clock
rates. The expansion data from a previous device needs no
additional delay since the partial window size in each device
is only 4x4. The internal convolver sums from each device in
the second row must be delayed by 8 Clks and the DELOP
output must have 12 additional delays. If this arrangement is
to be used in a non-interlaced application, the field store must
be replaced by four line delays.

SIX DEVICE SYSTEMS

As shown in figure 17, six devices, each in an 8Wx4D

mode using 8 bit pixels, can provide a 16W x 12D window at
20MHz clock rates. Expansion inputs from previous devices
in a row [but not the first device in each row] need an extra 4
Clks of delay since the partial window is eight pixels wide.
Internal convolver sums need a differential delay of 12 Clk
cycles from row to row [ Register D bits 3:2 = 11 ].

The DELOP output must have 32 additional delays to

match the total processing delay.

EIGHT DEVICE SYSTEMS

Two additional chips will extend the above six device

configuration to a 16 x 16 window. Internal convolver sums
must have differential delays of 12 clock cycles between rows,
as in the six device system. The DELOP output needs 44
additional clock delays.

NINE DEVICE SYSTEMS

Nine devices each in the 8 x 8 mode will provide a 24

x 24 window with 8 bit data and 10 MHz pixel clocks. This is
shown in Figure 18. Expansion data inputs from previous
devices in a row [ but not the first device in each row ] need an
extra 4 Clks of delay. The internal convolver sums need
differential delays of 20 Clk cycles between rows. Sixteen of
the latter delays can be provided internally by setting Register
B, bit3, and also Register D, bits 3:2. The four extra delays
must be provided externally.

The DELOP output needs 56 clock delays in addition

to the 29 required for the 8 x 8 single device configuration.

PDSP16488A MA

EPROM

DATA

X15

X14:8

X7:0

IP7:0

HRES

BYPASS

L7:0

PDSP
16488

BIN

O/C

GND

R/W

PROG

D15:0

DELOP

CHANGE
COEFFICIENTS

RES

PROG

O/C

SNG

CLK

MSTR

GND

BIN

GND

PIXEL
DATA

SYNC

LEAST SIG

BYTE OF 16

BIT PIXEL

OEN

OVERFLOW

CLOCK

DATA OUT

DELAYED
SYNC

RESET

OUTPUT

ENABLE

ADDR

HOST CPU

ADDR

DATA

R/W

ADDRESS
DECODE

X15

IP7:0

HRES

BYPASS

L7:0

O/C

R/W

D15:0

DELOP

RES

PROG

O/C

PC1

SNG

CLK

MSTR

BIN

GND

PIXEL
DATA

SYNC

LEAST SIG

BYTE OF 16

BIT PIXEL

OEN

BIN

OVERFLOW

CLOCK

DATA OUT

DELAYED
SYNC

RESET

OUTPUT

ENABLE

PC0

PDSP
16488

X14:8

X7:0

X15

X14:8

X7:0

IP7:0

HRES

BYPASS

L7:0

PDSP
16488

PIXEL
DATA

O/C

GND

SYNC

R/W

PROG

D15:0

DELOP

RES

PROG

SNG

CLK

MSTR

GND

BIN

GND

OEN

BIN

OVERFLOW

CLOCK

DATA OUT

DELAYED
SYNC

CHANGE
COEFFICIENTS

RESET

OUTPUT

ENABLE

FIELD

DELAY

ODD

FIELD

EPROM

DATA

ADDR

HOST CPU

ADDR

DATA

R/W

ADDRESS
DECODE

X15

X14:8

X7:0

IP7:0

HRES

BYPASS

L7:0

PIXEL
DATA

O/C

SYNC

R/W

D15:0

DELOP

RES

PROG

PC1

SNG

CLK

MSTR

BIN

GND

OEN

BIN

OVERFLOW

CLOCK

DATA OUT

DELAYED
SYNC

RESET

OUTPUT

ENABLE

PC0

PDSP
16488

FIELD
DELAY

ODD
FIELD

Figure 11 Single Device Systems

VCC

PDSP

16488A

PDSP

16488A

PDSP

16488A

PDSP

16488A

PDSP16488A MA

EPROM

DELAYED
SYNC

CLOCK

BIN

OVERFLOW

DATA OUT

SYNC

O/C

MSB

O/C

8 BIT

PIXEL

DATA

RESET

O/P ENABLE

PC0

X15

X14:8

X7:0

IP7:0

HRES

BYPASS

L7:0

D15:0

PROG

PDSP

16488

8X4

WINDOW

GND

RES

PC1

CS0

SNG

MST

R/W

GND

DELOP

O/C

GND

CS1

PC0

X15

X14:8

X7:0

IP7:0

HRES

BYPASS

L7:0

D15:0

PROG

CLOCK

PDSP

16488

8X4

WINDOW

RES

PC1

SNG

MST

R/W

OEN

O/C

GND

O/C

BIN

OEN

GND

DELAYED
SYNC

CLOCK

BIN

OVERFLOW

DATA OUT

SYNC

O/C

8 BIT
PIXEL
DATA

RESET

O/P ENABLE

X15

X14:8

X7:0

IP7:0

HRES

BYPASS

L7:0

D15:0

PROG

CLOCK

PDSP

16488

8X4

WINDOW

O/C

RES

PC1

SNG

MST

R/W

GND

DELOP

O/C

PC0

X15

X14:8

X7:0

IP7:0

HRES

BYPASS

L7:0

D15:0

PROG

CLOCK

PDSP

16488

8X4

WINDOW

RES

PC1

SNG

MST

R/W

OEN

O/C

BIN

R/W

ADDR

DATA

STROBE

HOST CPU

ADDRESS

DECODE

ODD
FIELD

FIELD

DELAY

REPLY

READ

REG

OEN

GND

O/C

CLOCK

Figure 12. 8 Bit Dual Device Systems

VCC

PDSP

16488A

8X4

WINDOW

PDSP

16488A

8X4

WINDOW

PDSP

16488A

8X4

WINDOW

PDSP

16488A

8X4

WINDOW

PDSP16488A MA

EPROM

DELAYED
SYNC

CLOCK

BIN

OVERFLOW

DATA OUT

SYNC

O/C

MSB

O/C

16 BIT
PIXEL
DATA

LSB

RESET

O/P ENABLE

PC0

X15

X14:8

X7:0

IP7:0

HRES

BYPASS

L7:0

D15:0

PROG

PDSP

16488

8X4

WINDOW

GND

RES

PC1

CS0

SNG

MST

R/W

GND

DELOP

O/C

GND

CS1

PC0

X15

X14:8

X7:0

IP7:0

HRES

BYPASS

L7:0

D15:0

PROG

CLOCK

PDSP

16488

8X4

WINDOW

RES

PC1

SNG

MST

R/W

OEN

O/C

GND

O/C

BIN

MSB

OEN

GND

O/C

DELAYED
SYNC

CLOCK

BIN

OVERFLOW

DATA OUT

SYNC

16 BIT
PIXEL
DATA

RESET

O/P ENABLE

PC0

X15

X14:8

X7:0

IP7:0

HRES

BYPASS

L7:0

D15:0

PROG

CLOCK

PDSP

16488

8X4

WINDOW

O/C

RES

PC1

SNG

MST

R/W

GND

DELOP

O/C

PC0

X15

X14:8

X7:0

IP7:0

HRES

BYPASS

L7:0

D15:0

PROG

CLOCK

PDSP

16488

8X4

WINDOW

RES

PC1

SNG

MST

R/W

OEN

O/C

BIN

R/W

ADDR

DATA

STROBE

HOST CPU

ADDRESS

DECODE

ODD
FIELD

FIELD

DELAY

REPLY

READ

REG

OEN

GND

O/C

MSB

LSB

D7;0

CLOCK

Figure 13. Dual Device 16 Bit Systems.

VCC

PDSP

16488A

8X4

WINDOW

PDSP

16488A

8X4

WINDOW

PDSP

16488A

8X4

WINDOW

PDSP

16488A

8X4

WINDOW

PDSP16488A MA

Figure 18. Nine Device Non Interlaced System.

GND

DATA IN

O/C

SYNC

BIN

O/P

ENABLE

DATA
OUT

GND

O/C

GND

EPROM

UPPER

ADDR

DATA

CE1

CE8

ALS

138

CE1

CE7

CE8

O/C

CE7

EPROM

UPPER
ADDRESS

ADDR

DATA

RESET

DELAYED SYNC

PDSP
16488

PROG

R/W

RES

PC1

BYPASS

HRES

IP7:0

X15

X14:8

X7:0

BIN

D15:0

CLOCK

PDSP
16488

PROG

R/W

RES

PC1

BYPASS

HRES

IP7:0

X15

X14:8

X7:0

BIN

D15:0

CLOCK

PDSP
16488

PROG

R/W

RES

PC1

BYPASS

HRES

IP7:0

X15

X14:8

X7:0

BIN

D15:0

CLOCK

PDSP
16488

PROG

R/W

RES

PC1

BYPASS

HRES

IP7:0

X15

X14:8

X7:0

BIN

D15:0

CLOCK

PDSP
16488

PROG

R/W

RES

PC1

BYPASS

HRES

IP7:0

X15

X14:8

X7:0

BIN

D15:0

CLOCK

PDSP
16488

PROG

R/W

RES

PC1

BYPASS

HRES

IP7:0

X15

X14:8

X7:0

BIN

D15:0

CLOCK

PDSP
16488

PROG

R/W

PC1

BYPASS

HRES

IP7:0

X15

X14:8

X7:0

D15:0

CLOCK

PDSP
16488

PROG

R/W

RES

PC1

BYPASS

HRES

IP7:0

X15

X14:8

X7:0

BIN

D15:0

CLOCK

PDSP
16488

PROG

R/W

RES

PC1

BYPASS

HRES

IP7:0

X15

X14:8

X7:0

BIN

D15:0

CLOCK

OVERFLOW

L7:0

PC0

L7:0

PC0

L7:0

PC0

L7:0

PC0

L7:0

PC0

L7:0

PC0

CS0

CS1

CS2

RES

CS3

MST

GND

OEN

GND

OEN

GND

OEN

GND

OEN

GND

OEN

GND

OEN

GND

OEN

GND

OEN

DELOP

GND

OEN

4 CLK

DELAYS

4 CLK

DELAYS

VCC

PDSP

16488A

PDSP

16488A

PDSP

16488A

PDSP

16488A

PDSP

16488A

PDSP

16488A

PDSP

16488A

PDSP

16488A

PDSP

16488A

PDSP16488A MA

Pin No.

34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66

Volts.

N/C
N/C

N/C

GND

N/C
N/C

GND

N/C
N/C

N/C

GND

GND
GND

N/C
N/C
N/C
N/C

GND

N/C
N/C
N/C
N/C
N/C
N/C

Volts.

N/C
N/C
N/C
N/C
N/C
N/C

GND

N/C
N/C
N/C
N/C
N/C

V1
V1
V1

N/C

N/C
N/C
N/C

GND
GND

N/C
N/C
N/C
N/C
N/C

GND
GND

N/C

Volts

N/C

GND
GND
GND

N/C

GND

V1
V1

GND

V1
V1
V1
V1

N/C

GND
GND
GND
GND
GND

GND

GND
GND
GND

N/C

GND

N/C

Pin No.

100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132

Volts.

N/C

N/C
N/C
N/C
N/C
N/C

GND

N/C

GND

V1
V1

N/C
N/C
N/C

GND

N/C
N/C

GND
GND

N/C

N/C
N/C
N/C
N/C

GND

N/C
N/C
N/C
N/C
N/C

Pin No.

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33

Pin No.

67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

Part No:

PDSP16488 Single Chip 2D Convolver with Integral Line Delays

Package Type:

GC132

VDD max = +5.0V = V1

N/C = not connected

Figure 19. Life Test/Burn-in connections

NOTE: PDA is 5% and based on groups 1 and 7

ORDERING INFORMATION

PDSP16488A MA GCPR (QFP Package - Non-compliant to MIL-STD-883 Class B)
PDSP16488A MA ACBR (PGA Package - Non-compliant to MIL-STD-883 Class B)

TECHNICAL DOCUMENTATION - NOT FOR RESALE

World Headquarters - Canada

Tel: +1 (613) 592 2122

Fax: +1 (613) 592 6909

North America

Asia/Pacific

Europe, Middle East,

Tel: +1 (770) 486 0194

Tel: +65 333 6193

and Africa (EMEA)

Fax: +1 (770) 631 8213

Fax: +65 333 6192

Tel: +44 (0) 1793 518528

Fax: +44 (0) 1793 518581

http://www.mitelsemi.com

Information relating to products and services furnished herein by Mitel Corporation or its subsidiaries (collectively "Mitel") is believed to be reliable. However, Mitel assumes no
liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of
patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or
service conveys any license, either express or implied, under patents or other intellectual property rights owned by Mitel or licensed from third parties by Mitel, whatsoever.
Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Mitel, or non-Mitel furnished goods or services may infringe patents or
other intellectual property rights owned by Mitel.

This publication is issued to provide information only and (unless agreed by Mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or
contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this
publication are subject to change by Mitel without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or
service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific
piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or
data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in
any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Mitel's
conditions of sale which are available on request.

Электронный компонент: PDSP16488AMAACBR