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Электронный компонент: SL6140MPTC

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SL6140
SL6140
400MHz Wideband AGC Amplifier
Features
G
400MHz Bandwidth (R
L
=50
)
G
High voltage Gain 45dB (R
L
=1k
)
G
70dB Gain Control Range
G
High Output Level at Low Gain
G
Surface Mount Plastic Package
G
Low Cost
Applications
G
RF/IF Amplifier
G
High Gain Mixers
G
Video Amplifiers
Description
The SL6140 is an integrated broadband AGC amplifier,
designed on an advanced bipolar process. The
amplifier provides over 15dB of linear gain into 50
at
400MHz. Gain control is also provided with over 70dB
of dynamic range. The SL6140 offers over 45dB of
voltage gain with an R
L
of 1k
.
DS2159
Issue no 5.0
July 1999
Ordering Information
SL6140/NA/MP
Industrial temperature range
miniature plastic package
SL6140/NA/MPTC Tape and Reel
Figure 1 Typical Application
10n
10n
10n
10n
1.0 F
+VCC
2
6
5
4
3
7
+VCC
OUTPUT
OUTPUT
RL
RL
RAGC
AGC
INPUT
INPUT
SL6140
8
1
The SL6140 (Figure 3) is a high gain amplifier with an
AGC control capable of reducing the gain of the amplifier
by over 70dB. The gain is adjustable by applying a
voltage to the AGC input via an external resistor (R
AGC
),
the value of which adjusts the curve of gain reduction
versus control voltage (see Figure 4). As the output
stage of the amplifier is an open collector the maximum
voltage gain is determined by R
L
. With load resistance
of 1k
the single ended voltage gain is 45dB and with a
load resistance of 50
the voltage gain is 15dB (20log
10
V
OUT
/V
IN
). Another parameter that depends on the load
resistance is the bandwidth: 25MHz for R
L
= 1k
, as
compared with 400MHz for R
L
= 50
. R
L
is chosen to
give either the required bandwidth or voltage gain for the
circuit.
Figure 7 through to 10 show the typical S parameters for
the device. Figures 11 and 12 show the typical variation
in 3rd order intercept performance with AGC.
In any application, the substrate should be connected to
the most negative point in the circuit, usually to the same
point as pin 3.
2
SL6140
Figure 2 Pin Connections Diagram (top view)
MP8
Electrical Characteristics
T
amb
= 25
C, V
CC
= 12V +5%, V
IN
= 1mV
RMS
, Frequency = 6MHz, Load (R
L
) = 10KOHms, R
AGC
= 22KOHm
These characteristics are guaranteed over the following conditions (unless otherwise stated)
1
8
2
7
3
6
4
5
OUTPUT
INPUT
+VCC
GROUND
INPUT
AGC INPUT
OUTPUT
GROUND
5,6,7
5,6
(sum)
5,6
2
5,6
5,6
5,6
5,6
5,6
5,6
19
7
1.0
75
45
55
15
25
400
3.5
3.5
5
mA
mA
mA
dB
dB
dB
dB
MHz
V p-p
V p-p
dB
Supply current
Output stage current
Output current matching
(magnitude of difference of output
currents)
AGC range
Voltage gain (single ended)
Bandwidth (-3dB)
Maximum output level (single
ended)
0dB AGC
-30dB AGC
Noise figure
5
60
40
23
9
No input signal
No input signal
See Figure 4 & Note 1
(VAGC = 0V to 10V)
R
L
= 1k
See Figure 5 & Note 1
Tuned input and output
R
L
= 50
RL = 1k
See Figure 5
RL = 50
Note 1
R
L
= 1k
. Note 1
Test CCT Figure 13
Max
Typ
Min
Pin
Units
Characteristic
Conditions
Value
Note. 1
Guaranteed but not tested.
Absolute Maximum Ratings
Supply voltage, V
CC
+18V
Input voltage (differential)
+5V
AGC supply
V
CC
Storage temperature
-55
C to +150C
Operating temperature range
SL6140
MP
-40
C to +85C
at 200mW
Chip operating temperature
SL6140
MP
+150
C
Thermal Resistance
Chip-to-ambient
SL6140
MP
163
C/W
Chip-to-case
SL6140
MP
57
C/W
3
SL6140
Figure 3 Full Circuit Diagram of SL6140
2.1k
1.1k
1.1k
5k
5k
5.6k
1.4k
7k
12.1k
470
X 2
1.9k
200
2.8k
2.8k
200
200
180
470
470
180
70
2k
66
45
1
8
2
3
7
6
4
5
SUBSTRATE
GROUND
OUTPUT
OUTPUT
VCC
AGC
I/P
INPUT
INPUT
4
SL6140
Figure 4 Gain Reduction v. AGC Voltage
1
2
3
4
5
6
7
8
9
10
0
0
10
20
30
40
50
60
70
G
A
I
N
R
E
D
U
C
T
I
O
N
(dB)
AGC VOLTAGE
RAGC=5.6k
RAGC=22k
Figure 5 Max Differential O/P Voltage v. Gain Reduction
7
8
6
5
4
3
2
1
0
10
20
30
40
50
0
GAIN REDUCTION (dB)
D
I
F
F
E
R
E
N
T
I
A
L
O
U
T
P
U
T
(V p-p)
1MHzSINEWAVE
5
SL6140
Figure 6 Voltage Gain v. Frequency
Figure 7 Input Impedance 50
System
0.1
10
100
1000
40
30
50
20
0
10
dB
G
A
I
N
FREQUENCY (MHz)
RL=50
RL=1k
6
SL6140
Figure 9 Reverse Transmission Coefficient S
12
SL6140
Figure 8 Output Impedance 50
System
7
SL6140
Figure 11 3rd Order Intercept Point Against Gain Reduction At 250.0MHz and 254.0MHz
Figure 10 Forward Transmission Coefficient S
12
SL6140
8
SL6140
Figure 12 3rd Order Intercept Point Against Gain Reduction At 100.0MHz and 104.0MHz
Figure 13 50MHz Noise Figure Test Circuit
1nF
1
8
L2
O/P
4
5
6
L1
1nF
3
7
2
+12V
VARIABLE CAPS 3-25pF
L1 7 TURNS # 18 SWG 8mm DIA 16mm LONG
L2 6 TURNS # 16 SWG 14mm DIA 19mm LONG
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