The SP5502 is a single-chip frequency synthesiser designed
for TV tuning systems. Control data is entered in the standard
I
2
C BUS format. The SP5502 has four programmable I
2
C BUS
addresses, which allows two or more synthesisers to be used
in a system.
The device is available in two variants: the SP5502F in 14-
lead miniature plastic package (MP14) and the SP5502S in 16-
lead miniature plastic package (MP16). See Features below for
functional differences between the devices.
FEATURES
s
Complete 13GHz Single Chip System
s
Programmable via the I
2
C BUS
s
Low Power Consumption (240mW Typ.)
s
Low Radiation
s
Phase Lock Detector
s
Varactor Drive Amp Disable
s
5 20mA Controllable Outputs (SP5502S)
s
3 20mA Controllable Outputs (SP5502F)
s
Variable I
2
C BUS Address for Multi-Tuner Applications
s
ESD Protection
*
*
Normal ESD handling precautions should be observed.
APPLICATIONS
s
Cable Tuning Systems
s
VCRs
Fig. 1 Pin connections top view
ORDERING INFORMATION
SP5502F KG MPAS (14-lead miniature plastic package)
SP5502S KG MPAS (16-lead miniature plastic package)
Fig. 2 Block diagram of SP5502S. (Ports P0 and P4 not present on SP5502F)
SP5502
1.3GHz I
2
C BUS 4-Address Synthesiser
Supersedes version in April 1994 Consumer IC Handbook, HB3120 - 2.0
DS3031 - 5.0 January 1997
2
SP5502
ELECTRICAL CHARACTERISTICS
T
AMB
= 10C to 80C, V
CC
= 45V to 55V. All pin references are to the SP5502S (MP16 package).
These Characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature
and supply voltage ranges unless otherwise stated. Reference frequency 4MHz unless otherwise stated.
Supply current
Prescaler input voltage
Prescaler input voltage
Prescaler input impedance
Prescaler input capacitance
SDA, SCL
Input high voltage
Input low voltage
Input high current
Input low current
Leakage current
SDA
Output voltage
Charge pump current low
Charge pump current high
Charge pump output leakage current
Charge pump drive output current
Charge pump amplifier gain
Recommended crystal series resistance
Crystal oscillator drive level
Crystal oscillator negative resistance
Output Ports
Sink current
Leakage current
Input Port
P3 input current high
P3 input current low
Typ.
Value
Conditions
Characteristic
Pin
12
13,14
13,14
4,5
4,5
4,5
4,5
4,5
4
1
1
1
16
2
6,7,9-11
6,7,9-11
8
8
125
30
3
0
500
10
750
20
48
50
2
50
170
6400
40
60
300
300
V
CC
15
10
10
10
04
5
200
10
1
05
Units
Min.
Max.
mA
mVrms
mVrms
pF
V
V
A
A
A
V
A
A
nA
mV p-p
mA
A
mA
mA
V
CC
= 5V
80MHz to 1GHz
13GHz, see Fig. 5
Input voltage = V
CC
Input voltage = 0V
When V
CC
= 0V
Sink current = 3mA
Byte 4, bit 2 = 0, pin 1 = 2V
Byte 4, bit 2 = 1, pin 1 = 2V
Byte 4, bit 4 = 1, pin 1 = 2V
V pin 16 = 07V
Parallel resonant crystal (note 2)
V
OUT
= 07V (see note 1)
V
OUT
= 132V
V pin 8 = V
CC
V pin 8 = 0V
NOTES
1. Source impedance between all output ports and ground is approximately 5
. This should be taken into account when calculating output port
saturation voltages.
2. The maximum resistance quoted refers to all conditions, including start-up.
FUNCTIONAL DESCRIPTION (Except where
otherwise indicated, `SP5502' refers to both
variants)
The SP5502 is programmed from an I
2
C BUS. Data and
Clock are fed in on the SDA and SCL lines respectively as
defined by the I
2
C Bus format. The synthesiser can either
accept new data (write mode) or send data (read mode). The
Tables in Fig. 3 illustrate the format of the data. The device
can be programmed to respond to several addresses, which
enables the use of more than one synthesiser in an I
2
C Bus
system. Table 3 shows how the address is selected by
applying a voltage to P3. The address input is shown in Fig.
6. The LSB of the address Byte (R/W) sets the device into read
mode if it is high and write mode if it is low. When the SP5502
receives a correct address Byte it pulls the SDA line low
during the acknowledge period and during following acknowl-
edge periods after further data Bytes are programmed. When
the SP5502 is programmed into the read mode the controlling
device accepting the data must pull down the SDA line during
the following acknowledge period to read another status Byte.
WRITE MODE (FREQUENCY SYNTHESIS)
When the device is in the write mode Bytes 2 3 select the
synthesised frequency while Bytes 4 5 select the output port
states and charge pump information.
Once the correct address is received and acknowledged,
the first Bit of the next Byte determines whether that Byte is
interpreted as Byte 2 or 4, a logic 0 for frequency information
and a logic 1 for charge pump and output port information.
Additional data Bytes can be entered without the need to re-
address the device until an I
2
C stop condition is recognised.
This allows a smooth frequency sweep for fine tuning or AFC
purposes.
If the transmission of data is stopped mid-byte (i.e., by
another device on the bus) then the previously programmed
byte is maintained.
Frequency data from Bytes 2 and 3 is stored in a 15-bit shift
register and is used to control the division ratio of the 15-bit
programmable divider which is preceded by a divide-by-8
prescaler and amplifier to give excellent sensitivity at the local
oscillator input; see Fig 5. The input impedance is shown in Fig
7.
3
SP5502
Table 1 Write data format (MSB transmitted first)
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Address
Programmable divider
Programmable divider
Charge pump and test bits
I/O port control bits
1
2
14
2
6
CP
X
0
2
13
2
5
T1
X
0
2
12
2
4
T0
P4
*
0
2
11
2
3
1
X
MA0
2
9
2
1
1
P1
MA1
2
10
2
2
1
P2
A
A
A
A
A
MSB
1
0
2
7
1
P7
LSB
0
2
8
2
0
OS
P0
*
Table 2 Read data format
Byte 1
Byte 2
Address
Status byte
1
FL
0
N
0
N
0
N
MA0
N
MA1
N
A
A
1
POR
1
N
Table 3 Address selection
MA0
0
1
0
1
MA1
0
0
1
1
Voltage input to P3
0V to 01V
CC
Open circuit
04V
CC
to 06V
CC
09V
CC
to V
CC
A
: Acknowledge bit
MA1, MA0
: Variable address bits (see Table 3)
CP
: Charge Pump current select
T1
: Test mode selection
T0
: Charge pump disable
OS
: Varactor drive Output disable Switch
P7, P4
*
, P2, P1, P0
*
:
Control output port states
POR
: Power On Reset indicator
FL
: Phase lock detect flag
X
: Don't care
N
: Not valid
NOTES
Programmed by connecting a 15k
resistor between Address Select Port P3 and V
CC
.
*
Don't care condition on SP5502F.
Fig. 3 Data formats
The programmed frequency can be calculated by multiply-
ing the programmed division ratio by 8 times the comparison
frequency F
COMP
.
When frequency data is entered, the phase comparator,
via the charge pump and varactor drive amplifier, adjusts the
local oscillator control voltage until the output of the program-
mable divider is frequency and phase locked to the comparison
frequency.
The reference frequency may be generated by an external
source capacitively coupled into pin 2 or provided by an on-
chip 4MHz crystal controlled oscillator.
Note that the comparison frequency is 78125kHz when a
4MHz reference is used.
Bit 2 of Byte 4 of the programming data (CP) controls the
current in the charge pump circuit, a logic 1 for 170A and
a logic 0 for 50A, allowing compensation for the variable
tuning slope of the tuner and also to enable fast channel
changes over the full band. Bit 4 of Byte 4 (T0) disables the
charge pump if set to a logic 1. Bit 8 of Byte 4 (OS) switches
the charge pump drive amplifier's output off when it is set to
a logic 1. Bit 3 of Byte 4 (T1) selects a test mode where the
phase comparator inputs are available on P2 and P7, a logic
1 connects F
COMP
to P2 and F
DIV
to P7.
Byte 5 programs the output ports P0-P2, P4 and P7 on the
SP5502S (P1, P2 and P7 only on SP5502F), a logic 0 for a
high impedance output, logic 1 for low impedance (on).
READ MODE
When the device is in the read mode the status data read from
the device on the SDA line takes the form shown in Table 2. Bit
1 (POR) is the power supply to the device has dropped below a
nominal 3V and the programmed information lost (e.g., when the
device is initially turned on). The POR is set to 0 when the read
sequence is terminated by a stop command. The outputs are all
set to high impedance when the device is initially powered up. Bit
2 (FL) indicates whether the device is phase locked, a logic 1 is
present if the device is locked and a logic 0 if the device is
unlocked.
4
SP5502
APPLICATION
A typical application is shown in Fig. 4. All input/output interface circuits are shown in Fig. 6.
Fig. 4 Typical application
Fig. 5 Typical input sensitivity
5
SP5502
Fig. 6 SP5502 input/output interface circuits
6
SP5502
Fig. 7 Typical input impedance
ABSOLUTE MAXIMUM RATINGS
All voltages are referred to V
EE
= 0V
Supply voltage
RF input voltage
Port voltage
Total port output current
RF input DC offset
Charge pump DC offset
Drive output DC offset
Crystal oscillator DC offset
SDA, SCL input voltage
Storage temperature
Junction temperature
MP16 thermal resistance, chip-to-ambient
MP16 thermal resistance, chip-to-case
MP14 thermal resistance, chip-to-ambient
MP14 thermal resistance, chip-to-case
Power consumption at 55V
Conditions
Parameter
Units
7
25
14
6
V
CC
03
50
V
CC
03
V
CC
03
V
CC
03
V
CC
03
V
CC
03
55
150
150
111
41
123
45
363
Value
Max.
Min.
03
03
03
03
03
03
03
03
03
03
55
Pin
SP5502F
SP5502S
12
13,14
6,7, 9-11
6,7, 9-11
8
6,7, 9-11
13,14
1
16
2
4,5
10
11,12
6,8, 9
6,8, 9
7
6,8, 9
11,12
1
14
2
4,5
V
V p-p
V
V
V
mA
V
V
V
V
V
V
C
C
C/W
C/W
C/W
C/W
mW
Port in off state
Port in on state
With V
CC
applied
V
CC
not applied
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