The SP5658 is a single chip frequency synthesiser
designed for tuning systems up to 2.7GHz.
The RF preamplifer contains a divide by two prescaler
which can be disabled for applications up to 2GHz so enabling
a step size equal to the comparison frequency up to 2GHz and
twice the comparison frequency up to 2.7GHz.
Comparison frequencies are obtained either from a crystal
controlled onchip oscillator or from an external source.
The device contains two switching ports, in the 14 pin
version and four in the 16 pin, together with an ``inlock" flag
output. The device also contains a varactor line disable and
charge pump disable facility.
FEATURES
s
Complete 2.7GHz single chip system
s
Optimised for low phase noise
s
Selectable divide by two prescaler
s
Selectable reference division ratio
s
Charge pump disable
s
Varactor line disable
s
`Inlock' flag
s
Two switching ports in 14 pin version
s
Four switching ports in 16 pin version
s
Pin compatible with SP5659 I 2 C bus low
phase noise synthesiserPP
s
ESD protection (Normal ESD handling procedures
should be observed)
APPLICATIONS
s
SAT, TV, VCR and Cable tuning systems
s
Communications systems
Fig. 1 Pin connections top view
1
14
1
16
1
16
CRYSTAL
CHARGE PUMP
DISABLE
ENABLE
DATA
CLOCK
PORT P1/OC
DRIVE
V
EE
RF INPUT
RF INPUT
V
CC
LOCK
PORT P0/OP
SP5658S
SP5658F
MP14
MP16
CRYSTAL
CHARGE PUMP
DISABLE
ENABLE
DATA
CLOCK
PORT P3
PORT P2
DRIVE
V
EE
RF INPUT
RF INPUT
V
CC
LOCK
PORT P0/OP
PORT P1/OC
ORDERING INFORMATION
SP5658F/KG/MP1S (Tubes, 14 lead SO)
SP5658S/KG/MP2S (Tubes, 16 lead SO)
SP5658F/KG/MP1T (Tape and Mounted)
SP5658S/KG/MP2T (Tape and Mounted)
SP5658
2.7GHz 3-Wire Bus Controlled Frequency Synthesiser
Advance Information
Supersedes October 1996 Media IC Handbook HB3923-2
DS4064 - 4.1 March 1998
2
SP5658
RF
13 BIT
COUNT
4 BIT
COUNT
18 BIT LATCH
3 BIT LATCH
4 BIT
LATCH AND
PORT
INTERFACE
DATA
INTERFACE
CRYSTAL
PUMP
DRIVE
DISABLE
CLOCK
ENABLE
DATA
P2 P1/0C
CHARGE
INPUTS
13
14
3
4
5
6
DISABLE
PROGRAMMABLE
DIVIDER
CHARGE
PUMP
(R0,R1,R2)
1 BIT
LATCH
REFERENCE
DIVIDER
See Table 1
PHASE
COMP
1 BIT
LATCH
1 BIT
LATCH
FLOCK
OSC
2
1
16
OS
V
EE
15
12 V
CC
11
10
7
CO
F
pd
F
comp
- 2/1
8
9
P3
P0/OP
-16/17
LOCK
T0
DE
:
:
Fig. 2 SP5658S block diagram
3
SP5658
ELECTRICAL CHARACTERISTICS
T amb = 20
C to + 80
C, V
CC
= + 4.5V to + 5.5V. Reference frequency = 4MHz. These characteristics are guaranteed by
either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise
stated.
Value
Characteristics
Pin
Units
Conditions
(SP5658S)
Supply current, I
CC
12
59
74
mA
V
CC
=5V Prescaler enabled, DE=1
52
65
mA
V
CC
=5V Prescaler disabled, DE=0
RF input voltage
13, 14
40
300
mV
rms
300MHz to 2.7GHz Prescaler
enabled, DE=1, See Fig. 5b
13,14
100
300
mV
rms
80MHz Prescaler enabled,
DE=1, See Fig. 5b.
13, 14
40
300
mV
rms
100MHz to 2.0GHz Prescaler
disabled, DE=0, See Fig. 5a
13,14
50
300
mV
rms
80MHz Prescaler disabled,
DE=0, See Fig. 5a.
RF input impedance
13, 14
50
Refer to Fig. 4
RF input capacitance
13, 14
2
pF
Refer to Fig. 4
Data, Clock, Enable & Disable
3,4,5,6
Input high voltage
3
V
CC
V
Input low voltage
0
0.7
V
Input high current
10
A
Input voltage = V
CC
Input low current
10
A
Input voltage = V
EE
Clock Rate
6
500
kHz
Clock data & enable input
4,5,6
0.4
V
hysteresis
Min
Typ
Max
4
SP5658
ELECTRICAL CHARACTERISTICS
T amb = 20
C to + 80
C, V
CC
= + 4.5V to + 5.5V. Reference frequency = 4MHz. These characteristics are guaranteed
by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless
otherwise stated.
Characteristics
Pin
Value
Units
Conditions
(SP5658S)
Bus Timing
4,5,6
Data set up, t
SU
300
ns
See Fig. 3
Data hold, t
HD
600
ns
See Fig. 3
Enable set up, t
ES
300
ns
See Fig. 3
Enable hold, t
EH
600
ns
See Fig. 3
Clock to enable, t
CE
300
ns
See Fig. 3
Charge pump output current
1
See Table 3, V
PIN1
= 2V
Charge pump output leakage
1
3
10
nA
V
PIN1
= 2V
Charge pump drive output
16
1
mA
V
PIN16
= 0.7V
current
Oscillator temperature stability
2
2
ppm/
C
Oscillator supply voltage
2
2
ppm/V
stability
External reference input
2
2
20
MHz
AC coupled sinewave
frequency
External reference input
2
200
500
mV
PP
AC coupled sinewave
amplitude
Crystal frequency
2
4
12
MHz
Crystal oscillator drive level
2
45
mV
PP
Recommended crystal series
100
200
Applies to 4MHz crystal only.
resistance
``Parallel resonant" crystal. Figure
quoted is under all conditions
including start up.
Crystal oscillator negative
2
400
Includes temperature and process
resistance
tolerances.
Comparison frequency
2
MHz
Phase noise at phase detector
142
dBC/
6kHz loop BW, phase comparator
Hz
freq 250kHz. Figure measured @
1kHz offset, DSB (within loop band
width).
RF division ratio
240
131071
Prescaler disabled, DE=0
480
262142
Prescaler enabled, DE=1
Reference division ratio
See Table 1
Output ports P0P3 #
7,8,9,10
Sink current
10
mA
V
PORT
=0.7V
Leakage current
10
A
V
PORT
=13.2V
Lock output
11
Sink current
1
mA
V
LOCK
=0.7V, `out of lock'
Leakage current
10
A
`in lock'
# Ports P2 and P3 are not available on the SP5658F.
Min
Typ
Max
5
SP5658
The output of the preamplifier is fed to the 2/1 selectable
prescaler and then to the 17 bit fully programmable divider,
which is of MN+A architecture. The M counter is 13 bit and the
A counter 4. If bit DE is set to a 0 the prescaler is disabled; Note
that the control function DE cannot be used dynamically.
The output of the programmable divider is fed to the phase
comparator where it is compared in both phase and frequency
domain with the comparison frequency. This frequency is
derived either from the on board crystal controlled oscillator or
from an external source. In both cases the reference
frequency is divided down to the comparison frequency by the
reference divider which is programmable into 1 of 8 ratios as
described in Table 1.
The output of the phase comparator feeds the charge
pump and loop amplifier section, which when used with an
external high voltage transistor and loop filter integrates the
current pulses into the varactor line voltage. The charge pump
can be disabled to a high impedance state by the DISABLE
input. The varactor drive output can also be disabled by the OS
bit within the data word, so switching the external transistor
`OFF' and allowing an external voltage to be written to the
varactor line for tuner alignment purposes.
The phase comparator also drives the lock detect circuit
which generates a lock flag. `Inlock' is indicated by a high
impedance state on the lock output.
The programmable divider output divided by 2, F
pd
/2 and
the comparison frequency, F
comp
can be switched to ports P0
and P1 respectively by switching the device into test mode.
The test modes are described in Table 2.
ABSOLUTE MAXIMUM RATINGS
All voltages are referred to V EE at 0V
Characteristics
Pin
Min
Max
Units
Conditions
(SP5658S)
Supply voltage, V
CC
12
0.3
7
V
RF input voltage
13, 14
2.5
V
pp
AC coupled as per application
RF input DC offset
13, 14
0.3
V
CC
+0.3
V
Port voltage
7 10
0.3
14
V
Port in off state
7 10
0.3
6
V
Port in on state
Total port current
7 10
50
mA
Lock output DC offset
11
0.3
V
CC
+0.3
V
Charge pump DC offset
1
0.3
V
CC
+0.3
V
Drive DC offset
16
0.3
V
CC
+0.3
V
Crystal DC offset
2
0.3
V
CC
+0.3
V
Data, Clock, Enable & Disable DC
3 6
0.3
V
CC
+0.3
V
offset
Storage temperature
55
+125
C
Junction temperature
150
C
MP14 Thermal Resistance
Chip to ambient 123
C/W
Chip to case 45
C/W
MP16 Thermal Resistance
Chip to ambient
111
C/W
Chip to case
41
C/W
Power consumption at V
CC
=5.5V
407
mW
All ports off, prescaler enabled
ESD protection
ALL
2
kV
MILSTD 883 TM 3015
FUNCTIONAL DESCRIPTION
The SP5658 contains all the elements necessary, with the
exception of a frequency reference, loop filter and external
high voltage transistor, to control a varicap tuned local
oscillator, so forming a complete PLL frequency synthesised
source. The device allows for operation with a high
comparison frequency and is fabricated in high speed logic,
which enables the generation of a loop with good phase noise
performance. The RF preamplifier contains a selectable
divide by two for operation above 2.0GHz. Up to 2GHz the RF
input interfaces directly with the programmable divider, so
eliminating degradation in phase noise due to the prescaler
action. The block diagram is shown in Fig.2.
The SP5658 is controlled by a standard 3wire bus
comprising data, clock and enable inputs. The programming
word for the 16 pin variant contains 28 bits, four of which are
used for port selection, 18 to set the programmable divider
ratio and enable/disable the prescaler, bit DE, three bits to
select the reference division ratio, bits R0R2, one bit to set
charge pump current, bit C0, and the remaining two bits to
access test modes, bit T0, and to disable the varactor drive,
bit OS. The data word for 14 pin variant is identical to 16 pin
except 26 bits only are required, two of which are used for port
selection. The programming format is shown in Fig. 3.
The clock input is disabled by an enable low signal, data
is therefore only clocked into the internal shift registers during
an enable high and is loaded into the controlling buffers by an
enable high to low transition. This load is also synchronised
with the programmable divider so giving smooth fine tuning.
The RF signal is fed to an internal preamplifier, which
provides gain and reverse isolation from the divider signals.
6
SP5658
Fig. 3 Data format and timing
R2
R1
R0
RATIO
Comparison Frequency with a 4MHz
external reference.
0
0
0
2
2MHz
0
0
1
4
1MHz
0
1
0
8
500kHz
0
1
1
16
250kHz
1
0
0
32
125kHz
1
0
1
64
62.5kHz
1
1
0
128
31.25kHz
1
1
1
256
15.625kHz
Table 1 Reference division ratios
CLOCK
ENABLE
16 PIN VARIANT
DATA
FREQUENCY DATA
2
27
2
26
2
25
2
24
2
23
2
22
2
21
2
20
2
19
2
18
2
17
2
16
2
0
P3
P2
P1
P0
TO OS CO R2
R1
R0 DE
LSB
14 PIN VARIANT
DATA
FREQUENCY DATA
2
25
2
24
2
23
2
22
2
21
2
20
2
19
2
18
2
17
2
16
2
0
P1
P0
TO OS CO R2
R1
R0 DE
LSB
CLOCK
ENABLE
DATA
t
ES
=Enable set up time
=Data set up time
=Data hold time
=Clocktoenable time
=Enable hold time
t
SU
t
HD
t
CE
t
EH
MSB IS TRANSMITTED
FIRST
t
SU
t
HD
3V
3V
0.7V
0.7V
t
CE
t
ES
t
EH
3V
0.7V
2
16
to 2
0
t : Programmable divider ratio control bits
R2
R1
R0
,
,
t : Reference divider ratio control bits (see Table1)
P3, P2, P1, P0
t : Port control bits
CO
t : Charge Pump current select (see Table 3)
OS
t : Drive output disable switch
T0
t : Test mode enable (see Table 2)
MSB
MSB
DE
: - 2 Prescaler (Enable = 1, Disable = 0)
:
7
SP5658
TO
OS
DIS
P0/OP
P1/0C
FUNCTIONAL DESCRIPTION
0
0
0
#
#
NORMAL OPERATION
0
0
1
#
#
CHARGE PUMP DISABLE
1
0
0
F pd/2
F comp
NORMAL OPERATION
0
1
0
#
#
VARACTOR LINE DISABLE
0
1
1
#
#
CHARGE PUMP AND
VARACTOR LINE DISABLE
1
X
1
NOT PERMITTED
# CONTROLLED BY BITS P0 AND P1 WITHIN DATA WORD
Table 2 Test modes
C0
CURRENT IN mA
MIN
TYP
MAX
0
0.23
0.3
0.37
1
0.68
0.9
1.12
Table 3 Charge pump current
Fig. 4 Typical input impedance
Fig. 5a Typical input sensitivity (Prescaler disabled, DE=0) Fig. 5b Typical input sensitivity (Prescaler enabled, DE=1)
0.5
0.2
1
0
+j0.2
+j0.5
+j1
+j2
+j5
2
5
j5
j2
j1
j0.5
j0.2
FREQUENCY MARKERS AT 100MHz,
S
11
:Z
0
= 50
X
X
X
X
NORMALISED TO 50
500MHz, 1GHz AND 2.7GHz
300
100
40
10
1000
2000
3000
FREQUENCY (MHz)
3500
OPERA TING
WINDOW
1000
2000
2700
3000
FREQUENCY (MHz)
3500
300
OPERA TING
WINDOW
300
100
40
10
VIN
(mV RMS
INTO 50 )
VIN
(mV RMS
INTO 50 )
100
80
80
50
8
SP5658
DOUBLE CONVERSION TUNER SYSTEMS
The high 2.7GHz maximum operating frequency and
excellent noise characteristics of the SP5658 enables the
construction of double conversion high IF tuners.
A typical system shown in Fig.7 will use the SP5658 as the
first LO control for full band upconversion to an IF of greater
than 1GHz. The wide range of reference division ratios allows
the SP5658 to be used both for the up converter LO with a high
phase comparator frequency (hence low phase noise) and the
down converter which utilises the device in a lower
comparison frequency mode (which offers a fine step size).
50900MHz
1.6GHz
38.9MHz
16502700MHz
SP5658
SP5658
First LO
Second LO
CONTROL
MICRO
15nF
68pF
+30V
+5V
22k
16k
47k
+12V
2n2
2N3904
1n
1n
10n
P1
TUNER
OSCILLATOR
OUTPUT
SP5658F
13k3
P0
DIS
LOCK
CLOCK
DATA
ENABLE
REF 10n
18pF
4MHz
Optional application utilising
onboard crystal controlled
oscillator
1
14
2
3
4
5
6
7
13
12
11
10
8
9
APPLICATION NOTES
A generic set of application notes AN168 for designing
with synthesisers such as the SP5658 has been written. This
covers aspects such as loop filter design and decoupling. This
application note is also featured in the Media IC Handbook.
A generic test/demo board has been produced which can
be used for the SP5658. A circuit diagram and layout for the
board is shown in Figs. 8 and 9.
The board can be used for the following purposes:
(A) measuring RF sensitivity performance.
(B) Indicating port function.
(C) Synthesising a voltage controlled oscillator.
(D) Testing of external reference sources.
Fig. 6 Example of double conversion from VHF/UHF frequencies to TV IF
Fig. 7 Typical application, SP5658F
9
SP5658
1
14
EXTERNAL REFERENCE
SKT2
10nF*
*(NOT FITTED)
C6
C2
15nF
R6 13K3
C3
68pF
+5V
P2
+12V
C8
C9
C7/C8/C9 = 100nF
R7
22K
C7
R8
16K
R9
47K
C12
2n2F
VAR
GND
T1
2N3904
13
12
11
10
9
8
2
3
4
5
6
7
C5
1nF
C4
1nF
SKT1
RF INPUT
C10
1nF
R5
4K7
D5
D4
D3
D2
D1
R4
4K7
R3
4K7
R2
4K7
R1
4K7
C11
1nF
NC NC
C1
18pF
X1 4MHz
P1
C13
100pF
C14
100pF
DISABLE / REF
ENABLE
DATA / SDA
CLOCK / SCL
8
+30V
PIN NO : 7
LOCK
Fig. 8 Test board
Fig. 9 Test board (layout)
10
SP5658
LOOP BANDWIDTH
The majority of applications for which the SP5658 is
intended require a loop filter bandwidth of between 2kHz and
10kHz.
Typically the VCO phase noise will be specified at both
1kHz and10kHz offset. It is common practice to arrange the
loop filter bandwidth such that the 1kHz figure lies within the
loop bandwidth. Thus the phase noise depends on the
synthesiser comparator noise floor, rather than the VCO.
The 10kHz offset figure should depend on the VCO
providing the loop is designed correctly, and is not
underdamped.
REFERENCE SOURCE
The SP5658 offers optimal LO phase noise performance
when operated with a large step size. This is due to the fact that
the LO phase noise within the loop bandwidth is:
phase comparator
noise floor
+ 20 log
10
LO frequency
phase comparator frequency
Assuming the phase comparator noise floor is flat irrespective
of sampling frequency, this means that the best performance
will be achieved when the overall LO to phase comparator
division ratio is a minimum.
There are two ways of achieving a higher phase
comparator sampling frequency:
A) Reduce the division ratio between the reference source
and the phase comparator
B) use a higher reference source frequency.
Approach B) may be preferred for best performance since it is
possible that the noise floor of the reference oscillator may
degrade the phase comparator performance if the reference
division ratio is very small.
( )
11
SP5658
V
REF
500
500
RF INPUTS
V
CC
CHARGE
PUMP
DRIVE
OUTPUT
PORT/LOCK
CRYSTAL
RF inputs
Loop amplifier
Disable, Enable, Data and Clock inputs
Reference oscillator
Output Ports and Lock Output
/O
V
CC
BIAS
25K
200
OS
(Output disable)
V
CC
Fig. 10 Input/Output interface circuits
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Copyright 1999 MITEL Corporation
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