SP8402
Very Low Phase Noise Divider by 2
N
The SP8402 is a very low phase noise divider which divides
by powers of two. The S0, S1, S2 data inputs select the division
ratio in the range 2
1
to 2
8
. Special circuits techniques have been
used to reduce the phase noise considerably below that
produced by standard dividers. The data inputs are CMOS or
TTL compatible.
The SP8402 is packaged in a 28 pin plastic SO package to
be compatible with the SP8400 and SP8401 devices.
FEATURES
s
Very low Phase Noise (Typically -155 to 160dBc/Hz at 1kHz
offset)
s
Supply Voltage 5V
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
6.5V
Output Current
20mA
Storage Temperature Range
-55
C to +125
C
Maximum Clock Input Voltage
2.5V p-p
ORDERING INFORMATION
SP8402 KG MPES (Commercial Grade)
MP28
Fig.1 Pin connections - top view
DS3738 - 2.1 March 1994
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
N/C
N/C
N/C
V
CC
+5V
GND
CLOCK INPUT
CLOCK INPUT
CLOCK INPUT
GND
V
CC
+5V
V
CC
+5V
N/C
S0
N/C
N/C
N/C
N/C
N/C
N/C
N/C
OUTPUT
OUTPUT
N/C
V
CC
+5V
N/C
S2
S1
CLOCK INPUT
Fig.2 Typical single sideband phase noise measured at 768MHz
(f) (dBc/Hz) 3dB
Frequency (Hz)
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
170
10
100
1k
10k
100k
2
SP8400
Fig.3 Typical input sensitivity
ELECTRICAL CHARACTERISTICS
Guaranteed over: Supply voltage V
CC
= +4.75V to +5.25V Temperature T
amb
= -10
C to +75
C
Tested at +4.75V and +5.25V at T
amb
= +25
C
FREQUENCY MHz
400
300
200
100
0
200
400
600
800
1000
1200
1400
355mV
140mV
OPERATING WINDOW
1600
500
600
V
in
mV rms
Min.
Typ.
Max.
Supply current
Output voltage swing
Input sensitivity 200MHz to 1.5GHz
Data Inputs
Logic high voltage
Low low voltage
Input current
92
410
102
140
(-4)
0.8
180
82
320
2.2
4, 11, 12, 18
20, 21
7, 8
Output loaded with 300R See Fig.5
p-p @ 1.4GHz input
256 mode
outputs loaded with 330R See Fig.5
RMS Sine wave into 50 Ohms
(dBm equivalent) See Fig.3
5V Data input voltage
mA
mV
mV
dBm
V
V
A
Units
Value
Conditions
Characteristic
Pin
S0
L
H
L
H
L
H
L
H
S1
L
L
H
H
L
L
H
H
S2
L
L
L
L
H
H
H
H
DIVISION RATIO
2
4
8
16
32
64
128
256
Fig.4 Truth table
3
SP8400
Fig.5 Test circuit
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SP8402
10nF
10nF
1nF
1nF
2x330R
1nF
TTL/CMOS
MODULUS
CONTROL
220nF
50R
OUTPUT
V
CC
RF
50R
SIGNAL
GENERATOR
4
SP8400
Fig.5 Typical application combining output to increase signal and retain low phase noise
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SP8402
10nF
10nF
1nF
1nF
2x330R
1nF
S0
S1
S2
50R
10nF
OUTPUT
10 F
+5V
CLOCK
INPUT
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