FUNCTION

VDD

SCL

PD5

SDA

PD6

DACCOMP

PD7

RED/C

CLAMP

GREEN/Y

COMPSYNC

AVDD

PALID

AGND

SCSYNC

AVDD

REFSQ

BLUE/CVBS2

GND

CVBS1

VDD

VREF

FC2

RREF

FC1

AGND

FC0

AGND

HSYNC

AVDD

VSYNC

PD0

TTXREQ

PD1

PD2

TTXDATA

PD3

VDD

PD4

GND

RESET

PXCK

ORDERING INFORMATION

VP5313A/CG/GP1N
VP5513A/CG/GP1N

The VP5313/VP5513 converts digital Y Cr Cb data into

analog PAL or NTSC composite video, and also provides
simultaneous RGB outputs. These additional converters can
optionally provide separate luma and chroma outputs plus a
further composite video channel. All outputs are capable of
driving doubly terminated 75

loads with standard video

levels.
All D/A converters are to 9 bit accuracy, and are provided with
27MHz oversampled data. The latter simplifies the
requirement for external analog anti-aliasing filters, and
reduces the sinx/x distortion inherent in D/A converters.
Separate digital scaling is applied to the chroma data path in
order to make the most efficient use of the 9 bit dynamic range.
The device accepts data inputs complying with CCIR
recommendation 656. In this format 4:2:2 video is multiplexed
onto an 8 bit bus using a 27MHz clock. Active video markers
are embedded into the data stream and extracted by the
VP5313/VP5513. Optionally the user can supply separate
horizontal and vertical syncs, and colour can be genlocked to
an external subcarrier if necessary.

In an alternative operating mode the VP5313/VP5513 can

be configured as the source of sync for the rest of the system.
In this master mode the horizontal and vertical sync pins
become outputs, and any control codes in the CCIR656 bit
stream are ignored.

The VP5313/VP5513 supports the insertion of teletext

data through a serial interface. An internal filter shapes the
data edges.

FEATURES

Converts Y, Cr, Cb data to analog RGB and composite
or S-video and composite video

Supports CCIR recommendations 601 and 656

All digital video encoding

Selectable master/slave mode for sync signals

Switchable chrominance bandwidth

CCIR 624 PAL SMPTE or 170M NTSC compatible
outputs

GENLOCK mode

C bus serial microprocessor interface

Only VP5313 supports Macrovision anti-taping
Rev. 7.01

Line 21 Closed Caption encoding

Teletext insertion, fully line programmable

APPLICATIONS

Digital Cable TV

Digital Satellite TV

Multi-media

Video games

Digital VCRs

Karaoke

Fig.1 Pin connections (top view)

GP44

VP5313/VP5513

NTSC/PAL Digital Video Encoder

Supersedes DS4509 1.9 September 1997 edition

DS4509 - 2.2 October 1998

VP5313/VP5513

RECOMMENDED OPERATING CONDITIONS

Parameter

Min.

Typ.

Max.

Units

Power supply voltage
Power supply current (including analog outputs)

Power supply current (including analog outputs)

Input clock frequency
SCL clock frequency
Analog video output load
DAC gain resistor
Ambient operating temperature

Symbol

VDD, AVDD

IDD
IDD

PXCK

SCL

4.75

-50ppm

5.25

230
190

+50ppm

500

mA
mA

MHz

kHz

�

5.00

27.00

37.5

730

All four DACs driving 37R5 loads

All four DACs driving 75R loads

ELECTRICAL CHARACTERISTICS

Test conditions (unless otherwise stated): As specified in Recommended Operating Conditions

DC CHARACTERISTICS

VIN

VIL

VIH

VIL

IIH

IIL

VOH

VOL

2.0

0.7VDD

3.7

0.8

0.3VDD

-10

0.4

0.6

�

Parameter

Conditions

VIN = VDD

VIN = VSS

IOH = -1mA

IOL = +4mA

IOL = +6mA

Symbol

Min.

Typ.

Max.

Units

Digital Inputs TTL compatible (except SDA, SCL)

Input high voltage

Input low voltage

Digital Inputs SDA, SCL

Input high voltage

Input low voltage

Input high current

Input low current

Digital Outputs CMOS compatible

Output high voltage

Output low voltage

Digital Output SDA

Output low voltage

66.83

1.00

1.3899

34.15

DC CHARACTERISTICS DACs

INL

DNL

REF

0.95

�

1.5

�

1.05

LSB
LSB

�

mA
mA

pV-s

Parameter

Symbol

Min.

Typ.

Max.

Units

Accuracy (each DAC)

Integral linearity error
Diffential linearity error
DAC matching error
Monotonicity
LSB size

Internal reference voltage
Internal reference voltage output impedance
Reference Current (V

REF

) R

REF

= 730

Maximum output
Peak Glitch Energy (see fig.3)

guaranteed

ABSOLUTE MAXIMUM RATINGS

Supply voltage

VDD, AVDD

-0�3 to 7�0V

Voltage on any non power pin

-0�3 to VDD+0�3V

Ambient operating temperature

0 to 70

�

Storage temperature

-55

�

C to 150

�

Note: Stresses exceeding these listed under Absolute
Maximum Ratings may induce failure. Exposure to Absolute
Maximum Ratings for extended periods may reduce
reliability. Functionality at or above these conditions is not
implied.

VP5313/VP5513

Pins

All pins

Notes

Meets Mil-Std-883 Class 2

Test Levels

2kV on 100pF through 1k5

200V on 200pF through 0

& 500nH

Test

Human body model

Machine model

Luminance bandwidth
Chrominance bandwidth (Extended B/w mode)
Chrominance bandwidth (Reduced B/w mode)
Burst frequency (NTSC)
Burst frequency (PAL-B, D,G,H,I)
Burst frequency (PAL-N Argentina)
Burst cycles (NTSC and PAL-N)
Burst cycles ( PAL-B, D, G, H,I)
Burst envelope rise / fall time (NTSC )
Burst envelope rise / fall time (PAL-B, D, G, H, I, N)
Analog video sync rise / fall time (NTSC)
Analog video sync rise / fall time (PAL-B, D, G, H,I)
Analog video blank rise / fall time (NTSC )
Analog video blank rise / fall time (PAL-B, D, G, H,I)
Differential gain
Differential phase
Signal to noise ratio (unmodulated ramp)
Chroma AM signal to noise ratio (100% red field)
Chroma PM signal to noise ratio (100% red field)
Hue accuracy
Colour saturation accuracy
Residual sub carrier
Luminance / chrominance delay

VIDEO CHARACTERISTICS (NTSC, PAL COMPOSITE VIDEO)

Parameter

1
1

-61
-56
-58
2.5
2.5

Max.

Symbol

Min.

Typ.

5.5
1.3

650

3.57954545
4.43361875
3.58205625

300
300
145
245
145
245

-60

MHz
MHz

kHz

MHz
MHz
MHz

Fsc cycles
Fsc cycles

ns
ns
ns
ns
ns
ns

% pk-pk

�

pk-pk

dB
dB
dB

%
%

Units

ESD COMPLIANCE

19.98
1.337

33.75
17.63

1.40
7.61
7.61
0.40

18.70

8.01
8.01
0.00

DC CHARACTERISTICS DACs

mA
mA

mA
mA
mA
mA
mA
mA

mA
mA
mA
mA

Parameter

Symbol

Min.

Typ.

Max.

Units

RGB outputs:

Peak level
Black level

CVBS1, 2 Y and C outputs - NTSC (pedestal enabled)
Maximum output, relative to sync bottom
White level relative to black level
Black level relative to blank level
Blank level relative to sync level
Colour burst peak - peak
DC offset (bottom of sync)

CVBS1, 2, Y and C outputs - PAL
White level relative to black level
Black level relative to sync level
Colour burst peak - peak
DC offset (bottom of sync)

All figures are for: RREF = 730

; if RL = 75

then RREF = 1460

VP5313/VP5513

Pin Name

Pin No.

Description

PD0-7

2-4,

8 Bit Pixel Data inputs clocked by PXCK. PD0 is the least significant bit. These pins are
internally pulled low.

PXCK

27MHz Pixel Clock input. The VP5313/VP5513 internally divides PXCK by two to provide the
pixel clock.

Slave address select.

SCL

Standard I

C bus serial clock input.

SDA

Standard I

C bus serial data input/output.

FC0-2

12-14

Field Counter output in master sync mode.

REFSQ

Reference square wave input used only during Genlock mode.

SCSYNC

Subcarrier sync input, (synchronises phase quadrant in 4xfsc genlock mode), see fig 6.

PALID

PAL IDENT input, controls swinging colour burst phase in PAL genlock mode.

COMPSYNC

Composite sync pulse output. This is an active low output signal.

CLAMP

The CLAMP output signal is synchronised to COMPSYNC output and indicates the position of
the BURST pulse, (lines 10-263 and 273-525 for NTSC; lines 6-310 and 319-623 for PAL-
B,D,G,I,N(Argentina)).

TTXREQ

Teletext Data Request output, requests next line of teletext data.

TTXDATA

Teletext Data input.

HSYNC

Horizontal Sync, output in master mode, input in slave mode

VSYNC

Vertical Sync, output in master mode, input in slave mode

RESET

Master reset. This is an asynchronous, active low, input signal and must be asserted for a
minimum 200ns in order to reset the VP5313/VP5513.

VREF

Voltage reference output. This output is nominally 1�0V and should be decoupled with a
100nF capacitor to GND.

RREF

DAC full scale current control. A resistor connected between this pin and GND sets the
magnitude of the video output current. An internal loop amplifier controls a reference current
flowing through this resistor so that the voltage across it is equal to the Vref voltage. This
reference current has a weighting equal to 20.8 LSB's.

DACCOMP

DAC compensation. A 100nF ceramic capacitor must be connected to AVDD.

CVBS1

Composite video output. These are high impedance current source outputs. A DC path to
GND must exist from each of these pins.

BLUE/CVBS2

Blue or composite DAC output. Output type as CVBS1.

GREEN/Y

Green or luminance DAC output. Output type as CVBS1.

RED/C

Red or chrominance DAC output. Output type as CVBS1.

VDD

1, 11, 20

Positive supply input. All VDD pins must be connected.

AVDD

37,28,30

Analog positive supply input. All AVDD pins must be connected.

GND

10,21,43

Negative supply input. All GND pins must be connected.

AGND

36,29,35

Analog negative supply input. All AGND pins must be connected.

PIN DESCRIPTIONS

38-42

VP5313/VP5513

ADDRESS

hex

00
01
02
03
04
05
06
07
08
09

0A
0B
0C
0D
0E
0F

10
11
12

13-1F
20-33
34-3F

40
41
42
43
44
45
46
47

48-4F

50
51
52
53
54

55-5F

60
61

62-FD
FE-FF

REGISTER

NAME

BAR

PART ID2
PART ID1
PART ID0

REV ID

MODE

GCR

VOCR

RSTCTL
SC_ADJ

FREQ2
FREQ1
FREQ0

SCHPHM

SCHPHL

HSOFFL

HSOFFM

SLAVE1
SLAVE2
TSTPAT

Not used

Reserved

Not used

TTXLO2
TTXLO1
TTXLO0

TTXLE2
TTXLE1
TTXLE0

TTXDD

TTXCTL

Not used

CCREG1
CCREG2
CCREG3
CCREG4

CC_CTL

Not used

IICEXCTL
IICEXW/R

Not used

Reserved

RA7

ID17
ID0F
ID07

REV7

FSC4SEL

DITHEN

SC7

FR17
FR0F
FR07

SCH7

HSOFF7

NCORSTD

HCNT7

L14
L22

L327
L335

TTXDD7

-
-
-
-
-

CTL7

W/RD7

RA6

ID16

ID0E

ID06

REV6

GENDITH

CHRMCLIP

SC6

FR16

FR0E

FR06

SCH6

HSOFF6

VBITDIS

HCNT6

L13
L21

L326
L334

TTXDD6

F1W1D6
F1W2D6
F2W1D6
F2W2D6

CTL6

W/RD6

RA5

ID15

ID0D

ID05

REV5

GENLKEN

CHRBW

SC5

FR15

FR0D

FR05

SCH5

HSOFF5

VSMODE

HCNT5

L12
L20

L325
L333

TTXDD5

F1W1D5
F1W2D5
F2W1D5
F2W2D5

CTL5

W/RD5

RA4

ID14

ID0C

ID04

REV4

DACCFG
NOLOCK

SYNCDIS

SC4

FR14

FR0C

FR04

SCH4

HSOFF4

F_SWAP

HCNT4

L11
L19

L324
L332

TTXDD4

F1W1D4
F1W2D4
F2W1D4
F2W2D4

CTL4

W/RD4

RA2

ID12

ID0A

ID02

REV2

VFS0

YCDELAY

LUMDIS

SC2

FR12

FR0A

FR02

SCH2

HSOFF2

SL_HS0

HCNT2

L17

L322
L330

TTXDD2

F1W1D2
F1W2D2
F2W1D2
F2W2D2

F1ST

CTL2

W/RD2

RA1

ID11
ID09
ID01

REV1

SYNCM1

CLMPDIS

CHRDIS

SC1

FR11
FR09
FR01

SCH1

HSOFF1
HSOFF9

HCNT9
HCNT1

TTXPAT

L16

L319
L321
L329

TTXDD1

F1W1D1
F1W2D1
F2W1D1
F2W2D1

F2EN

CTL1

W/RD1

RA3

ID13

ID0B

ID03

REV3

VFS1

PALIDEN

BURDIS

SC3

FR13

FR0B

FR03

SCH3

HSOFF3

SL_HS1

HCNT3

L10
L18

L323
L331

TTXDD3

F1W1D3
F1W2D3
F2W1D3
F2W2D3

F2ST

CTL3

W/RD3

DEFAULT

hex

00
53
13
01
00
00
20
00

9C
A8

00
00

00
00
00
00

00
00
00
00
00
00
01
00

XX
XX
XX
XX

RA0

ID10
ID08
ID00

REV0

SYNCM0

CVBSCLMP

PEDEN

TSURST

SC0

FR10
FR08
FR00

SCH8
SCH0

HSOFF0
HSOFF8

HCNT8
HCNT0

RAMPEN

L6
L7

L15

L318
L320
L328

TTXDD0

TTXEN

F1W1D3
F1W2D3
F2W1D3
F2W2D3

F1EN

CTL0

W/RD0

R/W

R
R
R
R

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

R/W
R/W
R/W
R/W
R/W

R/W

REGISTERS MAP

See Register Details for further explanations.

Table.1 Register map

VP5313/VP5513

REGISTER DETAILS

BAR

Base register

RA7-0

PART ID 2-0

Part number

ID17-00

Chip part ID number

REV ID

Revision number

REV7-0

Chip revision ID number

MODE

Mode Control

DACCFG
0

R,G,B & CVBS analog outputs

Y,C, CVBS1 & CVBS2 analog outputs

VFS1

VFS0

Video Standard

PAL-B,D,G,H,I,N(Arg.)

NTSC

Reserved

SYNCM1 SYNCM0

Sync mode

Slave, Rec. 656

Slave H & V I/P

Master H & V O/P

Reserved

GCR

Global Control

FSC4SEL

Input subcarrier frequency select

REFSQ I/P = Fsubcarrier
SCSYNC I/P ignored

REFSQ I/P = 4 x Fsubcarrier
When SCSYNC I/P is asserted the
REFSQ I/P divide by 4 is reset

GENDITH

Genlock dither addition control

No dither added

Dither added

GENLKEN

Genlock enable control

Internal subcarrier generation

When high, enable Genlock to REFSQ

NOLOCK

Genlock status bit (read only)

Genlocked

Cannot lock to REFSQ.
This bit is cleared by reading and set
again if lock cannot be attained.

PALIDEN

PAL Ident select

Normal operation, internal PAL switch
is used.

Enables PALID input, a phase control
an for PALID signal, (0 = +135

�

, 1 = -135

�

)

YCDELAY

Add delay to luma channel

Luma to Chroma delay, 0ns

Luma to Chroma delay, 37ns

CLAMPDIS

CLAMP O/P select

CLAMP O/P enabled

CLAMP O/P disabled

CVBSCLAMP Composite clamp enable

CVBS Clamp disabled

Clamps CVBS output, to prevent out of
range DAC codes.

VOCR

Video Output Control

DITHEREN

Luma dither enable

Normal operation

Luma dither enabled

CHRMCLIP

Chroma clipping select

No chroma clipping

Enable clipping of chroma data when
luma is clipped

CHRBW

Chroma bandwidth select

�

650kHz

�

1�3MHz

SYNCDIS

Sync disable (in CVBS signal)

Normal operation

Sync disabled

(COMPSYNC O/P is not affected)

BURDIS

Chroma burst disable

Normal operation

Chroma burst disabled

LUMDIS

Luma input disable - force black level

Normal operation

Luma disabled

CHRDIS

Chroma input disable - force monochrome

Normal operation

Chroma disabled

PEDEN

Pedestal (set-up) select
Valid for NTSC

Pedestal disabled

7�5 IRE pedestal on lines
23-262 and 286-525

VP5313/VP5513

RSTCTL

Reset Data Control

TSURST

Soft reset control

Normal operation

Chip soft reset

SC_ADJ

Sub Carrier Adjust

SC7-0

Sub carrier frequency seed value.

FREQ2-0

Sub carrier frequency

FR17-00

24 bit Sub carrier frequency programmed via
I

C bus. FREQ3 is the MSB.

SCHPHM-L

Sub carrier phase offset

SCH8-0

9 bit Sub carrier phase relative to the 50%
point of the leading edge of the horizontal
part of composite sync. SCHPHM bit 0 is the
MSB.

HSOFFL-M

Horizontal Sync Output Offset

HSOFF9-0

This is a 10 bit number which allows the user
to offset the start of digital data input with
reference to the pulse HS.

SLAVE1-2

H & V Slave Mode Control

NCORSTD

NCO line reset disable
NCO is always reset at end of 4(8)
field sequence in NTSC(PAL) regardless
of the value of this control bit

NCO is reset every line in NTSC mode

NCO line reset is disabled

VBITDIS

Ignore REC656 V-bit select

REC656 V-bit will be decoded and the
line blanked accordingly

REC656 V-bit will be ignored

VSMODE

Select type of Vsync input

Standard Vsync I/P

Field even/odd Vsync I/P

F_SWAP

Invert field detect decision

Standard relationship applies

Inverted relationship applies

SL_HS(1:0)

Internal Hsync delay control

No internal delay

1 x 27MHz cycle delay

2 x 27MHz cycle delay

3 x 27MHz cycle delay

TSLAVE2

HCNT(9:0) - Internal H counter is reset to this
value on falling edge of Hsync input.

TSTPAT

Test Pattern Register

TTX_PAT

Teletext test pattern enable

Normal operation

Teletext test pattern enabled

RAMPEN

Modulated test ramp enable

Normal operation

Modulated test ramp enabled

TTXLO2-0

Teletext Odd Line Enable

L6-22

1 = Teletext Enabled on that line number

TTXLE2-0

Teletext Even Line Enable

L318-335

1 = Teletext Enabled on that line number

TTXDD7-0

Teletext Request Pulse Position

TTXCTL

Teletext Control

TTXEN

Teletext enable

Teletext disabled

Teletext enabled

CCREG1

Closed Caption register 1

F1W1D6-0

Field one (line 21), first data byte

CCREG2

Closed Caption register 2

F1W2D6-0

Field one (line 21), second data byte

CCREG3

Closed Caption register 3

F2W2D6-0

Field two (line 284), first data byte

CCREG4

Closed Caption register 4

F2W2D6-0

Field two (line 284), second data byte

CCCTL

Closed Caption control register

F1ST

Field one (line 21) status bit

New data has been loaded to CCREG1-2

Data has been encoded

F2ST

Field one (line 284) status bit

New data has been loaded to CCREG3-4

Data has been encoded

F1EN

Closed Caption field one (line 21)

Disabled

Enabled

F2EN

Closed Caption field one (line 284)

Disabled

Enabled

VP5313/VP5513

IICEXCTL

C Extension Control

CTL7-0

Each bit controls port direction
0 = output 1 = input

IICEXR/W

C Extension Control

RD7-0

C bus read and write data from

C extension port

C BUS CONTROL INTERFACE

C bus address

The serial microprocessor interface is via the bi-directional

port consisting of a data (SDA) and a clock (SCL) line. It is
compatible to the Philips I

C bus standard (Jan. 1992

publication number 9398 393 40011). The interface is a slave
transmitter - receiver with a sub-address capability. All
communication is controlled by the microprocessor. The SCL
line is input only. The most significant bit (MSB) is sent first.
Data must be stable during SCL high periods.

A bus free state is indicated by both SDA and SCL lines

being high. START of transmission is indicated by SDA being
pulled low while SCL is high. The end of transmission, referred
to as a STOP, is indicated by SDA going from low to high while
SCL is high. The STOP state can be omitted if a repeated
START is sent after the acknowledge bit. The reading device
acknowledges each byte by pulling the SDA line low on the
ninth clock pulse, after which the SDA line is released to allow
the transmitting device access to the bus.

The device address can be partially programmed by the

setting of the pin SA. This allows the device to respond to one
of two addresses, providing for system flexibility. The I

C bus

address is seven bits long with the last bit indicating read/write
for subsequent bytes.

The first data byte sent after the device address, is the sub-

address - BAR (base address register). The next byte will be
written to the register addressed by BAR and subsequent
bytes to the succeeding registers. The BAR maintains its data
after a STOP signal.

NTSC/PAL Video Standards

Both NTSC (4-field, 525 lines) and PAL (8-field, 625 lines)

video standards are supported by the VP5313/VP5513. All
raster synchronisation, colour sub-carrier and burst charac-
teristics are adapted to the standard selected. The VP5313/
VP5513 generates outputs which follow the requirements of
SMPTE 170M and CCIR 624 for PAL signals.

The device supports the following standards:
PAL B, D, G, H, I, N (Argentina) (default state) and
NTSC.

Video Blanking

The VP5313/VP5513 automatically performs standard

composite video blanking. Lines 1-9, 264-272 inclusive, as
well as the last half of line 263 are blanked in NTSC mode. In
PAL mode, lines 1-5, 311-318, 624-625 inclusive, as well as
the last half of line 623 are blanked.

The V bit within REC656 defines the video blanking when

in TRS slave mode. By setting VBITDIS in the SLAVE1
register this blanking can be overidden. When in MASTER
mode the V bit is ignored; hence, if any lines are required to be
blank, they must have no video signal input on them.

Interpolator

The luminance and chrominance data is separately

passed through interpolating filters to produce output
sampling rates double that of the incoming pixel rate. This
reduces the sinx/x distortion that is inherent in the digital to
analog converters (DACs), and also simplifies the analog
reconstruction filter requirements.

Digital to Analog Converters

The VP5313/VP5513 contains four 9 bit digital to analog

converters which produce the analog video signals. The
DACs use a current steering architecture in which bit currents
are routed to one of two outputs; thus the DAC has true and
complimentary outputs, however, only the true outputs are
available on the pins. The use of identical current sources and
current steering their outputs means that monoticity is
guaranteed. An on-chip voltage reference of 1�00V (typ.)
provides the necessary biasing; if required, this can be
overridden by an external reference.

The full-scale output currents of the DACs is set by an

external 730

resistor between the RREF and AGND pins. An

on-chip loop amplifier stabilises the full-scale output current
against temperature and power supply variations.
By digitally summing the luma and chroma outputs a
composite output is generated. The analog outputs of the
VP5313/VP5513 are capable of directly driving doubly
terminated 75

co-axial cable. If it is required only to drive a

single 75

load then the DACGAIN resistor is simply doubled.

Luminance, Chrominance and Composite Video Outputs

The Luminance video output drives a 37.5

load at 1�0V,

sync tip to peak white. It contains only the luminance content
of the image plus the composite sync pulses. In the NTSC
mode, a set-up level offset is added during the active video
portion of the raster.

The Chrominance video output drives a 37.5

load at

levels proportional in amplitude to the luma output (40 IRE pk-
pk burst). Burst is injected with the appropriate timing relative
to the luma signal.

Output sinx/x compensation filters are required on all

video outputs, as shown in the typical application diagram, see
fig. 11 & 12.

RGB Video Outputs

The RGB video outputs drive a 37.5

load at 0.7V blank

to peak.

Output sinx/x compensation filters are required on all

video outputs, as shown in the typical application diagram, see
fig. 11 & 12.

Video Timing - Slave sync mode

The VP5313/VP5513 has an internal timing generator

which produces video timing signals appropriate to the mode
of operation. TRS slave mode means that the video encoder
synchronises itself to the TRS (Timing Reference Signal)
codes that are embedded into the Rec. 656 data pattern. In the

VP5313/VP5513

default (power up) the TRS slave mode is selected. All internal
timing signals are derived from the input clock, (PXCK) this
must be derived from a crystal controlled oscillator. Input pixel
data is latched on the rising edge of the PXCK clock.
The video timing generator produces the internal blanking and
burst gate pulses, together with the composite sync output
signal.

H&V slave mode is enabled by setting the SYNCM1-0 bits

in the MODE register to 01. In this mode the position of the
video syncs is derived from the HS and VS inputs. These HS
and VS pins are automatically configured as inputs.

Video Timing - Master sync mode

When SYNCM1-0 of the MODE register are 10, the

VP5313/VP5513 operates in a MASTER sync mode, all
REC656 timing reference codes are ignored with VS, HS and
FC0-2 outputs providing synchronisation signals to an
external (MPEG) device. The PXCK signal is, however, still
used to generate all internal clocks. In master mode the
direction setting of bits 4 - 0 of the IICEXCTL register are
ignored.

VS is the start of the field sync datum in the middle of the

equalisation pulses. HS is the line sync which is used by the
preceding MPEG2 decoder to define when to output digital
video data to the VP5313/VP5513. The position of the falling
edge of HS relative to the first data Cb0, can be programmed
in HSOFFM-L registers, see figure 5.

Genlock using REFSQ input

The VP5313/VP5513 can be Genlocked to another video

source by setting GENLKEN high (in GCR register) and
feeding a phase coherent sub carrier frequency signal into
REFSQ. Under normal circumstances, REFSQ will be the
same frequency as the sub carrier; however if FSC4SEL is set
high (in GCR register), a 4 x sub carrier frequency signal may
be input to REFSQ. In this case, the Genlock circuit can be
reset to the required phase of REFSQ, by supplying a pulse
to SCSYNC. The frequency of SCSYNC can be at the sub
carrier frequency, once per line or once per field could be
adequate, depending on the application. When GENLKEN is
set high, the direction setting of bit 5 of the IICEXCTL register
is ignored.

PALID input

When using PAL and Genlock mode; the VP5313/VP5513

requires a PAL phase identification signal, to define the
correct phase on every line. This is supplied to PALID input,
High = -135

�

and low = +135

�

. The signal is asynchronous,

and should by changed before the sub carrier burst signal.
PALID input is enabled by setting PALIDEN high (in GCR
register). When PALIDEN is set high, the direction setting of
bit 7 of the IICEXCTL register is ignored.

Line 21 coding

Two bytes of data are coded on the line 21 of each field,

see figure 8. In the NTSC Closed Caption service, the default
state is to code on line 21 of field one only. An additional
service can also be provided using line 21 (284) of the second
field. The data is coded as NRZ with odd parity, after a clock
run-in and framing code. The clock run-in frequency =
0.5034965MHz which is related to the nominal line period, D
= H / 32.

D = 63.55555556 / 32

�

Two data bytes per field are loaded via I

C bus registers

CCREG1-4. Each field can be independently enabled by
programming the enable bits in the control register (CC_CTL).
The data is cleared to zero in the Closed Caption shift
registers after it has been encoded by the VP5313/VP5513.
Two status bit are provided (in CC_CTL), which are set high
when data is written to the registers and set low when the data
has been encoded on the Luma signal. The data is cleared to
zero in the Closed Caption shift registers after it has been
encoded by the VP5313/VP5513. The next data bytes must
be written to the registers when the status bit goes high,
otherwise the Closed Caption data output will contain Null
characters. If a transmission slot is missed (ie. no data
received) the encoder will send Null characters. Null
characters are invisible to a closed caption reciever. The MSB
(bit 7) is the parity bit and is automatically added by the
encoder.

Teletext

The Teletext function within the VP5313/VP5513 co-

ordinates the insertion of teletext serial data into the
luminance data stream and subsequently the composite video
data stream.

The serial data is filtered prior to insertion to minimise the

high frequency components and to reduce the jitter inherent in
the digital data stream.

The lines in which teletext data are inserted are individually

programmable for both even and odd fields. The insertion of
teletext data will only be enabled if the format of the composite
video is configured to be PAL-B,G,H,I,N and the teletext
enable bit TTXEN is asserted.

For test purposes, the teletext function incorporates

control logic to generate a serial clock cracker pattern in place
of the normal teletext data. This test pattern is enabled when
the TTX_PAT bit is asserted. There is no row coding used so
it will not display on a TV.

The VP5313/VP5513 teletext interface comprises of a

teletext request output, TTX_REQ, and a serial data input,
TTX_DATA.

To ensure that the composite video timing requirements

are satisfied, the serial data must be received at a specific
point in time during lines containing teletext data. The teletext
request output, TTX_REQ, will be asserted to indicate when
data must be applied to TTX_DATA, which must be generated
synchronous to the rising edges of PXCK. The TTX_REQ may
be advanced in multiples of PXCK, to compensate for the
latency within the source device, by writing to the TTXDD
register.

The serial teletext data which is applied to the TTX_DATA

input must obey the sequence defined below.

The teletext bit rate is defined to be 6.9375 MHz, which

equates to 444 times the PAL line frequency (15.625 kHz). It
is clear that for a 27 MHz system clock, a constant bit period
cannot be achieved.

VP5313/VP5513

Figure 5 REC 656 interface with HS output timing

Pixel Data Input (PD[7,0])

PXCK Input (27MHz)

Cb0

Cr0

Cb1

Cr1

Nck=0

Nck=2

SU; PD

HD; PD

The horizontal line duration for PAL equates to 1728

CLK27M cycles and within each line there are 444 data bit
periods. The duration of 37 data bits (the smallest number
possible for an integer number of CLK27M cycles) therefore
equates to 144 CLK27M cycles.

To ensure that the average bit rate is 6.9375 MHz, 33 in

every 37 data bits will have a duration of 4 CLK27M cycles and
4 in every 37 data bits will have a duration of 3 CLK27M cycles.
Of the first 37 data bits in each line, bits 10, 19, 28 and 37 will

have a duration of 3 CLK27M cycles. The sequence will be
repeated for all subsequent 37 bit groups.

Master Reset

The VP5313/VP5513 must be initialised with RESET. This

is an asynchronous, active low signal and must be active for
a minimum of 200ns in order to reset the VP5313/VP5513.
The device resets to line 64, start of horizontal sync (i.e. line
blanking active). There is no on-chip power on reset circuitry.

(d) = default
xx = don't care.

The calculation of the FREQ register value is according to the following formula:-

FREQ = 2

/PXCK hex, where PXCK = 27.00MHz

NTSC value is rounded UP from the decimal number. PAL-B, D, G, H, I and N (Argentina) are rounded DOWN. The SC_ADJ
value is derived from the adjustment needed to be added after 8 fields to ensure accuracy of the Subcarrier frequency. Note the
SC_ADJ value of 9C required for PAL-B, D, G, H, I.

Standard

NTSC

PAL-B, G, H, I (d)

PAL-N (Argentina)

FREQ2-0

registers hex

87 C1 F1

A8 26 2B

87 DA 51

Lines/

field

525

625

Field

freq. HZ

59.94

1716

1728

Number of

pixels/line

at 27MHz

15.734266

15.625000

Horizontal

freq. kHz.

3.57954545

4.43361875

3.58205625

Subcarrier

freq. kHz.

(455/2)

(1135/4+1/625)

(917/4+1/625)

SC_ADJ

register

hex

Table.2 Line, field and subcarrier standards and register settings

NCO Adjustment

9 10 11 12 13 14 15 16

19 20 21

22 23 24

TTXDD

textbit #:

TTX_REQ

TTX_DATA

CVBS/Y

Figure 4 Teletext timing diagram

VP5313/VP5513

10.250

�

48 IRE

10.500

�

6.5D (12.910

�

2.0D (3.972

�

1.0D (1.986

�

16.0D (31.778

�

32.0D (63.556)

0.240

�

50 IRE

0 IRE

48 IRE

50 IRE

10.750

�

0.288

�

52 IRE

2 IRE

52 IRE

Encoder minimum

Encoder nominal

Encoder maximum

Description

H-sync to clock run-in

Clock run-in

2, 3

Clock run-in to third start bit

Data bit

1, 3

Data characters

Horizontal line

Rise / fall time of data bit transitions

Data bit high (logic level one)

Clock run-in maximum

Data bit low (logic level zero)

Clock run-in minimum

Data bit differential (high - low)
Clock run-in differential (max. - min)

Interval

Table. 5 Closed Caption data timing. (source EIA R - 4.3 Sept 16 1992)

Notes
1.

The Horizontal line frequency fH is nominally 15734.26Hz

�

0.05Hz. Interval D shall be adjusted to D = 1/(fH x 32) for the

instantaneous fH at line 21.

The clock run-in signal consists of 7.0 cycles of a 0.5034965MHz (1/D) sine wave when measured from the leading to trailing
0 IRE points. The sine wave is to be symmetrical about the 25 IRE level.

The negative going midpoints (half amplitude) of the clock run-in shall be coherent with the midpoints (half amplitude) of the
Start and Data bit transitions.

Two characters, each consisting of 7 data bits and 1 odd parity bit.

2 T Bar, measured between the 10% and 90% amplitude points.

The clock run-in maximum level shall not differ from the data bit high level by more than

�

1 IRE. The clock run-in minimum

level shall not differ from the data bit low level by more than

�

1 IRE.

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Электронный компонент: VP5513ACGGP1N