DESCRIPTION

The 3820 group is the 8-bit microcomputer based on the 740 fam-

ily core technology.

The 3820 group has the LCD drive control circuit and the serial I/

O as additional functions.

The various microcomputers in the 3820 group include variations

of internal memory size and packaging. For details, refer to the

section on part numbering.

For details on availability of microcomputers in the 3820 group, re-

fer to the section on group expansion.

FEATURES

Basic machine-language instructions ....................................... 71

The minimum instruction execution time ............................ 0.5

(at 8MHz oscillation frequency)

Memory size

ROM .................................................................. 4 K to 32 K bytes

RAM ................................................................. 192 to 1024 bytes

Programmable input/output ports ............................................. 43

Software pull-up/pull-down resistors (Ports P0-P7 except Port P4

)

Interrupts .................................................. 16 sources, 16 vectors

(includes key input interrupt)

Timers ........................................................... 8-bit

3, 16-bit

Serial I/O1 ..................... 8-bit

1 (UART or Clock-synchronized)

Serial I/O2 .................................... 8-bit

1 (Clock-synchronized)

LCD drive control circuit

Bias ................................................................................... 1/2, 1/3

Duty ............................................................................ 1/2, 1/3, 1/4

Common output .......................................................................... 4

Segment output ......................................................................... 40

2 Clock generating circuit

Clock (X

-X

OUT

) .................................. Internal feedback resistor

Sub-clock (X

CIN

-X

COUT

) .......... Without internal feedback resistor

(connect to external ceramic resonator or quartz-crystal oscillator)

Watchdog timer ............................................................. 15-bit

Power source voltage

In high-speed mode .................................................... 4.0 to 5.5 V

(at 8MHz oscillation frequency and high-speed selected)

In middle-speed mode ................................................2.5 to 5.5 V

(at 8MHz oscillation frequency and middle-speed selected)

In low-speed mode ...................................................... 2.5 to 5.5 V

(Extended operating temperature version: 3.0 V to 5.5 V)

Power dissipation

In high-speed mode ........................................................... 32 mW

(at 8 MHz oscillation frequency)

In low-speed mode .............................................................. 45

(at 32 kHz oscillation frequency, at 3 V power source voltage)

Operating temperature range ................................... 20 to 85

(Extended operating temperature version: 40 to 85

APPLICATIONS

Household appliances, consumer electronics, etc.

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

PIN CONFIGURATION (TOP VIEW)

/SEG

SEG

COM

/INT

/RTP

/INT

OUT

RDY1

CLK1

/INT

COM

IN2

/CNTR

RDY2

CLK2

OUT2

/CNTR

/RTP

OUT

RESET

COUT

CIN

M38203M4-XXXFP

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

M38203M4-XXXFP

Package type : 80P6N-A

80-pin plastic molded QFP

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

PIN CONFIGURATION (TOP VIEW)

Package type : 80P6S-A/80P6D-A

80-pin plastic-molded QFP

/SEG

SEG

COM

/INT

/RTP

/INT

OUT

RDY1

CLK1

/INT

COM

IN2

/CNTR

RDY2

CLK2

OUT2

/CNTR

/RTP

OUT

RESET

COUT

CIN

8 9 10 11 12 13 14 15 16 17 18 19 20

M38203M4-XXXGP

M38203M4-XXXHP

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

FUNCTIONAL BLOCK DIAGRAM (Package : 80P6N-A)

INT

CNTR

,CNTR

OUT

CPU

ROM

P0(8)

P7(2)

SI/O1(8)

COM

SEG

CIN

COUT

P1(8)

P2(8)

P4(8)

P5(8)

LCD

drive control

circuit

RAM

LCD display

RAM

(20 bytes)

Timer X(16)

Timer Y(16)

Timer 1(8)

Timer 2(8)

Timer 3(8)

Data bus

Clock generating

circuit

Clock

input

Clock

output

OUT

COUT

Sub-

clock

output

CIN

Sub-

clock

input

Reset input

(5V)

(0V)

RESET

I/O port P7

P6(2)

I/O port P6

Watchdog timer

P3(8)

P0(8)

I/O port P0

I/O port P1

Key-on wake up

I/O port P2

Real time port function

Input port P3

I/O port P4

INT

,INT

SI/O2(8)

I/O port P5

SEG

RESET

RTP

,RTP

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Function

· Apply voltage of 2.5 V to 5.5 V to V

, and 0 V to V

(Extended operating temperature version : 3.0 V to 5.5 V)

· Reset input pin for active "L"

· Input and output pins for the main clock generating circuit.
· Feedback resistor is built in between X

pin and X

OUT

pin.

· Connect a ceramic resonator or a quartz-crystal oscillator between the X

and X

OUT

pins to set

the oscillation frequency.

· If an external clock is used, connect the clock source to the X

pin and leave the X

OUT

pin open.

· This clock is used as the oscillating source of system clock.

· Input 0

voltage

· Input 0 V

voltage to LCD

· LCD common output pins
· COM

and COM

are not used at 1/2 duty ratio.

· COM

is not used at 1/3 duty ratio.

· LCD segment output pins

· 8-bit I/O port
· CMOS compatible input level
· CMOS 3-state output structure
· I/O direction register allows each port to be individually

programmed as either input or output.

· Pull-down control is enabled.

· 8-bit I/O port
· CMOS compatible input level
· CMOS 3-state output structure
· I/O direction register allows each port to be individually

programmed as either input or output.

· Pull-down control is enabled.

· 8-bit I/O port
· CMOS compatible input level
· CMOS 3-state output structure
· I/O direction register allows each pin to be individually

programmed as either input or output.

· Pull-up control is enabled.

· 8-bit Input port
· CMOS compatible input level
· Pull-down control is enabled.

· 1-bit input pin
· CMOS compatible input level

· 7-bit I/O port
· CMOS compatible input level
· CMOS 3-state output structure
· I/O direction register allows each pin to be individually

programmed as either input or output.

· Pull-up control is enabled.

RESET

OUT

COM

SEG

/SEG

/INT

CLK1,

RDY1

Name

Power source

Reset input

Clock input

Clock output

LCD power source

Common output

Segment output

I/O port P0

I/O port P1

I/O port P2

Input port P3

Input port P4

I/O port P4

Function except a port function

· LCD segment pins

· Key input (key-on wake up) interrupt

input pins

· LCD segment pins

clock output pin

· Interrupt input pins

· Serial I/O1 function pins

PIN DESCRIPTION

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Function

· 8-bit I/O port
· CMOS compatible input level
· CMOS 3-state output structure
· I/O direction register allows each pin to be individually

programmed as either input or output.

· Pull-up control is enabled.

· 2-bit I/O port
· CMOS compatible input level
· CMOS 3-state output structure
· I/O direction register allows each pin to be individually

programmed as either input or output.

· Pull-up control is enabled.

· 2-bit I/O port
· CMOS compatible input level
· CMOS 3-state output structure
· I/O direction register allows each pin to be individually

programmed as either input or output.

· Pull-up control is enabled.

IN2

OUT2

CLK2

RDY2

/CNTR

OUT

/INT

/RTP

COUT,

CIN

PIN DESCRIPTION

Name

I/O port P5

I/O port P6

I/O port P7

Function except a port function

· Serial I/O2 function pins

· Timer function pins

· Timer output pin

· Interrupt input pin

· Interrupt input pins(P6

)

· Real time port function pin

· Sub-clock generating circuit input

pins
(Connect a resonator. External clock
cannot be used.)

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

GROUP EXPANSION

Mitsubishi plans to expand the 3820 group as follows:

(1) Support for mask ROM, One Time PROM, and EPROM

versions

(2) ROM/PROM size .......................................... 8 K to 32 K bytes

RAM size ..................................................... 512 to 1024 bytes

(3) Packages

80P6N-A ............................. 0.8 mm-pitch plastic molded QFP

80P6S-A ........................... 0.65 mm-pitch plastic molded QFP

80P6D-A ............................. 0.5 mm-pitch plastic molded QFP

80D0 ................ 0.8 mm-pitch ceramic LCC (EPROM version)

Memory Expansion Plan

M38207M8/E8

New product

M38203M4/E4

Mass product

ROM size (bytes)

32K

28K

24K

20K

16K

12K

192 256

384

512

640

768

896

1024

RAM size (bytes)

Currently supported products are listed below.

As of May 1996

RAM size (bytes)

512

1024

Remarks

Mask ROM version

One Time PROM version

One Time PROM version (blank)

Mask ROM version

One Time PROM version

One Time PROM version (blank)

Mask ROM version

One Time PROM version

One Time PROM version (blank)

EPROM version

Mask ROM version

One Time PROM version

One Time PROM version (blank)

Mask ROM version

One Time PROM version

One Time PROM version (blank)

Mask ROM version

One Time PROM version

One Time PROM version (blank)

EPROM version

Package

80P6N-A

80P6S-A

80P6D-A

80D0

80P6N-A

80P6S-A

80P6D-A

80D0

Product

M38203M4-XXXFP

M38203E4-XXXFP

M38203E4FP

M38203M4-XXXGP

M38203E4-XXXGP

M38203E4GP

M38203M4-XXXHP

M38203E4-XXXHP

M38203E4HP

M38203E4FS

M38207M8-XXXFP

M38207E8-XXXFP

M38207E8FP

M38207M8-XXXGP

M38207E8-XXXGP

M38207E8GP

M38207M8-XXXHP

M38207E8-XXXHP

M38207E8HP

M38207E8FS

16384

(16254)

(P) ROM size (bytes)
ROM size for User in ( )

32768

(32638)

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

M38207M8D

New product

M38203M4D

New product

ROM size (bytes)

32K

28K

24K

20K

16K

12K

192 256

384

512

640

768

896

1024

RAM size (bytes)

GROUP EXPANSION
(EXTENDED OPERATING TEMPERATURE VERSION)

Mitsubishi plans to expand the 3820 group (extended operating

temperature version) as follows:

(1) Support for mask ROM, One Time PROM, and EPROM

versions

(2) ROM size ................................................... 16 K to 32 K bytes

RAM size ..................................................... 512 to 1024 bytes

(3) Packages

80P6N-A ............................. 0.8 mm-pitch plastic molded QFP

80P6S-A ...........................

0.65 mm-pitch plastic molded QFP

Memory Expansion Plan

Currently supported products are listed below.

RAM size (bytes)

512

1024

16384(16254)

32768(32638)

Remarks

Mask ROM version

As of May 1996

Package

80P6N-A

80P6S-A

Product

M38203M4DXXXFP

M38207M8DXXXFP

M38207M8DXXXGP

ROM size (bytes)

ROM size for User in ( )

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Remarks

Mask ROM version

Package

80P6N-A

80P6S-A

80P6D-A

80P6N-A

80P6S-A

80P6D-A

RAM size (bytes)

Product

M38203M2LXXXFP

M38203M2LXXXGP

M38203M2LXXXHP

M38203M4LXXXFP

M38203M4LXXXGP

M38203M4LXXXHP

GROUP EXPANSION
(LOW POWER SOURCE VOLTAGE VERSION)

Mitsubishi plans to expand the 3820 group (low power source volt-

age version) as follows:

(1) Support for mask ROM version

(2) ROM size ...................................................... 8 K to 32 K bytes

RAM size .................................................................. 512 bytes

(3) Packages

80P6N-A ............................. 0.8 mm-pitch plastic molded QFP

80P6S-A ........................... 0.65 mm-pitch plastic molded QFP

80P6D-A ............................. 0.5 mm-pitch plastic molded QFP

Memory Expansion Plan

Currently supported products are listed below.

8192

(8062)

As of May 1996

ROM size (bytes)

ROM size for User in ( )

16384

(16254)

M38203M2L

New product

ROM size (bytes)

32K

28K

24K

20K

16K

12K

192 256

384

512

640

768

896

1024

RAM size (bytes)

M38203M4L

New product

512

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)

The 3820 group uses the standard 740 family instruction set. Re-

fer to the table of 740 family addressing modes and machine in-

structions or the SERIES 740 <Software> User's Manual for de-

tails on the instruction set.

Machine-resident 740 family instructions are as follows:

The FST and SLW instruction cannot be used.

The STP, WIT, MUL, and DIV instruction can be used.

CPU Mode Register

The CPU mode register is allocated at address 003B

The CPU mode register contains the stack page selection bit and

the internal system clock selection bit.

Fig. 1 Structure of CPU mode register

CPU mode register

(

CPUM (CM) : address

003B

)

Not available

Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 :
1 0 :
1 1 :
Stack page selection bit
0 : 0 RAM in the zero page is used as stack area
1 : 1 RAM in page 1 is used as stack area
Not used (returns "1" when read)
(Do not write "0" to this bit)
Port X

switch bit

0 : I/O port
1 : X

CIN

, X

COUT

Main clock ( X

OUT

) stop bit

0 : Oscillating
1 : Stopped
Main clock division ratio selection bit
0 : f(X

)/2 (high-speed mode)

1 : f(X

)/8 (middle-speed mode)

Internal system clock selection bit
0 : X

-X

OUT

selected (middle-/high-speed mode)

1 : X

CIN

-X

COUT

selected (low-speed mode)

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MEMORY
Special Function Register (SFR) Area

The Special Function Register area in the zero page contains con-

trol registers such as I/O ports and timers.

RAM

RAM is used for data storage and for stack area of subroutine

calls and interrupts.

ROM

The first 128 bytes and the last 2 bytes of ROM are reserved for

device testing and the rest is user area for storing programs.

Interrupt Vector Area

The interrupt vector area contains reset and interrupt vectors.

Zero Page

The 256 bytes from addresses 0000

to 00FF

are called the

zero page area. The internal RAM and the special function regis-

ters (SFR) are allocated to this area.

The zero page addressing mode can be used to specify memory

and register addresses in the zero page area. Access to this area

with only 2 bytes is possible in the zero page addressing mode.

Special Page

The 256 bytes from addresses FF00

to FFFF

are called the

special page area. The special page addressing mode can be

used to specify memory addresses in the special page area. Ac-

cess to this area with only 2 bytes is possible in the special page

addressing mode.

Fig. 2 Memory map diagram

0100

0000

0040

0440

FF00

FFDC

FFFE

FFFF

192
256
384
512
640
768
896
1024

XXXX

00FF

013F

01BF

023F

02BF

033F

03BF

043F

4096
8192

12288
16384
20480
24576
28672
32768

F000

E000

D000

C000

B000

A000

9000

8000

F080

E080

D080

C080

B080

A080

9080

8080

YYYY

ZZZZ

RAM

ROM

0054

Reserved area

SFR area

Not used

Interrupt vector area

ROM area

Reserved ROM area

(128 bytes)

Zero page

Special page

RAM area

RAM size

(bytes)

Address
XXXX

ROM size

(bytes)

Address

YYYY

LCD display RAM area

Address

ZZZZ

Reserved ROM area

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Fig.3 Memory map of special function register (SFR)

0020

0021

0022

0023

0024

0025

0026

0027

0028

0029

002A

002B

002C

002D

002E

002F

0030

0031

0032

0033

0034

0035

0036

0037

0038

0039

003A

003B

003C

003D

003E

003F

0000

0001

0002

0003

0004

0005

0006

0007

0008

0009

000A

000B

000C

000D

000E

000F

0010

0011

0012

0013

0014

0015

0016

0017

0018

0019

001A

001B

001C

001D

001E

001F

Serial I/O2 register (SIO2)

Port P0 (P0)

Port P0 direction register (P0D)

Port P1 (P1)

Port P1 direction register (P1D)

Port P2 (P2)

Port P2 direction register (P2D)

Port P3 (P3)

Port P4 (P4)

Port P4 direction register (P4D)

Port P5 (P5)

Port P5 direction register (P5D)

Port P6 (P6)

Port P6 direction register (P6D)

Port P7 (P7)

Port P7 direction register (P7D)

Transmit/Receive buffer register (TB/RB)

Serial I/O1 status register (SIO1STS)

Serial I/O1 control register (SIO1CON)

UART control register (UARTCON)

Baud rate generator (BRG)

Serial I/O2 control register (SIO2CON)

Interrupt control register 2(ICON2)

Timer 3 (T3)

Timer X mode register (TXM)

Watchdog timer control register (WDTCON)

Interrupt edge selection register

(INTEDGE)

CPU mode register (CPUM)

Interrupt request register 1(IREQ1)

Interrupt request register 2(IREQ2)

Interrupt control register 1(ICON1)

Timer X (low-order) (TXL)

Timer Y (low-order) (TYL)

Timer 1 (T1)

Timer 2 (T2)

Timer X (high-order) (TXH)

Timer Y (high-order) (TYH)

PULL register A (PULLA)

PULL register B (PULLB)

Timer Y mode register (TYM)

Timer 123 mode register (T123M)

output control register (CKOUT)

Segment output enable register (SEG)

LCD mode register (LM)

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

I/O PORTS
Direction Registers (ports P2, P4

P4

, and

P5P7)

The 3820 group has 43 programmable I/O pins arranged in seven

I/O ports (ports P0P2 and P4P7). The I/O ports P2, P4

and P5P7 have direction registers which determine the input/out-

put direction of each individual pin. Each bit in a direction register

corresponds to one pin, each pin can be set to be input port or

output port.

When "0" is written to the bit corresponding to a pin, that pin be-

comes an input pin. When "1" is written to that bit, that pin be-

comes an output pin.

If data is read from a pin set to output, the value of the port output

latch is read, not the value of the pin itself. Pins set to input are

floating. If a pin set to input is written to, only the port output latch

is written to and the pin remains floating.

Direction Registers (ports P0 and P1)

Ports P0 and P1 have direction registers which determine the in-

put /output direction of each individual port.

Each port in a direction register corresponds to one port, each

port can be set to be input or output.

When "0" is written to the bit 0 of a direction register, that port be-

comes an input port. When "1" is written to that port, that port be-

comes an output port.

Bits 1 to 7 of ports P0 and P1 direction registers are not used.

Ports P3 and P4

These ports are only for input.

Pull-up/Pull-down Control

By setting the PULL register A (address 0016

) or the PULL reg-

ister B (address 0017

), ports except for port P4

can control ei-

ther pull-down or pull-up (pins that are shared with the segment

output pins for LCD are pull-down; all other pins are pull-up) with a

program.

However, the contents of PULL register A and PULL register B do

not affect ports programmed as the output ports.

Fig. 4 Structure of PULL register A and PULL register B

PULL register A
(PULLA : address 0016

)

0 : Disable
1 : Enable

Note : The contents of PULL register A
and PULL register B do not affect
ports programmed as the output ports.

PULL register B
(PULLB : address 0017

)

pull-down

pull-up

pull-down

, P7

pull-up

Not used (return "0" when read)

pull-up

, P6

pull-up

Not used (return "0" when read)

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Related SFRs

PULL register A

Segment output

enable register

PULL register A

Segment output

enable register

PULL register A

Interrupt control

PULL register A

Segment output

enable register

PULL register B

output control

PULL register B

Interrupt edge selection

PULL register B

Serial I/O1 control register

Serial I/O1 status register

UART control register

PULL register B

Serial I/O2 control

PULL register B

Timer X mode register

PULL register B

Timer Y mode register

PULL register B

Timer 123 mode register

PULL register B

Interrupt edge

selection register

PULL register B

Timer X mode register

Interrupt edge

selection register

PULL register B

Timer X mode register

PULL register A

CPU mode register

LCD mode register

/SEG

/INT

CLK1

RDY1

IN2

OUT2

CLK2

RDY2

/CNTR

OUT

/INT

/RTP

COUT

CIN

COM

-COM

SEG

-SEG

Name

Port P0

Port P1

Port P2

Port P3

Port P4

Port P5

Port P6

Port P7

Common

Segment

Input/Output

Input/output,

individual ports

Input/output,

individual ports

Input/output,

individual bits

Input

Input/output,

individual bits

Input/output,

individual bits

Input/output,

individual bits

Input/output,

individual bits

output

I/O Format

CMOS compatible

input level

CMOS 3-state output

CMOS compatible

input level

CMOS 3-state output

CMOS compatible

input level

CMOS 3-state output

CMOS compatible

input level

CMOS compatible

input level

CMOS compatible

input level

CMOS 3-state output

CMOS compatible

input level

CMOS 3-state output

CMOS compatible

input level

CMOS 3-state output

CMOS compatible

input level

CMOS 3-state output

LCD common output

LCD segment output

Non-Port Function

LCD segment output

Key input(Key-on

wake up) interrupt

input

LCD segment output

clock output

External interrupt input

Serial I/O1 function I/O

Serial I/O2 function I/O

Timer I/O

Timer output

External interrupt input

Real time port

function output

Real time port

function output

Sub-clock

generating circuit

I/O

Diagram No.

(1)

(2)

(3)

(4)

(5)

(2)

(6)

(7)

(8)

(9)

(10)

(11)

(12)

(13)

(14)

(10)

(15)

(2)

(16)

(17)

(18)

(19)

(20)

Note : Make sure that the input level at each pin is either 0 V or V

during execution of the STP instruction.

When an input level is at an intermediate potential, a current will flow from V

to V

through the input-stage gate.

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Fig. 5 Port block diagram (1)

(3)Ports P3

(1)Ports P0,P1

Segment output enable bit

(Note)

(5)Port P4

Data bus

Pull-down control

Segment output enable bit

Data bus

Direction register

Port latch

Pull-down control

Segment output enable bit

Note. Bit 0 of port P0 direction register and
port P1 direction register.

output control bit

Direction register

Pull-up control

Data bus

Port latch

Direction register

Pull-up control

Data bus

Port latch

Direction register

Pull-up control

Data bus

Port latch

(7)Port P4

Serial I/O1 output

Serial I/O1 enable bit

Transmission enable bit

D P-channel output disable bit

(6)Port P4

(4)Port P4

(2)Ports P2,P4

,P4

,P5

Direction register

Data bus

Port latch

Pull-up control

Key input (Key-on wake up) interrupt input

INT

interrupt input

Pull-up control

Reception enable bit

Serial I/O1 enable bit

Serial I/O1 input

Data bus

Port latch

Data bus

(8)Port P4

Serial I/O1 clock input

Direction register

Pull-up control

Data bus

Port latch

Serial I/O1 clock output

Serial I/O1 mode selection bit

Serial I/O1 enable bit

Serial I/O1 synchronization clock

selection bit

Serial I/O1 enable bit

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Fig. 6 Port block diagram (2)

Serial I/O2 output

Direction register

Port latch

Data bus

Pull-up control

Serial I/O1 ready output

(11) Port P5

(9) Port P4

Serial I/O1 mode selection bit

Serial I/O1 enable bit

Direction register

Port latch

Data bus

Pull-up control

RDY1

output enable bit

Serial I/O2 transmit completion signal

Serial I/O2 port selection bit

Direction register

Port latch

Data bus

Pull-up control

RDY2

output enable bit

Direction register

Port latch

Data bus

Pull-up control

Timer output

OUT

output control bit

Serial I/O2 ready output

(10) Ports P5

(12) Port P5

Direction register

Port latch

Data bus

Pull-up control

Serial I/O2 input

CNTR

interrupt input

Serial I/O2 clock output

Serial I/O2 clock input

Direction register

Port latch

Data bus

Pull-up control

Internal synchronization clock

select bits

Serial I/O2 port selection bit

Timer X operating mode bit

Timer output

CNTR

interrupt input

(Pulse output mode selection)

Direction register

Port latch

Data bus

Pull-up control

Real time port control bit

INT

interrupt input

Except P6

Data for real time port

Direction register

Port latch

Data bus

Pull-up control

(14) Port P5

(16) Ports P6

, P6

(15) Port P5

(13) Port P5

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

INTERRUPTS

Interrupts occur by sixteen sources: seven external, eight internal,

and one software.

Interrupt Control

Each interrupt is controlled by an interrupt request bit, an interrupt

enable bit, and the interrupt disable flag except for the software in-

terrupt set by the BRK instruction. An interrupt occurs if the corre-

sponding interrupt request and enable bits are "1" and the inter-

rupt disable flag is "0".

Interrupt enable bits can be set or cleared by software.

Interrupt request bits can be cleared by software, but cannot be

set by software.

The BRK instruction cannot be disabled with any flag or bit. The I

(interrupt disable) flag disables all interrupts except the BRK in-

struction interrupt.

Interrupt Operation

When an interrupt is received, the contents of the program counter

and processor status register are automatically stored into the

stack. The interrupt disable flag is set to inhibit other interrupts

from interfering.The corresponding interrupt request bit is cleared

and the interrupt jump destination address is read from the vector

table into the program counter.

Notes on Use

When the active edge of an external interrupt (INT

INT

, CNTR

or CNTR

) is changed, the corresponding interrupt request bit

may also be set. Therefore, please take following sequence;

(1) Disable the external interrupt which is selected.

(2) Change the active edge selection.

(3) Clear the interrupt request bit which is selected to "0".

(4) Enable the external interrupt which is selected.

Interrupt Source

Reset (Note 2)

INT

Serial I/O1

receive

Serial I/O1

transmit

Timer X

Timer Y

Timer 2

Timer 3

CNTR

Timer 1

INT

Key input

(Key-on wake up)

Serial I/O2

BRK instruction

Low

FFFC

FFFA

FFF8

FFF6

FFF4

FFF2

FFF0

FFEE

FFEC

FFEA

FFE8

FFE6

FFE4

FFE2

FFE0

FFDE

FFDC

High

FFFD

FFFB

FFF9

FFF7

FFF5

FFF3

FFF1

FFEF

FFED

FFEB

FFE9

FFE7

FFE5

FFE3

FFE1

FFDF

FFDD

Table 1. Interrupt vector addresses and priority

Priority

Interrupt Request

Generating Conditions

At reset

At detection of either rising or

falling edge of INT

input

At detection of either rising or

falling edge of INT

input

At completion of serial I/O1

data reception

At completion of serial I/O1

transmit shift or when transmit

buffer register is empty

At timer X underflow

At timer Y underflow

At timer 2 underflow

At timer 3 underflow

At detection of either rising or

falling edge of CNTR

input

At detection of either rising or

falling edge of CNTR

input

At timer 1 underflow

At detection of either rising or

falling edge of INT

input

At detection of either rising or

falling edge of INT

input

At falling of conjunction of input

level for port P2 (at input mode)

At completion of serial I/O2

data transmission or reception

At BRK instruction execution

Remarks

Non-maskable

External interrupt

(active edge selectable)

External interrupt

(active edge selectable)

Valid when serial I/O1 is selected

External interrupt

(active edge selectable)

External interrupt

(active edge selectable)

External interrupt

(active edge selectable)

External interrupt

(active edge selectable)

External interrupt

(valid when an "L" level is applied)

Valid when serial I/O2 is selected

Non-maskable software interrupt

Vector Addresses (Note 1)

Notes

1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Fig. 8 Interrupt control

Fig. 9 Structure of interrupt-related registers

Interrupt request bit

Interrupt enable bit

Interrupt disable flag (I)

BRK instruction

Reset

Interrupt request

7 0

Interrupt edge selection register

INT

interrupt edge selection bit

INT

interrupt edge selection bit

INT

interrupt edge selection bit

INT

interrupt edge selection bit

Not used (return "0" when read)

(INTEDGE : address 003A

)

Interrupt request register 1

INT

interrupt request bit

INT

interrupt request bit

Serial I/O1 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit

Interrupt control register 1

INT

interrupt enable bit

INT

interrupt enable bit

Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit

0 : No interrupt request issued
1 : Interrupt request issued

(IREQ1 : address 003C

)

(ICON1 : address 003E

)

Interrupt request register 2

CNTR

interrupt request bit

CNTR

interrupt request bit

Timer 1 interrupt request bit
INT

interrupt request bit

INT

interrupt request bit

Key input interrupt request bit
Serial I/O2 interrupt request bit
Not used (returns "0" when read)

(IREQ2 : address 003D

)

Interrupt control register 2

CNTR

interrupt enable bit

CNTR

interrupt enable bit

Timer 1 interrupt enable bit
INT

interrupt enable bit

INT

interrupt enable bit

Key input interrupt enable bit
Serial I/O2 interrupt enable bit
Not used (returns "0" when read)
(Do not write "1" to this bit)

0 : Interrupts disabled
1 : Interrupts enabled

(ICON2 : address 003F

)

0 : Falling edge active
1 : Rising edge active

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Key Input Interrupt (Key-on Wake Up)

A key input interrupt request is generated by applying "L" level to

any pin of port P3 that have been set to input mode. In other

words, it is generated when AND of input level goes from "1" to "0".

An example of using a key input interrupt is shown in Figure 9,

where an interrupt request is generated by pressing one of the

keys consisted as an active-low key matrix which inputs to ports

Fig. 10 Connection example when using key input interrupt and port P2 block diagram

Port P2

latch

Port P2

direction register = "0"

Port P2

latch

Port P2

direction register = "0"

Port P2

latch

Port P2

direction register = "0"

Port P2

latch

Port P2

direction register = "0"

Port P2

latch

Port P2

direction register = "1"

Port P2

latch

Port P2

direction register = "1"

Port P2

latch

Port P2

direction register = "1"

Port P2

latch

Port P2

direction register = "1"

input

output

PULL register A
Bit 2 = "1"

Port P2
Input reading circuit

Port PXx
"L" level output

P-channel transistor for pull-up

V V

CMOS output buffer

Key input interrupt request

V V

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

TIMERS

The 3820 group has five timers: timer X, timer Y, timer 1, timer 2,

and timer 3. Timer X and timer Y are 16-bit timers, and timer 1,

timer 2, and timer 3 are 8-bit timers.

All timers are down count timers. When the timer reaches "00

an underflow occurs at the next count pulse and the correspond-

ing timer latch is reloaded into the timer and the count is contin-

ued. When a timer underflows, the interrupt request bit corre-

sponding to that timer is set to "1".

Read and write operation on 16-bit timer must be performed for

both high and low-order bytes. When reading a 16-bit timer, read

the high-order byte first. When writing to a 16-bit timer, write the

low-order byte first. The 16-bit timer cannot perform the correct op-

eration when reading during the write operation, or when writing

during the read operation.

Fig. 11 Timer block diagram

Timer 1 count source
selection bit

Real time port
control bit "0"

"1"

/CNTR

"0"

f(X

)/16

(f(X

CIN

)/16 in low-speed mode*)

CNTR

active

edge switch bit

"10"

Timer Y stop
control bit

Falling edge detection

Period
measurement mode

Timer Y
interrupt
request

Pulse width HL continuously measurement mode

Rising edge detection

"00","01","11"

Timer Y operating
mode bit

Timer X
interrupt
request

Timer X mode register
write signal

/CNTR

Timer X (low) (8)

Timer X (low) latch (8)

Timer X (high) latch (8)

direction register

Pulse output mode

latch

Timer X stop
control bit

"0"

"1"

Timer X write
control bit

Q D

Latch

Q D

Latch

"1"

"0"

"1"

"10"

Timer X operat-
ing mode bit

"00","01","11"

f(X

)/16

(f(X

CIN

)/16 in low-speed mode*)

Pulse width
measurement
mode

CNTR

active

edge switch bit

CNTR

active

edge switch bit

Pulse output mode

Timer 2 latch (8)

Timer 2 (8)

"0"

direction register

latch

"1"

OUT

output

active edge
switch bit "0"

Timer 2 write
control bit

"0"

"1"

OUT

output

control bit

"1"

OUT

CIN

Timer 3 count
source selection
bit

"0"

"1"

Timer 2
interrupt
request

Timer 3
interrupt
request

OUT

output control bit

Timer 2 count source
selection bit

Timer 1 latch (8)

Timer 1 (8)

Timer 1
interrupt
request

Data bus

f(X

)/16

(f(X

CIN

)/16 in low-speed mode*)

f(X

)/16

(f(X

CIN

)/16 in low-speed mode*)

f(X

)/16(f(X

CIN

)/16 in low-speed mode*)

* Internal clock

= X

CIN

/2.

CNTR

interrupt
request

CNTR

interrupt
request

Timer Y operating mode bit

"00","01","10"

"11"

direction register "0"

Real time port
control bit "1"

latch

direction register "0"

Real time port
control bit "1"

latch

data for real time port

Timer Y (low) (8)

Timer Y (low) latch (8)

Timer Y (high) latch (8)

Timer 3 latch (8)

Timer 3 (8)

Timer X (high) (8)

Timer Y (high) (8)

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Timer X

Timer X is a 16-bit timer that can be selected in one of four modes

and can be controlled the timer X write and the real time port by

setting the timer X mode register.

Timer mode

The timer counts f(X

)/16 (or f(X

CIN

)/16 in low-speed mode).

Pulse output mode

Each time the timer underflows, a signal output from the CNTR

pin is inverted. Except for this, the operation in pulse output mode

is the same as in timer mode. When using a timer in this mode, set

the corresponding port P5

direction register to output mode.

Event counter mode

The timer counts signals input through the CNTR

pin.

Except for this, the operation in event counter mode is the same

as in timer mode. When using a timer in this mode, set the corre-

sponding port P5

direction register to input mode.

Pulse width measurement mode

The count source is f(X

)/16 (or f(X

CIN

)/16 in low-speed mode. If

CNTR

active edge switch bit is "0", the timer counts while the in-

put signal of CNTR

pin is at "H". If it is "1", the timer counts while

the input signal of CNTR

pin is at "L". When using a timer in this

mode, set the corresponding port P5

direction register to input

mode.

Timer X Write Control

If the timer X write control bit is "0", when the value is written in the

address of timer X, the value is loaded in the timer X and the latch

at the same time.

If the timer X write control bit is "1", when the value is written in the

address of timer X, the value is loaded only in the latch. The value

in the latch is loaded in timer X after timer X underflows.

If the value is written in latch only, unexpected value may be set in

the high-order counter when the writing in high-order latch and the

underflow of timer X are performed at the same timing.

Note on CNTR

Interrupt Active Edge Selec-

tion

CNTR

interrupt active edge depends on the CNTR

active edge

switch bit.

Real Time Port Control

While the real time port function is valid, data for the real time port

are output from ports P6

and P6

each time the timer X

underflows. (However, after rewriting a data for real time port, if the

real time port control bit is changed from "0" to "1", data is output

without the timer X.) If the data for the real time port is changed

while the real time port function is valid, the changed data are out-

put at the next underflow of timer X.

Before using this function, set the corresponding port direction

registers to output mode.

Fig. 12 Structure of timer X mode register

Timer X mode register
(TXM : address 0027

)

Timer X write control bit
0 : Write value in latch and counter
1 : Write value in latch only
Real time port control bit
0 : Real time port function invalid
1 : Real time port function valid
P6

data for real time port

0 : "L" level output
1 : "H" level output
P6

data for real time port

0 : "L" level output
1 : "H" level output
Timer X operating mode bits
b5 b4
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
CNTR

active edge switch bit

· CNTR

interrupt

0 : Falling edge active
1 : Rising edge active
· Pulse output mode
0 : Start at initial level "H" output
1 : Start at initial level "L" output
· Event counter mode
0 : Rising edge active
1 : Falling edge active
· Pulse width measurement mode
0 : Measure "H" level width
1 : Measure "L" level width
Timer X stop control bit
0 : Count start
1 : Count stop

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Timer Y

Timer Y is a 16-bit timer that can be selected in one of four modes.

Timer mode

The timer counts f(X

)/16 (or f(X

CIN

)/16 in low-speed mode).

Period measurement mode

CNTR

interrupt request is generated at rising/falling edge of

CNTR

pin input signal. Simultaneously, the value in timer Y latch

is reloaded in timer Y and timer Y continues counting down. /Ex-

cept for the above-mentioned, the operation in period measure-

ment mode is the same as in timer mode.

The timer value just before the reloading at rising/falling of CNTR

pin input signal is retained until the timer Y is read once after the

reload.

The rising/falling timing of CNTR

pin input signal is found by

CNTR

interrupt. When using a timer in this mode, set the corre-

sponding port P5

direction register to input mode.

Event counter mode

The timer counts signals input through the CNTR

pin.

Except for this, the operation in event counter mode is the same

as in timer mode. When using a timer in this mode, set the corre-

sponding port P5

direction register to input mode.

Pulse width HL continuously measurement mode

CNTR

interrupt request is generated at both rising and falling

edges of CNTR

pin input signal. Except for this, the operation in

pulse width HL continuously measurement mode is the same as in

period measurement mode. When using a timer in this mode, set

the corresponding port P5

direction register to input mode.

Note on CNTR

Interrupt Active Edge Selec-

tion

CNTR

interrupt active edge depends on the CNTR

active edge

switch bit. However, in pulse width HL continuously measurement

mode, CNTR

interrupt request is generated at both rising and

falling edges of CNTR

pin input signal regardless of the setting of

CNTR

active edge switch bit.

Fig. 13 Structure of timer Y mode register

Timer Y mode register
(TYM : address 0028

)

Not used (return "0" when read)
Timer Y operating mode bits
b5 b4
0 0 : Timer mode
0 1 : Period measurement mode
1 0 : Event counter mode
1 1 : Pulse width HL continuously
measurement mode
CNTR

active edge switch bit

· CNTR

interrupt

0 : Falling edge active
1 : Rising edge active

· Period measurement mode

0 : Measure falling edge to falling edge
1 : Measure rising edge to rising edge

· Event counter mode

0 : Rising edge active
1 : Falling edge active

Timer Y stop control bit
0 : Count start
1 : Count stop

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Timer 1, Timer 2, Timer 3

Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for

each timer can be selected by timer 123 mode register. The timer

latch value is not affected by a change of the count source. How-

ever, because changing the count source may cause an inadvert-

ent count down of the timer. Therefore, rewrite the value of timer

whenever the count source is changed.

Timer 2 Write Control

If the timer 2 write control bit is "0", when the value is written in the

address of timer 2, the value is loaded in the timer 2 and the latch

at the same time.

If the timer 2 write control bit is "1", when the value is written in the

address of timer 2, the value is loaded only in the latch. The value

in the latch is loaded in timer 2 after timer 2 underflows.

Timer 2 Output Control

When the timer 2 (T

OUT

) is output enabled, an inversion signal

from pin T

OUT

is output each time timer 2 underflows.

In this case, set the port P5

shared with the port T

OUT

to the out-

put mode.

Note on Timer 1 to Timer 3

When the count source of timer 1 to 3 is changed, the timer count-

ing value may be changed large because a thin pulse is generated

in count input of timer. If timer 1 output is selected as the count

source of timer 2 or timer 3, when timer 1 is written, the counting

value of timer 2 or timer 3 may be changed large because a thin

pulse is generated in timer 1 output.

Therefore, set the value of timer in the order of timer 1, timer 2 and

timer 3 after the count source selection of timer 1 to 3.

Fig. 14 Structure of timer 123 mode register

OUT

output active edge switch bit

0 : Start at "H" output
1 : Start at "L" output

OUT

output control bit

0 : T

OUT

output disabled

1 : T

OUT

output enabled

Timer 2 write control bit

0 : Write value in latch and counter
1 : Write value in latch only

Timer 2 count source selection bit

0 : Timer 1 underflow
1 : f(X

)/16

(Middle-/high-speed mode)
f(X

CIN

)/16

(Low-speed mode)(Note)

Timer 3 count source selection bit

0 : Timer 1 underflow
1 : f(X

)/16

(Middle-/high-speed mode)
f(X

CIN

)/16

(Low-speed mode)(Note)

Timer 1 count source selection bit

0 : f(X

)/16

(Middle-/high-speed mode)
f(X

CIN

)/16

(Low-speed mode)(Note)

1 : f(X

CIN

)

Not used (return "0" when read)

Timer 123 mode register
(T123M :address 0029

)

Note : Internal clock

is f

CIN

)/2 in the low-speed mode.

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

SERIAL I/O1

Serial I/O1 can be used as either clock synchronous or asynchro-

nous (UART) serial I/O1. A dedicated timer (baud rate generator)

is also provided for baud rate generation.

Clock Synchronous Serial I/O1 Mode

Clock synchronous serial I/O1 mode can be selected by setting

the mode selection bit of the serial I/O1 control register to "1".

For clock synchronous serial I/O1, the transmitter and the receiver

must use the same clock. If an internal clock is used, transfer is

started by a write signal to the TB/RB (address 0018

Fig. 15 Block diagram of clock synchronous serial I/O1

Fig. 16 Operation of clock synchronous serial I/O1 function

1/4

F/F

CLK1

Serial I/O1 status register

Serial I/O1 control register

RDY1

f(X

)

Receive buffer register (RB)

Address 0018

Receive shift register

Receive buffer full flag (RBF)

Serial I/O receive interrupt request (RI)

Clock control circuit

Shift clock

Serial I/O1 synchronization
clock selection bit
Frequency division ratio 1/(n+1)

Baud rate generator

Address 001C

BRG count source selection bit

Clock control circuit

Falling-edge detector

Data bus

Address 0018

Shift clock

Transmit shift register shift completion flag (TSC)

Transmit buffer empty flag (TBE)

Serial I/O transmit interrupt request (TI)

Transmit interrupt source selection bit

Address 0019

Data bus

Address 001A

Transmit shift register

Transmit buffer register (TB)

RBF = 1
TSC = 1

TBE = 0

TBE = 1
TSC = 0

Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)

Serial output TxD

Serial input RxD

Write signal to receive/transmit
buffer register (address 0018

)

Overrun error (OE)
detection

Notes 1 : The serial I/O1 transmit interrupt (TI) can be selected to occur either when the transmit buffer register has emptied (TBE=1)

or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the
serial I/O1 control register.
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is
output continuously from the TxD pin.
3 : The serial I/O1 receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1" .

Receive enable signal

RDY1

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Asynchronous Serial I/O1 (UART) Mode

Clock asynchronous serial I/O1 mode (UART) can be selected by

clearing the serial I/O1 mode selection bit of the serial I/O1 control

Eight serial data transfer formats can be selected, and the transfer

formats used by a transmitter and receiver must be identical.

The transmit and receive shift registers each have a buffer regis-

ter, but the two buffers have the same address in memory. Since

the shift register cannot be written to or read from directly, transmit

data is written to the transmit buffer register, and receive data is

read from the receive buffer register.

The transmit buffer register can also hold the next data to be

transmitted, and the receive buffer register can hold a character

while the next character is being received.

Fig. 17 Block diagram of UART serial I/O1

Fig. 18 Operation of UART serial I/O1 function

f(X

)

1/4

PE FE

1/16

Data bus

Receive buffer register(RB)

Address 0018

Receive shift register

Receive buffer full flag (RBF)

Serial I/O receive interrupt request (RI)

Baud rate generator

Frequency division ratio 1/(n+1)

Address 001C

ST/SP/PA generator

Transmit buffer register(TB)

Data bus

Transmit shift register

Address

0018

Transmit shift register shift completion flag (TSC)

Transmit buffer empty flag (TBE)

Serial I/O1 status register

Address

0019

STdetector

SP detector

UART control register

Address 001B

Character length selection bit

Address 001A

BRG count source selection bit

Transmit interrupt source selection bit

Serial I/O1 synchronization clock selection bit

Clock control circuit

Character length selection bit

7 bits

8 bits

Serial I/O1 control register

CLK1

Serial I/O1 status register

TSC=0
TBE=1

RBF=0

TBE=0

RBF=1

TBE=1

TSC=1

Transmit or receive clock

Transmit buffer register

write signal

Generated at 2nd bit in 2-stop-bit mode

1 start bit
7 or 8 data bits
1 or 0 parity bit
1 or 2 stop bit (s)

1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception).
2: The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes "1", depending on the setting of the transmit interrupt
source selection bit (TIC) of the serial I/O1 control register.
3: The serial I/O1 receive interrupt (RI) is set when the RBF flag becomes "1".
4: After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.

Notes

Serial output T

Serial input R

Receive buffer register

read signal

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Serial I/O1 Control Register (SIO1CON) 001A

The serial I/O1 control register contains eight control bits for the

serial I/O1 function.

UART Control Register (UARTCON) 001B

The UART control register consists of four control bits (bits 0 to 3)

which are valid when asynchronous serial I/O is selected and set

the data format of an data transfer. One bit in this register (bit 4) is

always valid and sets the output structure of the P4

D pin.

Serial I/O1 Status Register (SIO1STS) 0019

The read-only serial I/O1 status register consists of seven flags

(bits 0 to 6) which indicate the operating status of the serial I/O

function and various errors.

Three of the flags (bits 4 to 6) are valid only in UART mode.

The receive buffer full flag (bit 1) is cleared to "0" when the receive

buffer is read.

If there is an error, it is detected at the same time that data is

transferred from the receive shift register to the receive buffer reg-

ister, and the receive buffer full flag is set. A write to the serial I/O

status register clears all the error flags OE, PE, FE, and SE (bit 3

to bit 6, respectively). Writing "0" to the serial I/O enable bit SIOE

(bit 7 of the Serial I/O Control Register) also clears all the status

flags, including the error flags.

All bits of the serial I/O1 status register are initialized to "0" at re-

set, but if the transmit enable bit (bit 4) of the serial I/O control reg-

ister has been set to "1", the transmit shift register shift completion

flag (bit 2) and the transmit buffer empty flag (bit 0) become "1".

Transmit Buffer/Receive Buffer Register (TB/
RB) 0018

The transmit buffer register and the receive buffer register are lo-

cated at the same address. The transmit buffer register is write-

only and the receive buffer register is read-only. If a character bit

length is 7 bits, the MSB of data stored in the receive buffer regis-

ter is "0".

Baud Rate Generator (BRG) 001C

The baud rate generator determines the baud rate for serial trans-

fer.

The baud rate generator divides the frequency of the count source

by 1/(n + 1), where n is the value written to the baud rate genera-

tor.

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty

Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full

Transmit shift register shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed

Overrun error flag (OE)
0: No error
1: Overrun error

Parity error flag (PE)
0: No error
1: Parity error

Framing error flag (FE)
0: No error
1: Framing error

Summing error flag (SE)
0: OE U PE U FE =0
1: OE U PE U FE =1

Not used (returns "1" when read)

Serial I/O1 status register
(SIO1STS : address 0019

)

Serial I/O1 control register
(SIO1CON : address 001A

)

BRG count source selection bit (CSS)
0: f(X

)

1: f(X

)/4

Serial I/O1 synchronization clock selection bit (SCS)
·In clock synchronous mode
0 : BRG output/4
1 : External clock input
·In UART mode
0 : BRG output/16
1 : External clock input/16

RDY1

output enable bit (SRDY)

0: P4

RDY1

pin operates as I/O port

1: P4

RDY1

pin operates as signal output pin S

RDY1

signal indicates receive enable state)

Transmit interrupt source selection bit (TIC)
0: When transmit buffer has emptied
1: When transmit shift operation is completed

Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled

Receive enable bit (RE)
0: Receive disabled
1: Receive enabled

Serial I/O1 mode selection bit (SIOM)
0: Clock asynchronous serial I/O1 (UART) mode
1: Clock synchronous serial I/O1 mode

Serial I/O1 enable bit (SIOE)
0: Serial I/O1 disabled
(pins P4

operate as I/O pins)

1: Serial I/O1 enabled
(pins P4

operate as serial I/O1 pins)

UART control register
(UARTCON : address 001B

)

Character length selection bit (CHAS)
0: 8 bits
1: 7 bits

Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled

Parity selection bit (PARS)
0: Even parity
1: Odd parity

Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits

D P-channel output disable bit (POFF)

0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode)

Not used (return"1" when read)

Fig. 19 Structure of serial I/O1 control registers

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

SERIAL I/O2

The serial I/O2 function can be used only for clock synchronous

serial I/O.

For clock synchronous serial I/O2 the transmitter and the receiver

must use the same clock. If the internal clock is used, transfer is

started by a write signal to the serial I/O2 register.

Serial I/O2 Control Register (SIO2CON) 001D

The serial I/O2 control register contains 7 bits which control vari-

ous serial I/O functions.

Fig. 20 Structure of serial I/O2 control register

Fig. 21 Block diagram of serial I/O2 function

Serial I/O2 control register
(SIO2CON : address 001D

)

Internal synchronization clock select bits

0 0 0: f(X

)/8

0 0 1: f(X

)/16

0 1 0: f(X

)/32

0 1 1: f(X

)/64

1 0 0:
1 0 1:
1 1 0: f(X

)/128

1 1 1: f(X

)/256

Serial I/O2 port selection bit
0: I/O port
1: S

OUT2

CLK2

signal output

RDY2

output enable bit

0: I/O port
1: S

RDY2

signal output

Transfer direction selection bit
0: LSB first
1: MSB first

Synchronization clock selection bit
0: External clock
1: Internal clock

Not used (returns "0" when read)

b2 b1 b0

Do not set

"1"

"0"

"1"

"0"

"1"

RDY2

CLK2

"0"

"1"

1/8

1/16

1/32

1/64

1/128

1/256

Data bus

Serial I/O2
interrupt request

Serial I/O2 port selection bit

Serial I/O counter 2 (3)

Serial I/O shift register 2 (8)

Synchronization circuit

Serial I/O2 port selection bit

Synchronization clock

selection bit

RDY2

output enable bit

External clock

Internal synchronization
clock select bits

Divider

latch

RDY2

CLK2

OUT2

IN2

latch

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

LCD DRIVE CONTROL CIRCUIT

The 3820 group has the built-in Liquid Crystal Display (LCD) drive

control circuit consisting of the following.

LCD display RAM

Segment output enable register

LCD mode register

Selector

Timing controller

Common driver

Segment driver

Bias control circuit

A maximum of 40 segment output pins and 4 common output pins

can be used.

Up to 160 pixels can be controlled for LCD display. When the LCD

enable bit is set to "1" after data is set in the LCD mode register,

Fig. 23 Structure of segment output enable register and LCD mode register

Segment output enable register
(SEG : address 0038

)

LCD mode register
(LM : address 0039

)

Duty ratio selection bits
0 0 : Not available
0 1 : 2 (use COM

,COM

)

1 0 : 3 (use COM

COM

)

1 1 : 4 (use COM

COM

)

Bias control bit
0 : 1/3 bias
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
Not used (returns "0" when read)

(Do not write "1" to this bit)

LCD circuit divider division ratio selection bits
0 0 : LCDCK count source
0 1 : 2 division of LCDCK count source
1 0 : 4 division of LCDCK count source
1 1 : 8 division of LCDCK count source
LCDCK count source selection bit (Note)
0 : f(X

CIN

)/32

1 : f(X

)/8192

Segment output enable bit 0

0 : Input ports P3

1 : Segment output SEG

SEG

Segment output enable bit 1

0 : I/O ports P0

, P0

1 : Segment output SEG

,SEG

Segment output enable bit 2

0 : I/O ports P0

1 : Segment output SEG

SEG

Segment output enable bit 3

0 : I/O ports P1

,P1

1 : Segment output SEG

,SEG

Segment output enable bit 4

0 : I/O port P1

1 : Segment output SEG

Segment output enable bit 5

0 : I/O ports P1

1 : Segment output SEG

SEG

Not used (return "0" when read)
(Do not write "1" to this bit)

Note : LCDCK is a clock for a LCD timing controller.

the segment output enable register and the LCD display RAM, the

LCD drive control circuit starts reading the display data automati-

cally, performs the bias control and the duty ratio control, and dis-

plays the data on the LCD panel.

Table 2. Maximum number of display pixels at each

duty ratio

Duty ratio

Maximum number of display pixel

80 dots

or 8 segment LCD 10 digits

120 dots

or 8 segment LCD 15 digits

160 dots

or 8 segment LCD 20 digits

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Bias Control and Applied Voltage to LCD
Power Input Pins

To the LCD power input pins (V

), apply the voltage shown in

Table 3 according to the bias value.

Select a bias value by the bias control bit (bit 2 of the LCD mode

Common Pin and Duty Ratio Control

The common pins (COM

COM

) to be used are determined by

duty ratio.

Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the

LCD mode register).

Fig. 25 Example of circuit at each bias

Table 3. Bias control and applied voltage to V

Bias value

1/3 bias

1/2 bias

Voltage value

LCD

=2/3 V

LCD

=1/3 V

LCD

=1/2 V

LCD

Note 1 : V

LCD

is the maximum value of supplied voltage for the

LCD panel.

Table 4. Duty ratio control and common pins used

Duty

ratio

Common pins used

Notes 1 : COM

and COM

are open

2 : COM

is open

Bit 1

Bit 0

COM

, COM

(Note 1)

COM

(Note 2)

COM

Duty ratio selection bit

R4 = R5

Contrast control

1/2 bias

Contrast control

R1 = R2 = R3

1/3 bias

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

LCD Display RAM

Address 0040

to 0053

is the designated RAM for the LCD dis-

play. When "1" are written to these addresses, the corresponding

segments of the LCD display panel are turned on.

LCD Drive Timing

The LCDCK timing frequency (LCD drive timing) is generated in-

ternally and the frame frequency can be determined with the fol-

lowing equation;

(frequency of count source for LCDCK)

(divider division ratio for LCD)

f(LCDCK)=

f(LCDCK)

duty ratio

Frame frequency=

Fig. 26 LCD display RAM map

Bit

Address

0046

0047

0048

0049

004A

004B

004C

004D

004E

004F

0050

0051

0052

0053

COM

SEG

0040

0041

0042

0043

0044

0045

SEG

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

WATCHDOG TIMER

The watchdog timer gives a mean of returning to the reset status

when a program cannot run on a normal loop (for example, be-

cause of a software run-away).

The watchdog timer consists of an 8-bit watchdog timer L and a 6-

bit watchdog timer H.

Initial Value of Watchdog Timer

At reset or when writing data into the watchdog timer control reg-

ister, the watchdog timer H is set to "3F

" and the watchdog timer

L is set to "FF

". As a write instruction, it is possible to use any in-

struction that can cause a write signal such as STA, LDM and

CLB. Write data except bit 7 has no significance and the above

value is set independently.

Watchdog Timer Operation

The watchdog timer stops at reset and starts a countdown by writ-

ing to the watchdog timer control register. When the watchdog

timer H underflows, an internal reset occurs, and the reset status

is released after waiting the reset release time.

Then the program executes from the reset vector address.

Usually, a program is designed so that data can be written into the

watchdog timer control register before the watchdog timer H

underflows. If data is not written once into the watchdog timer con-

trol register, the watchdog timer does not function.

At execution of the STP instruction, both clock and watchdog timer

stops. At the same time that the stop mode is released, the watch-

dog timer restarts a count (Note). On the other hand, at execution

of the WIT instruction, the watchdog timer does not stop.

The time from execution of writing to the watchdog timer control

follows: (When bit 7 of the watchdog timer control register is "0")

Middle / High-speed mode (f(X

)=8 MHz) .................. 32.768 ms

Low-speed mode (f(X

CIN

)=32 kHz) ..................................... 8.19 s

Note: During the stop release wait time [X

(or X

CIN

) : about 8200

clock cycles], the watchdog timer counts.

Accordingly, does not underflow the watchdog timer H.

Fig. 30 Structure of watchdog timer control register

Fig. 29 Watchdog timer block diagram

Data bus

CIN

"1"

"0"

Internal system
clock selection bit
(Note)

"0"

"1"

1/16

Watchdog timer H
count source selection bit

Reset circuit

Undefined instruction
Reset

Watchdog timer H (6)

When writing to
watchdog timer control
register
set "3F

Internal reset

RESET

Watchdog timer L (8)

When writing to
watchdog timer
control register

set "FF

Note: This bit is bit 7 of CPU mode register. It selects the mode (middle/high-speed or low-speed)

Reset release wait time (about 8200 X

clock cycles)

Watchdog timer H bits (read only)

Not used (returns "1" when read)

Watchdog timer H count source selection bit

0 : Underflow from watchdog timer L
1 : f(X

)/16 or f(X

CIN

)/16

Watchdog timer control register
(WDTCON : address 0037

)

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(0001

) · · ·

Timer Y (low-order)

Port P0 direction register

Port P1 direction register

Port P2 direction register

PULL register B

Timer Y (high-order)

Serial I/O1 control register

UART control register

Serial I/O2 control register

Timer X (high-order)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

( 9 )

(10)

(11)

(12)

(13)

(14)

(15)

(16)

(17)

(18)

(19)

(20)

(21)

(22)

(23)

(24)

(0003

) · · ·

(0005

) · · ·

(0017

) · · ·

(001A

) · · ·

(001B

) · · ·

(001D

) · · ·

(0020

) · · ·

(0021

) · · ·

(0022

) · · ·

(0023

) · · ·

(0024

) · · ·

(0025

) · · ·

(0026

) · · ·

(0027

) · · ·

(0028

) · · ·

(0029

) · · ·

(002A

) · · ·

Address

Timer X (low-order)

Timer 1

Timer 2

Timer 3

Timer X mode register

Timer Y mode register

Timer 123 mode register

output control register

Port P7 direction register

(000F

) · · ·

1 1 1 0 0 0

Serial I/O1 status register

(0019

) · · · 1 0 0 0 0 0

Port P4 direction register

Port P5 direction register

Port P6 direction register

(0009

) · · ·

(000B

) · · ·

(000D

) · · ·

(25)

(26)

(27)

(0037

) · · ·

(0038

) · · ·

(0039

) · · ·

Watchdog timer control register

Segment output enable register

LCD mode register

PULL register A

(0016

) · · · 0 0 0 0 1 0

Note.

: Undefined

The contents of all other registers and RAM are undefined

at poweron reset, so they must be initialized by software.

(28)

(29)

(30)

(31)

(32)

(33)

(34)

(35)

(003A

) · · ·

(003B

) · · ·

(003C

) · · ·

(003D

) · · ·

(003E

) · · ·

Interrupt edge selection register

CPU mode register

Interrupt request register 1

Interrupt request register 2

Interrupt control register 1

Interrupt control register 2

Processor status register

Program counter

0 1 0 0 1 0

Contents of address FFFC

! ! ! ! !

(PS)

(PC

)

(PC

)

Contents of address FFFD

(003F

) · · ·

0 1 1 1 1 1

RESET CIRCUIT

To reset the microcomputer, RESET pin should be held at an "L"

level for 2

s or more. Then the RESET pin is returned to an "H"

level (the power source voltage should be between 2.5 V and

5.5 V, and the oscillation should be stable), reset is released. In or-

der to give the X

clock time to stabilize, internal operation does

not begin until after 8200 X

clock cycles (timer 1 and timer 2 are

connected together and 512 cycles of f(X

)/16) are complete. Af-

ter the reset is completed, the program starts from the address

contained in address FFFD

(high-order byte) and address

FFFC

(low-order byte).

Make sure that the reset input voltage is less than 0.5 V for V

2.5 V (Extended operating temperature version: the reset input

voltage is less than 0.6V for V

of 3.0V).

Fig. 33 Internal state of microcomputer immediately after re-

set

Fig. 32 Example of reset circuit

(Note)

0.2V

Note. Reset release voltage : V

= 2.5V

(Extended operating temperature version : 3.0V)

Power on

RESET

Power source voltage
detection circuit

Reset input
voltage

Power source
voltage

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

CLOCK GENERATING CIRCUIT

The 3820 group has two built-in oscillation circuits. An oscillation

circuit can be formed by connecting a resonator between X

and

OUT

CIN

and X

COUT

). Use the circuit constants in accordance

with the resonator manufacturer's recommended values. No exter-

nal resistor is needed between X

and X

OUT

since a feed-back re-

sistor exists on-chip. However, an external feed-back resistor is

needed between X

CIN

and X

COUT

To supply a clock signal externally, input it to the X

pin and make

the X

OUT

pin open. The sub-clock X

CIN

-X

COUT

oscillation circuit

cannot directly input clocks that are externally generated. Accord-

ingly, be sure to cause an external resonator to oscillate.

Immediately after poweron, only the X

oscillation circuit starts

oscillating, and X

CIN

and X

COUT

pins function as I/O ports. The

pull-up resistor of X

CIN

and X

COUT

pins must be made invalid to

use the sub-clock.

Frequency Control

Middle-speed mode

The internal clock

is the frequency of X

divided by 8.

After reset, this mode is selected.

High-speed mode

The internal clock

is half the frequency of X

Low-speed mode

The internal clock

is half the frequency of X

CIN

A low-power consumption operation can be realized by stopping

the main clock X

in this mode. To stop the main clock, set bit 5

of the CPU mode register to "1".

When the main clock X

is restarted, set enough time for oscil-

lation to stabilize by programming.

Note: If you switch the mode between middle/high-speed and low-

speed, stabilize both X

and X

CIN

oscillations. The suffi-

cient time is required for the sub-clock to stabilize, espe-

cially immediately after poweron and at returning from stop

mode. When switching the mode between middle/high-

speed and low-speed, set the frequency on condition that

f(X

)>3f(X

CIN

Fig. 35 Ceramic resonator circuit

Fig. 36 External clock input circuit

CIN

COUT

OUT

CIN

COUT

OUT

External oscillation
circuit

Open

CIN

COUT

CIN

COUT

Oscillation Control

Stop mode

If the STP instruction is executed, the internal clock

stops at an

"H" level, and X

and X

CIN

oscillators stop. Timer 1 is set to "FF

and timer 2 is set to "01

Either X

or X

CIN

divided by 16 is input to timer 1 as count

source, and the output of timer 1 is connected to timer 2.

The bits of the timer 123 mode register except bit 4 are cleared to

"0". Set the timer 1 and timer 2 interrupt enable bits to disabled

("0") before executing the STP instruction.

Oscillator restarts at reset or when an external interrupt is re-

ceived, but the internal clock

is not supplied to the CPU until

timer 2 underflows. This allows time for the clock circuit oscillation

to stabilize.

Wait mode

If the WIT instruction is executed, the internal clock

stops at an

"H" level. The states of X

and X

CIN

are the same as the state be-

fore the executing the WIT instruction. The internal clock restarts

at reset or when an interrupt is received. Since the oscillator does

not stop, normal operation can be started immediately after the

clock is restarted.

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Fig. 38 State transitions of internal clock

: Port Xc switch bit

0: I/O port
1: X

CIN

, X

COUT

: Main clock (X

OUT

) stop bit

0: Oscillating
1: Stopped
CM

: Main clock division ratio selection bit

0: f(X

)/2 (high-speed mode)

1: f(X

)/8 (middle-speed mode)

: Internal system clock selection bit

0: X

OUT

selected

(middle-/high-speed mode)
1: X

CIN

COUT

selected

(low-speed mode)

Notes

Reset

CPU mode register
(CPUM : address 003B

)

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

=0(8MHz selected)

=1(Middle-speed)

=0(8MHz oscillating)

=0(32kHz stopped)

=0(8MHz selected)

=0(High-speed)

=0(8MHz oscillating)

=0(32kHz stopped)

=0(8MHz selected)

=0(High-speed)

=0(8MHz oscillating)

=1(32kHz oscillating)

=1(32kHz selected)

=0(High-speed)

=0(8MHz oscillating)

=1(32kHz oscillating)

=1(32kHz selected)

=0(High-speed)

=1(8MHz stopped)

=1(32kHz oscillating)

=0(8MHz selected)

=1(Middle-speed)

=0(8MHz oscillating)

=1(32kHz oscillating)

=1(32kHz selected)

=1(Middle-speed)

=0(8MHz oscillating)

=1(32kHz oscillating)

=1(32kHz selected)

=1(Middle-speed)

=1(8MHz stopped)

=1(32kHz oscillating)

Low-speed mode (f(

) =16 kHz)

Low-speed mode (f(

) =16 kHz)

Low-speed mode (f(

) =16 kHz)

Low-speed mode (f(

) =16 kHz)

High-speed mode (f(

) =4MHz)

Middle-speed mode

(f(

) =1 MHz)

Middle-speed mode

(f(

) =1 MHz)

High-speed mode (f(

) =4MHz)

before the switching from the low-speed mode to middle-/high-

1: Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.)
2: The all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wai
mode is released.
3: Timer and LCD operate in the wait mode.
4: In middle-/high-speed mode, when the stop mode is released, a delay of approximately 1 ms occurs automatically by timer 1 and
timer 2.
5: In low-speed mode, when the stop mode is released, a delay of approximately 0.25 s occurs automatically by timer 1 and timer
6: Wait until oscillation stabilizes after oscillating the main clock
speed mode.
7: The example assumes that 8 MHz is being applied to the

pin and 32 kHz to the

CIN

pin.

indicates the internal clock.

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

NOTES ON PROGRAMMING
Processor Status Register

The contents of the processor status register (PS) after a reset are

undefined, except for the interrupt disable flag (I) which is "1". Af-

ter a reset, initialize flags which affect program execution.

In particular, it is essential to initialize the index X mode (T) and

the decimal mode (D) flags because of their effect on calculations.

Interrupts

The contents of the interrupt request bits do not change immedi-

ately after they have been written. After writing to an interrupt re-

quest register, execute at least one instruction before performing a

BBC or BBS instruction.

Decimal Calculations

To calculate in decimal notation, set the decimal mode flag (D) to

"1", then execute an ADC or SBC instruction. Only the ADC and

SBC instructions yield proper decimal results. After executing an

ADC or SBC instruction, execute at least one instruction before

executing a SEC, CLC, or CLD instruction.

In decimal mode, the values of the negative (N), overflow (V), and

zero (Z) flags are invalid.

The carry flag can be used to indicate whether a carry or borrow

has occurred. Initialize the carry flag before each calculation.

Clear the carry flag before an ADC and set the flag before an

SBC.

Timers

If a value n (between 0 and 255) is written to a timer latch, the fre-

quency division ratio is 1/(n + 1).

Multiplication and Division Instructions

The index mode (T) and the decimal mode (D) flags do not affect

the MUL and DIV instruction.

The execution of these instructions does not change the contents

of the processor status register.

Ports

The contents of the port direction registers cannot be read.

The following cannot be used:

· The data transfer instruction (LDA, etc.)

· The operation instruction when the index X mode flag (T) is "1"

· The addressing mode which uses the value of a direction regis-

ter as an index

· The bit-test instruction (BBC or BBS, etc.) to a direction register

· The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a

direction register

Use instructions such as LDM and STA, etc., to set the port direc-

tion registers.

Serial I/O

In clock synchronous serial I/O, if the receive side is using an ex-

ternal clock and it is to output the S

RDY

signal, set the transmit en-

able bit, the receive enable bit, and the S

RDY

output enable bit to

"1".

Serial I/O1 continues to output the final bit from the T

D pin after

transmission is completed. The S

OUT2

pin from serial I/O2 goes to

high impedance after transmission is completed.

Instruction Execution Time

The instruction execution time is obtained by multiplying the fre-

quency of the internal clock

by the number of cycles needed to

execute an instruction.

The number of cycles required to execute an instruction is shown

in the list of machine instructions.

The frequency of the internal clock

is half of the X

frequency.

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

DATA REQUIRED FOR MASK ORDERS

The following are necessary when ordering a mask ROM produc-

tion:

(1) Mask ROM Order Confirmation Form

(2) Mark Specification Form

(3) Data to be written to ROM, in EPROM form (three identical

copies)

ROM PROGRAMMING METHOD

The built-in PROM of the blank One Time PROM version and built-

in EPROM version can be read or programmed with a general-

purpose PROM programmer using a special programming

adapter. Set the address of PROM programmer in the user ROM

area.

The PROM of the blank One Time PROM version is not tested or

screened in the assembly process and following processes. To en-

sure proper operation after programming, the procedure shown in

Figure 39 is recommended to verify programming.

Fig. 39 Programming and testing of One Time PROM version

Programming with PROM

programmer

Screening (Caution)

(150

C for 40 hours)

Verification with

PROM programmer

Functional check in

target device

The screening temperature is far higher
than the storage temperature. Never
expose to 150

C exceeding 100 hours.

Caution :

Package

80P6N-A

80P6S-A

80P6D-A

80D0

Name of Programming Adapter

PCA4738F-80A

PCA4738G-80

PCA4738H-80

PCA4738L-80A

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

RECOMMENDED OPERATING CONDITIONS

ABSOLUTE MAXIMUM RATINGS

Power source voltage

Input voltage P0

, P1

, P2

, P4

, P5

, P6

, P7

Input voltage V

Input voltage RESET, X

Output voltage P0

, P1

Output voltage P3

Output voltage P2

, P4

, P5

, P6

, P7

Output voltage SEG

SEG

Output voltage X

OUT

Power dissipation

Operating temperature

Storage temperature

Topr

Tstg

Symbol

Parameter

Conditions

Ratings

0.3 to 7.0

0.3 to V

+0.3

0.3 to V

to V

+0.3

0.3 to V

+0.3

0.3 to V

+0.3

0.3 to V

+0.3

0.3 to V

+0.3

0.3 to V

+0.3

0.3 to V

+0.3

0.3 to V

+0.3

300

20 to 85

40 to 125

Unit

All voltages are based on V

Output transistors are cut off.

At output port

At segment output

= 25

= 2.5 to 5.5 V, T

= 20 to 85

C, unless otherwise noted.)

5.5

0.3 V

0.2 V

High-speed mode f(X

)=8 MHz

Power source voltage

Middle-speed mode f(X

)=8 MHz

Low-speed mode

Power source voltage

"H" input voltage

, P1

, P3

, P4

, P5

, P6

, P7

(CM

=0)

"H" input voltage

, P4

, P5

"H" input voltage

RESET

"H" input voltage

"L" input voltage

, P1

, P3

, P4

, P5

, P6

, P7

(CM

=0)

"L" input voltage

, P4

, P5

"L" input voltage

RESET

"L" input voltage

Symbol

Parameter

Limits

Min.

Unit

4.0

2.5

0.7 V

0.8 V

5.0

Typ.

Max.

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

RECOMMENDED OPERATING CONDITIONS

= 2.5 to 5.5 V, T

= 20 to 85

C, unless otherwise noted.)

Notes

1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an av

erage value measured over 100 ms. The total peak current is the peak value of all the currents.

2: The peak output current is the peak current flowing in each port.
3: The average output current is an average value measured over 100 ms.
4: When the oscillation frequency has a duty cycle of 50 %.
5: When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency f(X

CIN

) is less than

f(X

)/3.

1.0

2.5

5.0

8.0

(4XV

8.0

"H" total peak output current

, P1

, P2

(Note 1)

"H" total peak output current

,P5

, P6

, P7

(Note 1)

"L" total peak output current

, P1

, P2

(Note 1)

"L" total peak output current

,P5

, P6

, P7

(Note 1)

"H" total average output current P0

, P1

, P2

(Note 1)

"H" total average output current P4

,P5

, P6

, P7

(Note 1)

"L" total average output current

, P1

, P2

(Note 1)

"L" total average output current

,P5

, P6

, P7

(Note 1)

"H" peak output current

, P1

, P2

, P4

, P5

, P6

, P7

(Note 2)

"L" peak output current

, P1

(Note 2)

"L" peak output current

, P4

, P5

, P6

, P7

(Note 2)

"H" average output current

, P1

(Note 3)

"H" average output current

, P4

, P5

, P6

, P7

(Note 3)

"L" average output current

, P1

(Note 3)

"L" average output current

, P4

, P5

, P6

, P7

(Note 3)

Clock input frequency

for timers X and Y

(duty cycle 50 %)

Main clock input oscillation
frequency (Note 4)

Sub-clock input oscillation frequency (Note 4, 5)

OH(peak)

OL(peak)

OH(avg)

OL(avg)

OH(peak)

OL(peak)

OH(avg)

OL(avg)

f(CNTR

)

f(CNTR

)

f(X

)

f(X

CIN

)

Symbol

Parameter

Limits

Min.

MHz

kHz

Unit

Typ.

Max.

4.0 V

5.5 V

4.0 V

32.768

High-speed mode (4.0 V

5.5 V)

High-speed mode (V

4.0 V)

Middle-speed mode

4.0

(2XV

MHz

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

Note : When "1" is set to port X

switch bit (bit 4 of address 003B

) of CPU mode register, the drive ability of port P7

is different from the

value above mentioned.

"H" output voltage P0

, P1

, P3

"H" output voltage P2

, P4

,P5

, P6

, P7

(Note 1)

"L" output voltage

, P1

, P3

"L" output voltage

, P4

, P5

, P6

, P7

(Note 1)

Hysteresis

CNTR

, CNTR

, INT

INT

Hysteresis

D, S

CLK1

, S

IN2

, S

CLK2

Hysteresis

RESET

"H" input current

, P1

, P3

"H" input current

, P4

, P5

, P6

, P7

"H" input current

RESET

"H" input current

"L" input current

, P1

, P3

, P7

"L" input current

, P4

, P5

, P6

, P7

"L" input current

RESET

"L" input current

RAM hold voltage

Symbol

Parameter

Limits

Min.

Unit

0.5

4.0

Typ.

Max.

= 0.1 mA

= 25

= 2.5 V

= 5 mA

= 1.25 mA

= 2.5 V

= 5 mA

= 1.25 mA

= 2.5 V

= 10 mA

= 2.5 mA

= 2.5 V

RESET: V

=2.5 V to 5.5 V

= V

Pull-downs "off"

= 5.0 V, V

= V

Pull-downs "on"

= 3.0 V, V

= V

Pull-downs "on"

= V

Pull-ups "off"

= 5.0 V, V

= V

Pull-ups "on"

= 3.0 V, V

= V

Pull-ups "on"

= V

When clock is stopped

Test conditions

T+

RAM

2.0

1.0

2.0

0.5

1.0

6.0

2.0

0.5

1.0

2.0

0.5

1.0

5.0

140

5.0

140

5.0

5.5

ELECTRICAL CHARACTERISTICS

=4.0 to 5.5 V, T

= 20 to 85

C, unless otherwise noted.)

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

All oscillation stopped
(in STP state)
Output transistors "off"

Symbol

Parameter

Limits

Min.

Unit

ELECTRICAL CHARACTERISTICS

=2.5 to 5.5 V, T

= 20 to 85

C, unless otherwise noted.)

Typ.

Max.

= 25

= 85

Test conditions

Power source current

· High-speed mode, V

= 5 V

f(X

) = 8 MHz

f(X

CIN

) = 32.768 kHz

Output transistors "off"

· High-speed mode, V

= 5 V

f(X

) = 8 MHz (in WIT state)

f(X

CIN

) = 32.768 kHz

Output transistors "off"

· Low-speed mode, V

= 5V, Ta

f(X

) = stopped

f(X

CIN

) = 32.768 kHz

Output transistors "off"

· Low-speed mode, V

= 5 V, Ta = 25

f(X

) = stopped

f(X

CIN

) = 32.768 kHz (in WIT state)

Output transistors "off"

· Low-speed mode, V

= 3 V, Ta

f(X

) = stopped

f(X

CIN

) = 32.768 kHz

Output transistors "off"

· Low-speed mode, V

= 3V, Ta = 25

f(X

) = stopped

f(X

CIN

) = 32.768 kHz (in WIT state)

Output transistors "off"

6.4

1.6

7.0

4.5

0.1

3.2

14.0

9.0

1.0

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

Note: When f(X

) = 8 MHz and bit 6 of address 001A

is "1" (clock synchronous).

Divide this value by four when f(X

) = 8 MHz and bit 6 of address 001A

is "0" (UART).

Reset input "L" pulse width

Main clock input cycle time (X

input)

Main clock input "H" pulse width

Main clock input "L" pulse width

CNTR

, CNTR

input cycle time

CNTR

, CNTR

input "H" pulse width

CNTR

, CNTR

input "L" pulse width

INT

to INT

input "H" pulse width

INT

to INT

input "L" pulse width

Serial I/O1 clock input cycle time (Note)

Serial I/O1 clock input "H" pulse width (Note)

Serial I/O1 clock input "L" pulse width (Note)

Serial I/O1 input set up time

Serial I/O1 input hold time

Serial I/O2 clock input cycle time

Serial I/O2 clock input "H" pulse width

Serial I/O2 clock input "L" pulse width

Serial I/O2 input set up time

Serial I/O2 input hold time

w(RESET)

c(X

)

wH(X

)

wL(X

)

c(CNTR)

wH(CNTR)

wL(CNTR)

wH(INT)

wL(INT)

c(S

CLK1

)

wH(S

CLK1

)

wL(S

CLK1

)

su(R

CLK1

)

h(S

CLK1

c(S

CLK2

)

wH(S

CLK2

)

wL(S

CLK2

)

su(S

IN2

CLK2

)

h(S

CLK2

IN2

)

Symbol

Parameter

Limits

Min.

Unit

TIMING REQUIREMENTS 1

= 4.0 to 5.5 V, V

SS =

0 V, T

= 20 to 85

C, unless otherwise noted.)

125

250

105

800

370

220

100

1000

400

200

Typ.

Max.

Reset input "L" pulse width

Main clock input cycle time (X

input)

Main clock input "H" pulse width

Main clock input "L" pulse width

CNTR

, CNTR

input cycle time

CNTR

, CNTR

input "H" pulse width

CNTR

, CNTR

input "L" pulse width

INT

to INT

input "H" pulse width

INT

to INT

input "L" pulse width

Serial I/O1 clock input cycle time (Note)

Serial I/O1 clock input "H" pulse width (Note)

Serial I/O1 clock input "L" pulse width (Note)

Serial I/O1 input set up time

Serial I/O1 input hold time

Serial I/O2 clock input cycle time

Serial I/O2 clock input "H" pulse width

Serial I/O2 clock input "L" pulse width

Serial I/O2 input set up time

Serial I/O2 input hold time

w(RESET)

c(X

)

wH(X

)

wL(X

)

c(CNTR)

wH(CNTR)

wL(CNTR)

wH(INT)

wL(INT)

c(S

CLK1

)

wH(S

CLK1

)

wL(S

CLK1

)

su(R

CLK1

)

h(S

CLK1

c(S

CLK2

)

wH(S

CLK2

)

wL(S

CLK2

)

su(S

IN2

CLK2

)

h(S

CLK2

IN2

)

Symbol

Parameter

Limits

Min.

Unit

TIMING REQUIREMENTS 2

= 2.5 to 4.0 V, V

SS =

0 V, T

= 20 to 85

C, unless otherwise noted.)

125

500/

250/

2)20

250/

2)20

230

2000

950

400

200

2000

950

400

300

Typ.

Max.

Note: When f(X

) = 2 MHz and bit 6 of address 001A

is "1" (clock synchronous).

Divide this value by four when f(X

) = 2 MHz and bit 6 of address 001A

is "0" (UART).

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

Serial I/O1 clock output "H" pulse width

Serial I/O1 clock output "L" pulse width

Serial I/O1 output delay time (Note 1)

Serial I/O1 output valid time (Note 1)

Serial I/O1 clock output rising time

Serial I/O1 clock output falling time

Serial I/O2 clock output "H" pulse width

Serial I/O2 clock output "L" pulse width

Serial I/O2 output delay time

Serial I/O2 output valid time

Serial I/O2 clock output falling time

CMOS output rising time (Note 2)

CMOS output falling time (Note 2)

140

0.2

(

CLK2

)

Symbol

Parameter

Limits

Min.

Unit

SWITCHING CHARACTERISTICS 1

= 4.0 to 5.5 V, V

SS =

0 V, T

= 20 to 85

C, unless otherwise noted.)

c(S

CLK1

)

/230

c(S

CLK1

)

/230

c(S

CLK2

)

/2160

c(S

CLK2

)

/2160

Typ.

Max.

wH(S

CLK1

)

wL(S

CLK1

)

d(S

CLK1

v(S

CLK1

r(S

CLK1

)

f(S

CLK1

)

wH(S

CLK2

)

wL(S

CLK2

)

d(S

CLK2

OUT2

)

v(S

CLK2

OUT2

)

f(S

CLK2

)

r(CMOS)

f(CMOS)

Notes1: When the P4

D P-channel output disable bit of the UART control register (bit 4 of address 001B

) is "0".

2: X

OUT

and X

COUT

pins are excluded.

Serial I/O1 clock output "H" pulse width

Serial I/O1 clock output "L" pulse width

Serial I/O1 output delay time (Note 1)

Serial I/O1 output valid time (Note 1)

Serial I/O1 clock output rising time

Serial I/O1 clock output falling time

Serial I/O2 clock output "H" pulse width

Serial I/O2 clock output "L" pulse width

Serial I/O2 output delay time

Serial I/O2 output valid time

Serial I/O2 clock output falling time

CMOS output rising time (Note 2)

CMOS output falling time (Note 2)

350

0.2

CLK2

)

Symbol

Parameter

Limits

Min.

Unit

SWITCHING CHARACTERISTICS 2

= 2.5 to 4.0 V, V

SS =

0 V, T

= 20 to 85

C, unless otherwise noted.)

c(S

CLK1

)

/250

c(S

CLK1

)

/250

c(S

CLK2

)

/2240

c(S

CLK2

)

/2240

Max.

wH(S

CLK1

)

wL(S

CLK1

)

d(S

CLK1

v(S

CLK1

r(S

CLK1

)

f(S

CLK1

)

wH(S

CLK2

)

wL(S

CLK2

)

d(S

CLK2

OUT2

)

v(S

CLK2

OUT2

)

f(S

CLK2

)

r(CMOS)

f(CMOS)

Notes1:When the P4

D P-channel output disable bit of the UART control register (bit 4 of address 001B

) is "0".

2: X

OUT

and X

COUT

pins are excluded.

Typ.

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

ABSOLUTE MAXIMUM RATINGS (Extended Operating Temperature Version)

RECOMMENDED OPERATING CONDITIONS (Extended Operating Temperature Version)

Power source voltage

Input voltage P0

, P1

, P2

, P4

, P5

, P6

, P7

Input voltage V

Input voltage RESET, X

Output voltage P0

, P1

Output voltage P3

Output voltage P2

, P4

, P5

, P6

, P7

Output voltage SEG

SEG

Output voltage X

OUT

Power dissipation

Operating temperature

Storage temperature

Topr

Tstg

Symbol

Parameter

Conditions

Ratings

0.3 to 7.0

0.3 to V

+0.3

0.3 to V

to V

+0.3

0.3 to V

+0.3

0.3 to V

+0.3

0.3 to V

+0.3

0.3 to V

+0.3

0.3 to V

+0.3

0.3 to V

+0.3

0.3 to V

+0.3

300

40 to 85

65 to 150

Unit

All voltages are based on V

Output transistors are cut off.

At output port

At segment output

= 25

= 3.0 to 5.5 V, T

= 40 to 20

C and V

= 2.5 to 5.5 V, T

= 20 to 85

C, unless otherwise noted.)

5.5

5.5
5.5

High-speed mode f(X

)=8 MHz

Middle-speed mode

Power source voltage

f(X

)=8 MHz

Low-speed mode

Power source voltage

"H" input voltage

, P1

, P3

, P4

, P5

, P6

, P7

(CM

=0)

"H" input voltage

, P4

, P5

"H" input voltage

RESET

"H" input voltage

"L" input voltage

, P1

, P3

, P4

, P5

, P6

, P7

(CM

=0)

"L" input voltage

, P4

, P5

Symbol

Parameter

Limits

Min.

Unit

4.0

2.5

3.0

5.0

Typ.

Max.

= 20 to 85

= 40 to 20

= 20 to 85

= 40 to 20

2.5

3.0

0.7 V

0.8 V

5.0

5.5

0.3 V

0.2 V

"L" input voltage

RESET

"L" input voltage

5.0

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

RECOMMENDED OPERATING CONDITIONS (Extended Operating Temperature Version)

= 3.0 to 5.5 V, T

= 40 to 20

C and V

= 2.5 to 5.5 V, T

= 20 to 85

C unless otherwise noted.)

Notes

1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an av

erage value measured over 100 ms. The total peak current is the peak value of all the currents.

CIN

) is less than

f(X

)/3.

1.0

2.5

5.0

8.0

(4XV

8.0

"H" total peak output current

, P1

, P2

(Note 1)

"H" total peak output current

,P5

, P6

, P7

(Note 1)

"L" total peak output current

, P1

, P2

(Note 1)

"L" total peak output current

,P5

, P6

, P7

(Note 1)

"H" total average output current P0

, P1

, P2

(Note 1)

"H" total average output current P4

,P5

, P6

, P7

(Note 1)

"L" total average output current

, P1

, P2

(Note 1)

"L" total average output current

,P5

, P6

, P7

(Note 1)

"H" peak output current

, P1

, P2

, P4

, P5

, P6

, P7

(Note 2)

"L" peak output current

, P1

(Note 2)

"L" peak output current

, P4

, P5

, P6

, P7

(Note 2)

"H" average output current

, P1

(Note 3)

"H" average output current

, P4

, P5

, P6

, P7

(Note 3)

"L" average output current

, P1

(Note 3)

"L" average output current

, P4

, P5

, P6

, P7

(Note 3)

Clock input frequency

for timers X and Y

(duty cycle 50 %)

Main clock input oscillation
frequency (Note 4)

Sub-clock input oscillation frequency (Note 4, 5)

OH(peak)

OL(peak)

OH(avg)

OL(avg)

OH(peak)

OL(peak)

OH(avg)

OL(avg)

f(CNTR

)

f(CNTR

)

f(X

)

f(X

CIN

)

Symbol

Parameter

Limits

Min.

MHz

kHz

Unit

Typ.

Max.

4.0 V

5.5 V

4.0 V

32.768

High-speed mode (4.0 V

5.5 V)

High-speed mode (V

4.0 V)

Middle-speed mode

4.0

(2XV

MHz

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

Note : When "1" is set to port X

switch bit (bit 4 of address 003B

) of CPU mode register, the drive ability of port P7

is different from the

value above mentioned.

"H" output voltage P0

, P1

, P3

"H" output voltage P2

, P4

,P5

, P6

, P7

(Note)

"L" output voltage

, P1

, P3

"L" output voltage

, P4

, P5

, P6

, P7

(Note)

Hysteresis

CNTR

, CNTR

, INT

INT

Hysteresis

D, S

CLK1

, S

IN2

, S

CLK2

Hysteresis

RESET

"H" input current

, P1

, P3

"H" input current

, P4

, P5

, P6

, P7

"H" input current

RESET

"H" input current

"L" input current

, P1

, P3

, P7

"L" input current

, P4

, P5

, P6

, P7

"L" input current

RESET

"L" input current

RAM hold voltage

Symbol

Parameter

Limits

Min.

Unit

=2.5 to 5.5 V, T

= 20 to 85

C, and V

=3.0 to 5.5 V, T

= 40 to 20

C, unless otherwise noted.)

ELECTRICAL CHARACTERISTICS (Extended Operating Temperature Version)

0.5

4.0

Typ.

Max.

= 2.5 mA

= 0.6 mA

= 3.0 V

= 5 mA

= 1.25 mA

= 3.0 V

= 5 mA

= 1.25 mA

= 3.0 V

= 10 mA

= 2.5 mA

= 3.0 V

RESET: V

=3.0 V to 5.5 V

= V

Pull-downs "off"

= 5.0 V, V

= V

Pull-downs "on"

= 3.0 V, V

= V

Pull-downs "on"

= V

Pull-ups "off"

= 5.0 V, V

= V

Pull-ups "on"

= 3.0 V, V

= V

Pull-ups "on"

= V

When clock is stopped

Test conditions

T+

RAM

2.0

0.9

2.0

0.5

0.9

6.0

2.0

0.5

1.1

2.0

0.5

1.1

5.0

170

5.0

140

5.0

5.5

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

All oscillation stopped
(in STP state)
Output transistors "off"

Symbol

Parameter

Limits

Min.

Unit

ELECTRICAL CHARACTERISTICS (Extended Operating Temperature Version)

=3.0 to 5.5 V, T

= 40 to 20

C and V

=2.5 to 5.5 V, T

= 20 to 85

C, unless otherwise noted.)

Typ.

Max.

= 25

= 85

Test conditions

Power source current

· High-speed mode, V

= 5 V

f(X

) = 8 MHz

f(X

CIN

) = 32.768 kHz

Output transistors "off"

· High-speed mode, V

= 5 V

f(X

) = 8 MHz (in WIT state)

f(X

CIN

) = 32.768 kHz

Output transistors "off"

· Low-speed mode, V

= 5V, Ta

f(X

) = stopped

f(X

CIN

) = 32.768 kHz

Output transistors "off"

· Low-speed mode, V

= 5 V, Ta = 25

f(X

) = stopped

f(X

CIN

) = 32.768 kHz (in WIT state)

Output transistors "off"

· Low-speed mode, V

= 3 V, Ta

f(X

) = stopped

f(X

CIN

) = 32.768 kHz

Output transistors "off"

· Low-speed mode, V

= 3V, Ta = 25

f(X

) = stopped

f(X

CIN

) = 32.768 kHz (in WIT state)

Output transistors "off"

6.4

1.6

7.0

4.5

0.1

3.2

14.0

9.0

1.0

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

Note: When f(X

) = 8 MHz and bit 6 of address 001A

is "1" (clock synchronous).

Divide this value by four when f(X

) = 8 MHz and bit 6 of address 001A

is "0" (UART).

Reset input "L" pulse width

Main clock input cycle time (X

input)

Main clock input "H" pulse width

Main clock input "L" pulse width

CNTR

, CNTR

input cycle time

CNTR

, CNTR

input "H" pulse width

CNTR

, CNTR

input "L" pulse width

INT

to INT

input "H" pulse width

INT

to INT

input "L" pulse width

Serial I/O1 clock input cycle time (Note)

Serial I/O1 clock input "H" pulse width (Note)

Serial I/O1 clock input "L" pulse width (Note)

Serial I/O1 input set up time

Serial I/O1 input hold time

Serial I/O2 clock input cycle time

Serial I/O2 clock input "H" pulse width

Serial I/O2 clock input "L" pulse width

Serial I/O2 input set up time

Serial I/O2 input hold time

w(RESET)

c(X

)

wH(X

)

wL(X

)

c(CNTR)

wH(CNTR)

wL(CNTR)

wH(INT)

wL(INT)

c(S

CLK1

)

wH(S

CLK1

)

wL(S

CLK1

)

su(R

CLK1

)

h(S

CLK1

c(S

CLK2

)

wH(S

CLK2

)

wL(S

CLK2

)

su(S

IN2

CLK2

)

h(S

CLK2

IN2

)

Symbol

Parameter

Limits

Min.

Unit

= 4.0 to 5.5 V, V

SS =

0 V, T

= 40 to 85

C, unless otherwise noted.)

125

250

105

800

370

220

100

1000

400

200

Typ.

Max.

Reset input "L" pulse width

Main clock input cycle time (X

input)

Main clock input "H" pulse width

Main clock input "L" pulse width

CNTR

, CNTR

input cycle time

CNTR

, CNTR

input "H" pulse width

CNTR

, CNTR

input "L" pulse width

INT

to INT

input "H" pulse width

INT

to INT

input "L" pulse width

Serial I/O1 clock input cycle time (Note)

Serial I/O1 clock input "H" pulse width (Note)

Serial I/O1 clock input "L" pulse width (Note)

Serial I/O1 input set up time

Serial I/O1 input hold time

Serial I/O2 clock input cycle time

Serial I/O2 clock input "H" pulse width

Serial I/O2 clock input "L" pulse width

Serial I/O2 input set up time

Serial I/O2 input hold time

w(RESET)

c(X

)

wH(X

)

wL(X

)

c(CNTR)

wH(CNTR)

wL(CNTR)

wH(INT)

wL(INT)

c(S

CLK1

)

wH(S

CLK1

)

wL(S

CLK1

)

su(R

CLK1

)

h(S

CLK1

c(S

CLK2

)

wH(S

CLK2

)

wL(S

CLK2

)

su(S

IN2

CLK2

)

h(S

CLK2

IN2

)

Symbol

Parameter

Limits

Min.

Unit

= 2.5 to 4.0 V, V

SS =

0 V, T

= 20 to 85

C, and V

= 3.0 to 4.0 V, V

SS =

0 V, T

= 40 to 20

C, unless otherwise noted.)

125

500/

250/

2)20

250/

2)20

230

2000

950

400

200

2000

950

400

300

Typ.

Max.

Note: When f(X

) = 2 MHz and bit 6 of address 001A

is "1" (clock synchronous).

Divide this value by four when f(X

) = 2 MHz and bit 6 of address 001A

is "0" (UART).

TIMING REQUIREMENTS 1 (Extended Operating Temperature Version)

TIMING REQUIREMENTS 2 (Extended Operating Temperature Version)

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

Serial I/O1 clock output "H" pulse width

Serial I/O1 clock output "L" pulse width

Serial I/O1 output delay time (Note 1)

Serial I/O1 output valid time (Note 1)

Serial I/O1 clock output rising time

Serial I/O1 clock output falling time

Serial I/O2 clock output "H" pulse width

Serial I/O2 clock output "L" pulse width

Serial I/O2 output delay time

Serial I/O2 output valid time

Serial I/O2 clock output falling time

CMOS output rising time (Note 2)

CMOS output falling time (Note 2)

140

0.2

CLK2

)

Symbol

Parameter

Limits

Min.

Unit

= 4.0 to 5.5 V, V

SS =

0 V, T

= 40 to 85

C, unless otherwise noted.)

c(S

CLK1

)

/230

c(S

CLK1

)

/230

c(S

CLK2

)

/2160

c(S

CLK2

)

/2160

Typ.

Max.

wH(S

CLK1

)

wL(S

CLK1

)

d(S

CLK1

v(S

CLK1

r(S

CLK1

)

f(S

CLK1

)

wH(S

CLK2

)

wL(S

CLK2

)

d(S

CLK2

OUT2

)

v(S

CLK2

OUT2

)

f(S

CLK2

)

r(CMOS)

f(CMOS)

Notes1: When the P4

D P-channel output disable bit of the UART control register (bit 4 of address 001B

) is "0".

2: X

OUT

and X

COUT

pins are excluded.

Serial I/O1 clock output "H" pulse width

Serial I/O1 clock output "L" pulse width

Serial I/O1 output delay time (Note 1)

Serial I/O1 output valid time (Note 1)

Serial I/O1 clock output rising time

Serial I/O1 clock output falling time

Serial I/O2 clock output "H" pulse width

Serial I/O2 clock output "L" pulse width

Serial I/O2 output delay time

Serial I/O2 output valid time

Serial I/O2 clock output falling time

CMOS output rising time (Note 2)

CMOS output falling time (Note 2)

350

0.2

CLK2

)

Symbol

Parameter

Limits

Min.

Unit

= 2.5 to 4.0 V, V

SS =

0 V, T

= 20 to 85

C, and V

= 3.0 to 4.0 V, T

= 40 to 20

C, unless otherwise noted.)

c(S

CLK1

)

/250

c(S

CLK1

)

/250

c(S

CLK2

)

/2240

c(S

CLK2

)

/2240

Max.

wH(S

CLK1

)

wL(S

CLK1

)

d(S

CLK1

v(S

CLK1

r(S

CLK1

)

f(S

CLK1

)

wH(S

CLK2

)

wL(S

CLK2

)

d(S

CLK2

OUT2

)

v(S

CLK2

OUT2

)

f(S

CLK2

)

r(CMOS)

f(CMOS)

Notes1: When the P4

D P-channel output disable bit of the UART control register (bit 4 of address 001B

) is "0".

2: X

OUT

and X

COUT

pins are excluded.

Typ.

SWITCHING CHARACTERISTICS 1 (Extended Operating Temperature Version)

SWITCHING CHARACTERISTICS 2 (Extended Operating Temperature Version)

Measurement output pin

100pF

CMOS output

Note

When bit 4 of the UART

control register (address 001B

) is "1".

(N-channel open-drain output mode)

Measurement output pin

100pF

N-channel open-drain output (Note)

Fig.40 Circuit for measuring output switching characteristics

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

Power source voltage

Input voltage P0

, P1

, P2

, P4

, P5

, P6

, P7

Input voltage V

Input voltage RESET, X

Output voltage P0

, P1

Output voltage P3

Output voltage P2

, P4

, P5

, P6

, P7

Output voltage SEG

SEG

Output voltage X

OUT

Power dissipation

Operating temperature

Storage temperature

Topr

Tstg

Symbol

Parameter

Conditions

Ratings

0.3 to 7.0

0.3 to V

+0.3

0.3 to V

to V

+0.3

0.3 to V

+0.3

0.3 to V

+0.3

0.3 to V

+0.3

0.3 to V

+0.3

0.3 to V

+0.3

0.3 to V

+0.3

0.3 to V

+0.3

300

20 to 85

40 to 150

Unit

All voltages are based on V

Output transistors are cut off.

At output port

At segment output

= 25

= 2.2 to 5.5 V, T

= 20 to 85

C, unless otherwise noted.)

5.5

0.3 V

0.2 V

High-speed mode f(X

)=8 MHz

Power source voltage

Middle-speed mode f(X

)=8 MHz

Low-speed mode

Power source voltage

"H" input voltage

, P1

, P3

, P4

, P5

, P6

, P7

(CM

=0)

"H" input voltage

, P4

, P5

"H" input voltage

RESET

"H" input voltage

"L" input voltage

, P1

, P3

, P4

, P5

, P6

, P7

(CM

=0)

"L" input voltage

, P4

, P5

"L" input voltage

RESET

"L" input voltage

Symbol

Parameter

Limits

Min.

Unit

4.0

2.2

0.7 V

0.8 V

5.0

Typ.

Max.

ABSOLUTE MAXIMUM RATINGS (Low Power Source Voltage Version)

RECOMMENDED OPERATING CONDITIONS (Low Power Source Voltage Version)

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

RECOMMENDED OPERATING CONDITIONS (Low Power Source Voltage Version)

= 2.2 to 5.5 V, T

= 20 to 85

C, unless otherwise noted.)

Notes

1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an av

erage value measured over 100 ms. The total peak current is the peak value of all the currents.

CIN

) is less than

f(X

)/3.

1.0

2.5

5.0

8.0

"H" total peak output current

, P1

, P2

(Note 1)

"H" total peak output current

,P5

, P6

, P7

(Note 1)

"L" total peak output current

, P1

, P2

(Note 1)

"L" total peak output current

,P5

, P6

, P7

(Note 1)

"H" total average output current P0

, P1

, P2

(Note 1)

"H" total average output current P4

,P5

, P6

, P7

(Note 1)

"L" total average output current

, P1

, P2

(Note 1)

"L" total average output current

,P5

, P6

, P7

(Note 1)

"H" peak output current

, P1

, P2

, P4

, P5

, P6

, P7

(Note 2)

"L" peak output current

, P1

(Note 2)

"L" peak output current

, P4

, P5

, P6

, P7

(Note 2)

"H" average output current

, P1

(Note 3)

"H" average output current

, P4

, P5

, P6

, P7

(Note 3)

"L" average output current

, P1

(Note 3)

"L" average output current

, P4

, P5

, P6

, P7

(Note 3)

Clock input frequency

for timers X and Y

(duty cycle 50 %)

Main clock input oscillation
frequency (Note 4)

Sub-clock input oscillation frequency (Note 4, 5)

OH(peak)

OL(peak)

OH(avg)

OL(avg)

OH(peak)

OL(peak)

OH(avg)

OL(avg)

f(CNTR

)

f(CNTR

)

f(X

)

f(X

CIN

)

Symbol

Parameter

Limits

Min.

MHz

kHz

Unit

Typ.

Max.

4.0 V

5.5 V

4.0 V

32.768

High-speed mode (4.0 V

5.5 V)

High-speed mode (V

4.0 V)

Middle-speed mode

4.0

(10XV

MHz

(20XV

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

Note : When "1" is set to port X

switch bit (bit 4 of address 003B

) of CPU mode register, the drive ability of port P7

is different from the

value above mentioned.

"H" output voltage P0

, P1

, P3

"H" output voltage P2

, P4

,P5

, P6

, P7

(Note)

"L" output voltage

, P1

, P3

"L" output voltage

, P4

, P5

, P6

, P7

(Note)

Hysteresis

CNTR

, CNTR

, INT

INT

, P2

Hysteresis

D, S

CLK1

, S

IN2

, S

CLK2

Hysteresis

RESET

"H" input current

, P1

, P3

"H" input current

, P4

, P5

, P6

, P7

"H" input current

RESET

"H" input current

"L" input current

, P1

, P3

, P7

"L" input current

, P4

, P5

, P6

, P7

"L" input current

RESET

"L" input current

Symbol

Parameter

Limits

Min.

Unit

=4.0 to 5.5 V, T

= 20 to 85

C, unless otherwise noted.)

0.5

8.0

4.0

8.0

Typ.

Max.

= 0.1 mA

= 25

= 2.2 V

= 5 mA

= 1.25 mA

= 2.2 V

= 5 mA

= 1.25 mA

= 2.2 V

= 10 mA

= 2.5 mA

= 2.2 V

RESET: V

=2.2 V to 5.5 V

= V

Pull-downs "off"

= 5.0 V, V

= V

Pull-downs "on"

= 3.0 V, V

= V

Pull-downs "on"

= V

Pull-ups "off"

= 5.0 V, V

= V

Pull-ups "on"

= 3.0 V, V

= V

Pull-ups "on"

= V

Test conditions

T+

2.0

1.0

2.0

0.5

1.0

6.0

2.0

0.5

1.1

2.0

0.5

1.0

5.0

170

5.0

140

5.0

ELECTRICAL CHARACTERISTICS (Low Power Source Voltage Version)

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

All oscillation stopped
(in STP state)
Output transistors "off"

Symbol

RAM

Parameter

RAM hold voltage

Limits

Min.

2.0

Unit

ELECTRICAL CHARACTERISTICS (Low Power Source Voltage Version)

=2.2 to 5.5 V, T

= 20 to 85

C, unless otherwise noted.)

Typ.

Max.

5.5

= 25

= 85

Test conditions

Power source current

· High-speed mode, V

= 5 V

f(X

) = 8 MHz

f(X

CIN

) = 32.768 kHz

Output transistors "off"

· High-speed mode, V

= 5 V

f(X

) = 8 MHz (in WIT state)

f(X

CIN

) = 32.768 kHz

Output transistors "off"

· Low-speed mode, V

= 5V, Ta

f(X

) = stopped

f(X

CIN

) = 32.768 kHz

Output transistors "off"

· Low-speed mode, V

= 5 V, Ta = 25

f(X

) = stopped

f(X

CIN

) = 32.768 kHz (in WIT state)

Output transistors "off"

· Low-speed mode, V

= 3 V, Ta

f(X

) = stopped

f(X

CIN

) = 32.768 kHz

Output transistors "off"

· Low-speed mode, V

= 3V, Ta = 25

f(X

) = stopped

f(X

CIN

) = 32.768 kHz (in WIT state)

Output transistors "off"

6.4

1.6

7.0

4.5

0.2

3.2

14.0

9.0

2.0

When clock is stopped

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

_____

w(RESET)

c(X

)

wH(X

)

wL(X

)

c(CNTR)

wH(CNTR)

wL(CNTR)

wH(INT)

wL(INT)

c(S

CLK1

)

wH(S

CLK1

)

wL(S

CLK1

)

su(R

CLK1

)

h(S

CLK1

c(S

CLK2

)

wH(S

CLK2

)

wL(S

CLK2

)

su(S

IN2

CLK2

)

h(S

CLK2

IN2

)

Note: When f(X

) = 8 MHz and bit 6 of address 001A

is "1" (clock synchronous).

Divide this value by four when f(X

) = 8 MHz and bit 6 of address 001A

is "0" (UART).

Reset input "L" pulse width

Main clock input cycle time (X

input)

Main clock input "H" pulse width

Main clock input "L" pulse width

CNTR

, CNTR

input cycle time

CNTR

, CNTR

input "H" pulse width

CNTR

, CNTR

input "L" pulse width

INT

to INT

input "H" pulse width

INT

to INT

input "L" pulse width

Serial I/O1 clock input cycle time (Note)

Serial I/O1 clock input "H" pulse width (Note)

Serial I/O1 clock input "L" pulse width (Note)

Serial I/O1 input set up time

Serial I/O1 input hold time

Serial I/O2 clock input cycle time

Serial I/O2 clock input "H" pulse width

Serial I/O2 clock input "L" pulse width

Serial I/O2 input set up time

Serial I/O2 input hold time

Symbol

Parameter

Limits

Min.

Unit

= 4.0 to 5.5 V, V

SS =

0 V, T

= 20 to 85

C, unless otherwise noted.)

TIMING REQUIREMENTS 1 (Low Power Source Voltage Version)

125

250

105

800

370

220

100

1000

400

200

Typ.

Max.

Reset input "L" pulse width

Main clock iuput cycle time (X

input)

Main clock input "H" pulse width

Main clock input "L" pulse width

CNTR

, CNTR

input cycle time

CNTR

, CNTR

input "H" pulse width

CNTR

, CNTR

input "L" pulse width

INT

to INT

input "H" pulse width

INT

to INT

input "L" pulse width

Serial I/O1 clock input cycle time (Note)

Serial I/O1 clock input "H" pulse width (Note)

Serial I/O1 clock input "L" pulse width (Note)

Serial I/O1 input set up time

Serial I/O1 input hold time

Serial I/O2 clock input cycle time

Serial I/O2 clock input "H" pulse width

Serial I/O2 clock input "L" pulse width

Serial I/O2 input set up time

Serial I/O2 input hold time

_____

w(RESET)

c(X

)

wH(X

)

wL(X

)

c(CNTR)

wH(CNTR)

wL(CNTR)

wH(INT)

wL(INT)

c(S

CLK1

)

wH(S

CLK1

)

wL(S

CLK1

)

su(R

CLK1

)

h(S

CLK1

c(S

CLK2

)

wH(S

CLK2

)

wL(S

CLK2

)

su(S

IN2

CLK2

)

h(S

CLK2

IN2

)

Symbol

Parameter

Limits

Min.

Unit

= 2.5 to 4.0 V, V

SS =

0 V, T

= 20 to 85

C, unless otherwise noted.)

125

900/

0.4)

450/

0.4)20

450/

0.4)20

230

2000

950

400

200

2000

950

400

300

Typ.

Max.

Note: When f(X

) = 2 MHz and bit 6 of address 001A

is "1" (clock synchronous).

Divide this value by four when f(X

) = 2 MHz and bit 6 of address 001A

is "0" (UART).

TIMING REQUIREMENTS 2 (Low Power Source Voltage Version)

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

Measurement output pin

100pF

CMOS output

Note

When bit 4 of the UART

control register (address 001B

) is "1".

(N-channel open-drain output mode)

Measurement output pin

100pF

N-channel open-drain output (Note)

Serial I/O1 clock output "H" pulse width

Serial I/O1 clock output "L" pulse width

Serial I/O1 output delay time (Note 1)

Serial I/O1 output valid time (Note 1)

Serial I/O1 clock output rising time

Serial I/O1 clock output falling time

Serial I/O2 clock output "H" pulse width

Serial I/O2 clock output "L" pulse width

Serial I/O2 output delay time

Serial I/O2 output valid time

Serial I/O2 clock output falling time

CMOS output rising time (Note 2)

CMOS output falling time (Note 2)

140

0.2

CLK2

)

Symbol

Parameter

Limits

Min.

Unit

= 4.0 to 5.5 V, V

SS =

0 V, T

= 20 to 85

C, unless otherwise noted.)

c(S

CLK1

)

/230

c(S

CLK1

)

/230

c(S

CLK2

)

/2160

c(S

CLK2

)

/2160

Typ.

Max.

wH(S

CLK1

)

wL(S

CLK1

)

d(S

CLK1

v(S

CLK1

r(S

CLK1

)

f(S

CLK1

)

wH(S

CLK2

)

wL(S

CLK2

)

d(S

CLK2

OUT2

)

v(S

CLK2

OUT2

)

f(S

CLK2

)

r(CMOS)

f(CMOS)

Notes 1: When the P4

D P-channel output disable bit of the UART control register (bit 4 of address 001B

) is "0".

2: X

OUT

and X

COUT

pins are excluded.

SWITCHING CHARACTERISTICS 1 (Low Power Source Voltage Version)

Serial I/O1 clock output "H" pulse width

Serial I/O1 clock output "L" pulse width

Serial I/O1 output delay time (Note 1)

Serial I/O1 output valid time (Note 1)

Serial I/O1 clock output rising time

Serial I/O1 clock output falling time

Serial I/O2 clock output "H" pulse width

Serial I/O2 clock output "L" pulse width

Serial I/O2 output delay time

Serial I/O2 output valid time

Serial I/O2 clock output falling time

CMOS output rising time (Note 2)

CMOS output falling time (Note 2)

350

0.2

CLK2

)

Symbol

Parameter

Limits

Min.

Unit

= 2.2 to 4.0 V, V

SS =

0 V, T

= 20 to 85

C, unless otherwise noted.)

c(S

CLK1

)

/250

c(S

CLK1

)

/250

c(S

CLK2

)

/2240

c(S

CLK2

)

/2240

Max.

wH(S

CLK1

)

wL(S

CLK1

)

d(S

CLK1

v(S

CLK1

r(S

CLK1

)

f(S

CLK1

)

wH(S

CLK2

)

wL(S

CLK2

)

d(S

CLK2

OUT2

)

v(S

CLK2

OUT2

)

f(S

CLK2

)

r(CMOS)

f(CMOS)

Notes 1: When the P4

D P-channel output disable bit of the UART control register (bit 4 of address 001B

) is "0".

2: X

OUT

and X

COUT

pins are excluded.

SWITCHING CHARACTERISTICS 2 (Low Power Source Voltage Version)

Typ.

Fig.41 Circuit for measuring output switching characteristics

© 1996 MITSUBISHI ELECTRIC CORP.
H-DF047-C KI-9609
New publication, effective Sep. 1996.
Specifications subject to change without notice.

Notes regarding these materials

These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.

Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts or circuit application examples
contained in these materials.

All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for the latest product information before purchasing a product listed herein.

Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for
transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.

The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.

If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the
approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.

Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.

Keep safety first in your circuit designs!

Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of
substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.

MITSUBISHI MICROCOMPUTERS

3820Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 3820

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 3820

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 3820