Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
1
M2V56S20ATP is a 4-bank x 16777216-word x 4-bit,
M2V56S30ATP is a 4-bank x 8388608-word x 8-bit,
M2V56S40ATP is a 4-bank x 4194304-word x 16-bit,
synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of
CLK. The M2V56S20/30/40ATP achieve very high speed data rate up to 100MHz (-7) , 133MHz (-6),
166MHz(-5) and are suitable for main memory or graphic memory in computer systems.
- Single 3.3v0.3V power supply
- Max. Clock frequency -5:PC166<3-3-3> / -6:PC133<3-3-3> / -7:PC100<2-2-2>
- Fully Synchronous operation referenced to clock rising edge
- Single Data Rate
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/full page (programmable)
- Burst type- sequential / interleave (programmable)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- 8192 refresh cycles /64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)
- LVTTL Interface
- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch
Some of contents are subject to change without notice.
DESCRIPTION
FEATURES
Standard
PC100 (CL2)
PC133 (CL3)
PC133 (CL2)
166MHz
133MHz
100MHz
100MHz
100MHz
133MHz
M2V56S20/30/40ATP-7,-7L
M2V56S20/30/40ATP-6,-6L
M2V56S20/30/40ATP-5,-5L
Max. Frequency
@CL3
Max. Frequency
@CL2
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
2
CLK
: Master Clock
CKE
: Clock Enable
/CS
: Chip Select
/RAS
: Row Address Strobe
/CAS
: Column Address Strobe
/WE
: Write Enable
DQ0-15
: Data I/O
DQM, DQMU/L : Output Disable / Write Mask
A0-12
: Address Input
BA0,1
: Bank Address Input
Vdd
: Power Supply
VddQ
: Power Supply for Output
Vss
: Ground
VssQ
: Ground for Output
PIN CONFIGURATION
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Vdd
DQ0
VddQ
NC
DQ1
VssQ
NC
DQ2
VddQ
NC
DQ3
VssQ
NC
Vdd
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
Vdd
Vss
DQ15
VssQ
DQ14
DQ13
VddQ
DQ12
DQ11
VssQ
DQ10
DQ9
VddQ
DQ8
Vss
NC
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
Vss
Vss
DQ7
VssQ
NC
DQ6
VddQ
NC
DQ5
VssQ
NC
DQ4
VddQ
NC
Vss
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
Vss
Vss
NC
VssQ
NC
DQ3
VddQ
NC
NC
VssQ
NC
DQ2
VddQ
NC
Vss
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
Vss
Vdd
DQ0
VddQ
DQ1
DQ2
VssQ
DQ3
DQ4
VddQ
DQ5
DQ6
VssQ
DQ7
Vdd
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
Vdd
Vdd
NC
VddQ
NC
DQ0
VssQ
NC
NC
VddQ
NC
DQ1
VssQ
NC
Vdd
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
Vdd
x16
x8
x4
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
3
Package Type TP: TSOP(II)
BLOCK DIAGRAM
/CS /RAS /CAS /WE DQMU/L
Memory
Array
Bank #0
DQ0-3 (x4), 0-7 (x8), 0 - 15 (x16)
I/O Buffer
Memory
Array
Bank #1
Memory
Array
Bank #2
Memory
Array
Bank #3
Mode Register
Control Circuitry
Address Buffer
A0-12
BA0,1
Clock Buffer
CLK
CKE
Control Signal Buffer
Speed Grade
5: 166MHz@CL3, 133MHz@CL2
6: 133MHz@CL3, 100MHz@CL2
7: 100MHz@CL2
Type Designation Code
This rule is applied to only Synchronous DRAM family.
Mitsubishi Main Designation
Process Generation A:2nd. gen.
Function Reserved for Future Use
Organization 2 n 2: x4, 3: x8, 4: x16
SDRAM Data Rate Type S:Single Data Rate
Density 56: 256M bits
Interface V:LVTTL
Memory Style (DRAM)
M 2 V 56 S 4 0 A TP - 5 L
Power Grade L:Low Power, Space:Standard
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
4
VddQ and VssQ are supplied to the Output Buffers only.
Power Supply for the memory array and peripheral circuitry.
Din Mask / Output Disable: When DQMU/L is high in burst write, Din for
the current cycle is masked. When DQMU/L is high in burst read, Dout
is disabled at the next but one cycle.
Data In and Data out are referenced to the rising edge of CLK.
Combination of /RAS, /CAS, /WE defines basic commands.
A0-12 specify the Row / Column Address in conjunction with BA0,1.
The Row Address is specified by A0-12. The Column Address is
specified by A0-9,11. A10 is also used to indicate precharge option.
When A10 is high at a read / write command, an auto precharge is
performed. When A10 is high at a precharge command, all banks are
precharged.
Bank Address: BA0,1 specifies one of four banks to which a command
is applied. BA0,1 must be set with ACT, PRE, READ, WRITE
commands.
Input / Output
Power Supply
Power Supply
Input
Input
Input
Input
VddQ, VssQ
Vdd, Vss
DQM
DQMU/L
DQ0-15
BA0,1
A0-12
/RAS, /CAS, /WE
Chip Select: When /CS is high, any command means No Operation
Input
/CS
Clock Enable: CKE controls internal clock. When CKE is low, internal
clock for the following cycle is ceased. CKE is also used to select auto
/ self refresh. After self refresh mode is started, CKE becomes
asynchronous input. Self refresh is maintained as long as CKE is low.
Input
Master Clock: All other inputs are referenced to the rising edge of CLK.
Input
CKE
CLK
PIN FUNCTION
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
5
BASIC FUNCTIONS
The M2V56S20/30/40ATP provides basic functions, bank (row) activate, burst read / write, bank (row)
precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at
CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and
precharge option, respectively. To know the detailed definition of commands, please see the command
truth table.
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data appears after
/CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-
precharge,
READA
)
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written
is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write
(auto-precharge,
WRITEA
).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates burst read
/write operation. When A10 =H at this command, all banks are deactivated (precharge all,
PREA
).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address are generated internally. After this
command, the banks are precharged automatically.
/CS
Chip Select : L=select, H=deselect
/RAS
Command
/CAS
Command
/WE
Command
CKE
Refresh Option @refresh command
A10
Precharge Option @precharge or read/write command
CLK
define basic commands
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
6
COMMAND TRUTH TABLE
NOTE:
1. A7-9,11-12=L, A0-A6 =Mode
Address
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
COMMAND
MNEMONIC
CKE
n-1
CKE
n
/CS
/RAS /CAS
/WE BA0,1 A10
/AP
A0-9,
11-12
Deselect
DESEL
H
X
H
X
X
X
X
X
X
No Operation
NOP
H
X
L
H
H
H
X
X
X
Row Address Entry &
Bank Activate
ACT
H
X
L
L
H
H
V
V
V
Single Bank Precharge
PRE
H
X
L
L
H
L
V
L
X
Precharge All Banks
PREA
H
X
L
L
H
L
H
X
Column Address Entry
& Write
WRITE
H
X
L
H
L
L
V
L
V
Column Address Entry
& Write with
Auto-Precharge
WRITEA
H
X
L
H
L
L
V
H
V
Column Address Entry
& Read
READ
H
X
L
H
L
H
V
L
V
Column Address Entry
& Read with
Auto-Precharge
READA
H
X
L
H
L
H
V
H
V
Auto-Refresh
REFA
H
H
L
L
L
H
X
X
X
Self-Refresh Entry
REFS
H
L
L
L
L
H
X
X
X
Self-Refresh Exit
REFSX
L
H
H
X
X
X
X
X
X
L
H
L
H
H
H
X
X
X
Burst Terminate
TBST
H
X
L
H
H
L
X
X
X
Mode Register Set
MRS
H
X
L
L
L
L
L
L
V
X
note
1
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
7
FUNCTION TRUTH TABLE
Current State
/CS
/RAS /CAS
/WE
Address
Command
Action
IDLE
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
X
TBST
ILLEGAL*2
L
H
L
X
BA, CA, A10
READ / WRITE ILLEGAL*2
L
L
H
H
BA, RA
ACT
Bank Active, Latch RA
L
L
H
L
BA, A10
PRE / PREA
NOP*4
L
L
L
H
X
REFA
Auto-Refresh*5
L
L
L
L
Op-Code,
Mode-Add
MRS
Mode Register Set*5
ROW ACTIVE
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
X
TBST
NOP
L
H
L
H
BA, CA, A10
READ / READA
Begin Read, Latch CA,
Determine Auto-Precharge
L
H
L
L
BA, CA, A10
WRITE /
WRITEA
Begin Write, Latch CA,
Determine Auto-Precharge
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
Precharge / Precharge All
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
READ
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
X
TBST
Terminate Burst
L
H
L
H
BA, CA, A10
READ / READA
Terminate Burst, Latch CA,
Begin New Read, Determine
Auto-Precharge*3
L
H
L
L
BA, CA, A10
WRITE /
WRITEA
Terminate Burst, Latch CA,
Begin Write, Determine Auto-
Precharge*3
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
Terminate Burst, Precharge
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
8
FUNCTION TRUTH TABLE (continued)
Current State
/CS
/RAS /CAS
/WE
Address
Command
Action
WRITE
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
X
TBST
Terminate Burst
L
H
L
H
BA, CA, A10
READ / READA
Terminate Burst, Latch CA,
Begin Read, Determine Auto-
Precharge*3
L
H
L
L
BA, CA, A10
WRITE /
WRITEA
Terminate Burst, Latch CA,
Begin Write, Determine Auto-
Precharge*3
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
Terminate Burst, Precharge
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
READ with
AUTO
PRECHARGE
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
X
TBST
ILLEGAL
L
H
L
H
BA, CA, A10
READ / READA ILLEGAL
L
H
L
L
BA, CA, A10
WRITE /
WRITEA
ILLEGAL
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL*2
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
WRITE with
AUTO
PRECHARGE
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
X
TBST
ILLEGAL
L
H
L
H
BA, CA, A10
READ / READA ILLEGAL
L
H
L
L
BA, CA, A10
WRITE /
WRITEA
ILLEGAL
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL*2
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
9
FUNCTION TRUTH TABLE (continued)
Current State
/CS
/RAS /CAS
/WE
Address
Command
Action
PRE -
CHARGING
H
X
X
X
X
DESEL
NOP (Idle after tRP)
L
H
H
H
X
NOP
NOP (Idle after tRP)
L
H
H
L
X
TBST
ILLEGAL*2
L
H
L
X
BA, CA, A10
READ / WRITE ILLEGAL*2
L
L
H
H
BA, RA
ACT
ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
NOP*4 (Idle after tRP)
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
ROW
ACTIVATING
H
X
X
X
X
DESEL
NOP (Row Active after tRCD)
L
H
H
H
X
NOP
NOP (Row Active after tRCD)
L
H
H
L
X
TBST
ILLEGAL*2
L
H
L
X
BA, CA, A10
READ / WRITE ILLEGAL*2
L
L
H
H
BA, RA
ACT
ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL*2
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
WRITE RE-
COVERING
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
X
TBST
ILLEGAL*2
L
H
L
X
BA, CA, A10
READ / WRITE ILLEGAL*2
L
L
H
H
BA, RA
ACT
ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL*2
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
10
FUNCTION TRUTH TABLE (continued)
Current State
/CS
/RAS /CAS
/WE
Address
Command
Action
RE-
FRESHING
H
X
X
X
X
DESEL
NOP (Idle after tRC)
L
H
H
H
X
NOP
NOP (Idle after tRC)
L
H
H
L
X
TBST
ILLEGAL
L
H
L
X
BA, CA, A10
READ / WRITE ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
MODE
REGISTER
SETTING
H
X
X
X
X
DESEL
NOP (Idle after tRSC)
L
H
H
H
X
NOP
NOP (Idle after tRSC)
L
H
H
L
X
TBST
ILLEGAL
L
H
L
X
BA, CA, A10
READ / WRITE ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No OPeration
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of
that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and/or data-integrity are not guaranteed.
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
11
Current State
CKE
n-1
CKE
n
/CS /RAS /CAS /WE
Add
Action
SELF-
REFRESH*1
H
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
Exit Self-Refresh (Idle after tRC)
L
H
L
H
H
H
X
Exit Self-Refresh (Idle after tRC)
L
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP (Maintain Self-Refresh)
POWER
DOWN
H
X
X
X
X
X
X
INVALID
L
H
X
X
X
X
X
Exit Power Down to Idle
L
L
X
X
X
X
X
NOP (Maintain Power Down)
ALL BANKS
IDLE*2
H
H
X
X
X
X
X
Refer to Function Truth Table
H
L
L
L
L
H
X
Enter Self-Refresh
H
L
H
X
X
X
X
Enter Power Down
H
L
L
H
H
H
X
Enter Power Down
H
L
L
H
H
L
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
X
X
X
ILLEGAL
L
X
X
X
X
X
X
Refer to Current State =Power Down
ANY STATE
other than
listed above
H
H
X
X
X
X
X
Refer to Function Truth Table
H
L
X
X
X
X
X
Begin CLK Suspend at Next Cycle*3
L
H
X
X
X
X
X
Exit CLK Suspend at Next Cycle*3
L
L
X
X
X
X
X
Maintain CLK Suspend
FUNCTION TRUTH TABLE for CKE
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
NOTES:
1. CKE Low to High transition will re-enable CLK and other inputs asynchronously .
A minimum setup time must be satisfied before any command other than EXIT.
2. Self-Refresh can be entered only from the All Banks Idle State.
3. Must be legal command.
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
12
SIMPLIFIED STATE DIAGRAM
Automatic Sequence
Command Sequence
IDLE
PRE
CHARGE
POWER
DOWN
READ
READA
WRITE
WRITEA
POWER
ON
CKEL
CKEH
CKEL
CKEH
CKEL
CKEH
CKEL
CKEH
ACT
REFA
REFS
REFSX
CKEL
CKEH
MRS
CKEL
CKEH
WRITE
READ
WRITEA
WRITEA
READA
WRITE
READ
PRE
READA
WRITEA
READA
POWER
APPLIED
MODE
REGISTER
SET
SELF
REFRESH
AUTO
REFRESH
CLK
SUSPEND
WRITE
SUSPEND
READ
SUSPEND
READA
SUSPEND
WRITEA
SUSPEND
ROW
ACTIVE
PRE
TBST
TBST
PRE
PRE
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
13
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a
SDRAM from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP condition at the
inputs.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 100s.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by
setting the mode register (MRS). The mode register stores these data
until the next MRS command, which may be issued when all banks are in
idle state. After tRSC from a MRS command, the SDRAM is ready for
new command.
/CS
/RAS
/CAS
/WE
BA0,1 A12-A0
CLK
V
R: Reserved for Future Use
BA0 BA1 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0
0
0
0
0 SW
0
0
LTMODE
BT
BL
BURST
LENGTH
BL
BT=0
BT=1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1
2
4
8
R
R
R
Full Page
1
2
4
8
R
R
R
R
0
1
BURST
TYPE
SEQUENTIAL
INTERLEAVED
LATENCY
MODE
CL
/CAS LATENCY
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
R
R
2
3
R
R
R
R
Burst Write
Single Write
SW
0
1
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
14
A2 A1 A0
Initial Address BL
Sequential
Interleaved
Column Addressing
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
-
0
0
-
0
1
-
1
0
-
1
1
-
-
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
7
0
1
2
0
1
2
3
1
2
3
0
2
3
0
1
3
0
0
1
7
6
5
4
0
1
2
3
1
0
3
2
2
3
0
1
3
2
0
1
-
-
1
1
2
1
0
3
4
5
6
3
2
1
0
1
0
1
0
8
4
2
Command
Address
CLK
Read
Y
Write
Y
/CAS Latency
Burst Length
Burst Length
DQ
Burst Type
CL= 3
BL= 4
Q0
Q1
Q2
Q3
D0
D1
D2
D3
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
15
OPERATIONAL DESCRIPTION
BANK ACTIVATE
One of four banks is activated by an ACT command.
An bank is selected by BA0-1. A row is selected by A0-12.
Multiple banks can be active state concurrently by issuing multiple ACT commands.
Minimum activation interval between one bank and another bank is tRRD.
PRECHARGE
An open bank is deactivated by a PRE command.
A bank to be deactivated is designated by BA0-1.
When multiple banks are active, a precharge all command (PREA, PRE + A10=H) deactivates all of
open banks at the same time. BA0-1 are "Don't Care" in this case.
Minimum delay time of an ACT command after a PRE command to the same bank is tRP.
READ
A READ command can be issued to any active bank. The start address is specified by A0-9,11(x4), A0-
9 (x8), A0-8 (x16). 1st output data is available after the /CAS Latency from the READ. The consecutive
data length is defined by the Burst Length. The address sequence of the burst data is defined by the Burst
Type. Minimum delay time of a READ command after an ACT command to the same bank is tRCD.
When A10 is high at a READ command, auto-precharge (READA) is performed. Any command (READ,
WRITE, PRE, ACT,TBST) to the same bank is inhibited till the internal precharge is complete. The
internal precharge starts at the BL after READA. The next ACT command can be issued after (BL +
tRP) from the previous READA. In any case, tRCD+BL > tRASmin must be met.
Bank Activation and Precharge All (BL=4, CL=3)
CLK
Command
A0-9,11-12
A10
BA0-1
DQ
ACT
READ
ACT
PRE
ACT
Xa
Xb
Yb
Xa
1
Xa
Xb
0
00
01
01
00
Qb0
Qb1
Qb2
Qb3
tRRD
tRCD
tRP
Xa
Precharge All
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
16
CLK
Command
A0-9,11-12
A10
BA0-1
DQ
ACT
ACT
Xa
Xa
Xa
00
00
tRCD
tRP
Xa
Read with Auto-Precharge (CL=2, BL=4)
READ
Ya
1
00
Qa0
Qa1
Qa2
Qa3
internal precharge starts
BL
CLK
Command
DQ
ACT
ACT
tRCD
Auto-Precharge Timing (READ, BL=4)
READ
Qa0
Qa1
Qa2
Qa3
internal precharge starts
BL
DQ
Qa0
Qa1
Qa2
Qa3
CL=2
CL=3
CLK
Command
A0-9,11-12
A10
BA0-1
DQ
ACT
READ
ACT
PRE
ACT
Xa
Xb
Yb
Xa
0
Xa
Xb
0
00
01
01
00
Qb0
Qb1
Qb2
Qb3
tRCD
tRCD
tRP
Xa
Multi Bank Interleaving Read (CL=2, BL=4)
READ
Ya
0
00
Qa0
Qa1
Qa2
Qa3
00
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
17
WRITE
A WRITE command can be issued to any active bank.The start address is specified by A0-9,11(x4),
A0-9 (x8), A0-8 (x16). 1st input data is set at the same cycle as the WRITE. The consecutive data length
to be written is defined by the Burst Length. The address sequence of burst data is defined by the Burst
Type. Minimum delay time of a WRITE command after an ACT command to the same bank is tRCD.
From the last input data to the PRE command, the write recovery time (tWR) is required. When A10 is
high at a WRITE command, auto-precharge (WRITEA) is performed. Any command (READ, WRITE,
PRE, ACT, TBST) to the same bank is inhibited till the internal precharge is complete. The internal
precharge starts at tWR after the last input data cycle. The next ACT command can be issued after (BL
+ tWR -1 +tRP) from the previous WRITEA. In any case, tRCD + BL + tWR -1 > tRASmin must be
met.
CLK
Command
A0-9,11-12
A10
BA0-1
DQ
ACT
PRE
ACT
Xa
Xa
0
Xa
00
00
tRCD
tRP
Xa
Write (BL=4)
Write
Ya
0
00
Da0
Da1
Da2
Da3
BL
tWR
CLK
Command
A0-9,11-12
A10
BA0-1
DQ
ACT
ACT
Xa
Xa
Xa
00
00
tRCD
tRP
Xa
Write with Auto-Precharge (BL=4)
Write
Ya
1
00
Da0
Da1
Da2
Da3
BL
tWR
internal precharge starts
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
18
BURST INTERRUPTION
[ Read Interrupted by Read ]
Burst read operation can be interrupted by new read of any active bank. Random column access is
allowed. READ to READ interval is minimum 1 CLK.
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of any active bank. Random column access is allowed.
In this case, the DQ should be controlled adequately by using the DQM to prevent the bus contention.
The output is disabled automatically 2 cycle after WRITE assertion.
CLK
Command
A0-9,11-12
A10
BA0-1
DQ
READ
Yb
0
00
Qc0
Qc1
Qc2
Qc3
Read interrupted by Read (CL=2, BL=4)
READ
Ya
0
00
Qa0
Qa1
Qa2
Qb0
READ
Yc
0
10
CLK
Command
A0-9,11-12
A10
BA0-1
DQ
ACT
Xa
Xa
00
Read interrupted by Write (CL=2, BL=4)
READ
Ya
0
00
Qa0
Da0
Da1
Da2
DQM
Write
Ya
0
00
Da3
Output disable by DQM by WRITE
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
19
[ Read Interrupted by Precharge ]
A burst read operation can be interrupted by a precharge of the same bank . READ to PRE interval is
minimum 1 CLK.
A PRE command to output disable latency is equivalent to the /CAS Latency.
Read interrupted by Precharge (BL=4)
CLK
Command
DQ
PRE
READ
Q0
Q1
Q2
Command
DQ
PRE
READ
Q0
Q1
Command
DQ
PRE
READ
Q0
Command
DQ
PRE
READ
Q0
Q1
Q2
Command
DQ
PRE
READ
Q0
Q1
Command
DQ
PRE
READ
Q0
CL=2
CL=3
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
20
[ Read Interrupted by Burst Terminate ]
Similarly to the precharge, a burst terminate command can interrupt the burst read operation and
disable the data output. The terminated bank remains active. READ to TBST interval is minimum 1
CLK. A TBST command to output disable latency is equivalent to the /CAS Latency.
CLK
Command
DQ
TBST
READ
Q0
Q1
Q2
Command
DQ
TBST
READ
Q0
Q1
Command
DQ
TBST
READ
Q0
Command
DQ
TBST
READ
Q0
Q1
Q2
Command
DQ
TBST
READ
Q0
Q1
Command
DQ
TBST
READ
Q0
CL=2
CL=3
Read interrupted by Terminate (BL=4)
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
21
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of any active bank. Random column access is
allowed. WRITE to WRITE interval is minimum 1 CLK.
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of any active bank. Random column access is allowed.
WRITE to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is
"Don't Care".
Write interrupted by Write (BL=4)
CLK
Command
A0-9,11-12
A10
BA0-1
DQ
Write
Yb
0
00
Dc0
Dc1
Dc2
Dc3
Write
Ya
0
00
Da0
Da1
Da2
Db0
Write
Yc
0
10
CLK
Command
A0-9,11-12
A10
BA0-1
DQ
ACT
Xa
Xa
00
Write interrupted by Read (CL=2, BL=4)
READ
Yb
0
00
Da0
Da1
Qb0
Write
Ya
0
00
Qb1
Qb2
Qb3
don't care
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
22
[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of the same bank. Write recovery time (tWR) is
required from the last data to PRE command. During write recovery, data inputs must be masked by
DQM.
[ Write Interrupted by Burst Terminate ]
Burst terminate command can terminate burst write operation. In this case, the write recovery time is
not required and the bank remains active. WRITE to TBST interval is minimum 1 CLK.
CLK
Command
A0-9,11-12
A10
BA0-1
DQ
Write
Ya
0
00
Write interrupted by Precharge (BL=4)
ACT
Xa
0
00
Da0
Da1
PRE
0
00
ACT
Xa
0
00
tWR
tRP
DQM
CLK
Command
A0-9,11-12
A10
BA0-1
DQ
Write
Ya
0
00
Write interrupted by Terminate (BL=4)
ACT
Xa
0
00
Da0
Da1
TBST
Write
Yb
0
00
Db0
Db1
Db2
Db3
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
23
[ Write with Auto-Precharge Interrupted by Write / Read to another Bank ]
Burst write with auto-precharge can be interrupted by write or read to another bank. Next ACT
comand can be issued after (BL+tWR-1+tRP) from the WRITEA. Auto-precharge interruption by a
command to the same bank is inhibited.
WRITEA interrupted by WRITE to another bank (BL=4)
CLK
Command
A0-9,11-12
A10
BA0-1
DQ
Db0
Db1
Db2
Db3
Write
Ya
1
00
Da0
Da1
Write
Yb
0
10
BL
tWR
tRP
ACT
Xa
Xa
00
interrupted
auto-precharge
activate
WRITEA interrupted by READ to another bank (CL=2, BL=4)
CLK
Command
A0-9,11-12
A10
BA0-1
DQ
Write
Ya
1
00
Da0
Da1
Read
Yb
0
10
BL
tWR
tRP
ACT
Xa
Xa
00
interrupted
auto-precharge
activate
Qb0
Qb1
Qb2
Qb3
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
24
[ Read with Auto-Precharge Interrupted by Read to another Bank ]
Burst read with auto-precharge can be interrupted by read to another bank. Next ACT comand can
be issued after (BL+tRP) from the READA. Auto-precharge interruption by a command to the same
bank is inhibited.
READA interrupted by READ to another bank (CL=2, BL=4)
CLK
Command
A0-9,11-12
A10
BA0-1
DQ
Read
Ya
1
00
Qa0
Qa1
Read
Yb
0
10
BL
tRP
ACT
Xa
Xa
00
interrupted
auto-precharge
activate
Qb0
Qb1
Qb2
Qb3
Full Page Burst
Full page burst length is available for only the sequential burst type. Full page burst read / write is
repeated untill a Precharge or a Burst Terminate command is issued. In case of the full page burst,
a read / write with auto-precharge command is illegal.
Single Write
When sigle write mode is set, burst length for write is always one, independently of Burst Length
defined by (A2-0).
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
25
AUTO REFRESH
Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /CAS= L, /WE= /CKE= H)
command. The refresh address is generated internally. 8192 REFA cycles within 64ms refresh 256Mbit
memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing an auto-
refresh, all banks must be in idle state. Auto-refresh to auto-refresh interval is minimum tRFC. Any
command must not be issued before tRFC from the REFA command.
Auto-Refresh
CLK
/CS
/RAS
/CAS
/WE
CKE
A0-12
BA0-1
Auto Refresh on All Banks
NOP or DESELECT
Auto Refresh on All Banks
minimum tRFC
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
26
SELF REFRESH
Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, CKE= L).
Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode,
CKE is asynchronous and the only enabled input. All other inputs including CLK are disabled and
ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh,
supplying stable CLK inputs, asserting DESEL or NOP command and then asserting CKE=H. After
tRFC from the 1st CLK edge following CKE=H, all banks are in idle state and a new command can be
issued, but DESEL or NOP commands must be asserted till then.
Self-Refresh
CLK
/CS
/RAS
/CAS
/WE
CKE
A0-12
BA0-1
Self Refresh Entry
Self Refresh Exit
X
00
new command
minimum tRFC
for recovery
Stable CLK
NOP
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
27
CLK SUSPEND and POWER DOWN
CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By
negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output
suspend or input suspend. CKE is a synchronous input except during the self-refresh mode. CLK
suspend can be performed either when the banks are active or idle. A command at the suspended cycle is
ignored.
Power Down by CKE
CLK
Command
CKE
Command
CKE
Standby Power Down
Active Power Down
PRE
NOP
NOP
NOP
NOP
NOP
NOP
ACT
DQ Suspend by CKE
CLK
Command
DQ
CKE
Write
Read
D0
D1
D2
D3
Q0
Q1
Q2
Q3
ext.CLK
CKE
int.CLK
tIH
tIS
tIH
tIS
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
28
DQM CONTROL
DQMU/L is a dual functional signal defined as the data mask for writes and the output disable for
reads. During writes, DQMU/L masks input data word by word. DQMU/L to Data In latency is 0.
During reads, DQMU/L forces output to Hi-Z word by word. DQMU/L to output Hi-Z latency is 2.
DQM Function
CLK
Command
DQ
DQMU/L
masked by DQMU/L=H
disabled by DQMU/L=H
Write
Read
D0
D2
D3
Q0
Q1
Q3
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
29
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
(Ta=0 ~ 70'C, unless otherwise noted)
CAPACITANCE
(Ta=0 ~ 70'C, Vdd = VddQ = 3.3 0.3V, Vss = VssQ = 0V, unless otherwise noted)
'C
-65~ 150
Storage Tempreture
Tstg
'C
0~ 70
Operating Temprature
Topr
mW
1000
Ta=25'C
Power Dissipation
Pd
mA
50
Output Current
IO
V
-0.5 ~ VddQ+0.5
with respect to VssQ
Output Voltage
VO
V
-0.5 ~ Vdd+0.5
with respect to Vss
Input Voltage
VI
V
-0.5 ~ 4.6
with respect to VssQ
Supply Voltage for Output
VddQ
V
-0.5 ~ 4.6
with respect to Vss
Supply Voltage
Vdd
Unit
Ratings
Conditions
Parameter
Symbol
V
0.8
-0.3
Low-Level Input Voltage all inputs
VIL
V
Vdd+0.3
2.0
High-Level Input Voltage all inputs
VIH
V
0
0
0
Supply Voltage fo Output
VssQ
V
3.6
3.3
3.0
Supply Voltage for Output
VddQ
V
0
0
0
Supply Voltage
Vss
V
3.6
3.3
3.0
Supply Voltage
Vdd
Max.
Typ.
Min.
Unit
Limits
Parameter
Symbol
pF
6.5
4.0
CI/O
pF
3.5
2.5
Input Capacitance,I/O pin
Input Capacitance,CLK pin
CI(K)
pF
3.8
2.5
Input Capacitance,control pin
CI(C)
pF
3.8
2.5
VI=1.4V
f=1MHz
VI=25mVrms
Input Capacitance,address pin
CI(A)
Max.
Min.
Unit
Limits
Test Condition
Parameter
Symbol
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
30
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~ 70'C, Vdd = VddQ = 3.3 0.3V, Vss = VssQ = 0V, Output Open, unless otherwise noted)
Notes
1.
addresses are changed 3 times during tRC, only 1 bank is active & all other banks are idle
2.
all banks are idle
3.
input signals are changed one time during 3xtCLK
4.
input signals are stable
5.
all banks are active
6. Low Power Version (-5L/-6L/-7L)
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70'C, Vdd = VddQ = 3.3 0.3V, Vss = VssQ = 0V, unless otherwise noted)
Symbol
Parameter
Test Conditions
Limits
Min.
Max.
Unit
VOH(DC)
VOL(DC)
IOZ
I
I
High-Level Output Voltage (DC)
Low-Level Output Voltage (DC)
Off-state Output Current
Input Current
IOH=-2mA
IOL= 2mA
Q floating Vo=0 ~ VddQ
VIH=0 ~ VddQ+0.3V, other input pins=0V
2.4
0.4
V
V
A
A
-10
-10
10
10
6
mA
2
2
2
-5L/-6L/-7L
3
180
120
110
110
15
30
6
25
1
1.5
100
95
90
-6
mA
3
3
-5 /-6/-7
CKE<0.2v
Self-Refresh Current
Icc6
150
100
90
140
120
115
90
85
x16
x8
x4
x16
x8
x4
Organi
zation
4,5
3,5
2,4
2,3
5
2
1
mA
mA
mA
mA
mA
mA
mA
mA
mA
170
90
15
25
6
20
1
1
80
220
140
15
35
6
30
1
2
110
tCLK=min, tRFC=min
Auto-Refresh Current
Icc5
tCLK=min, BL=4, gapless
data
Burst Operating
Current
Icc4
tCLK=L, CKE>VIHmin
tCLK=min, CKE>VIHmin,
/CS> VIHmin
Active Standby
Current
in Normal Mode
Icc3NS
Icc3N
tCLK=L, CKE>VIHmin
tCLK=min, CKE>VIHmin,
/CS>VIHmin
Idle Standby Current
in Normal Mode
Icc2NS
Icc2N
tCLK=L, CKE<VILmax
tCLK=min, CKE<VILmax
Icc2PS
Icc2P
Idle Standby Current
in Power Down Mode
tCLK=min, tRC=min, BL=1
Operating Current
(1bank)
Icc1
Note
Unit
-7
-5
Limits(max)
Test Conditions
Parameter
Symbol
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
31
AC TIMING REQUIREMENTS
(Ta=0 ~ 70'C, Vdd = VddQ = 3.3 0.3V, Vss = VssQ = 0V, unless otherwise noted)
Input Pulse Levels:
0.8V to 2.0V
Input Timing Measurement Level:
1.4V
120000
7.8
12
12
12
15
42
15
60
60
0.8
1.5
10
1
2.5
2.5
6
7.5
-5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
7.8
7.8
20
15
20
15
20
15
20
20
20
20
120000
50
120000
45
80
75
70
67.5
1
2
0.8
1.5
10
1
10
1
3
3
2.5
2.5
10
10
7.5
10
Average Refresh Interval
Mode Register Set Cycle
time
ACT to ACT Delay time
Write Recovery time
Row Precharge time
Row Active time
Row to Column Delay
Refresh Cycle time
Row Cycle time
Input Hold time (all inputs)
Input Setup time (all inputs)
Transition time of CLK
CLK Low pulse width
CLK High pulse width
tREF
tRSC
tRRD
tWR
tRP
tRAS
tRCD
tRFC
tRC
tIH
tIS
tT
tCL
tCH
CL=3
CL=2
CLK cycle time
tCLK
Note
Unit
Max.
Min.
Max.
Min.
Max.
Min.
-7
-6
Limits
Parameter
Symbol
AC timing is referenced to the
input signal crossing through
1.4V.
CLK
Signal
1.4V
1.4V
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
32
SWITCHING CHARACTERISTICS
(Ta=0 ~ 70'C, Vdd = VddQ = 3.3 0.3V, Vss = VssQ = 0V, unless otherwise noted)
Output Load Condition
50pF
Vout
tOLZ
tAC
tOH
tOHZ
CLK
DQ
1.4V
1.4V
ns
6
3
5.4
3
5.4
3
CL=3
CL=2
5.4
3
0
3
3
5.4
5.4
-5
ns
ns
ns
ns
ns
ns
6
3
6
3
0
0
3
3
3
3
6
6
5.4
6
CL=3
CL=2
CL=3
CL=2
Delay Time, Output High
impedannce from CLK
Delay Time, Output Low
impedance from CLK
Output Hold Time from CLK
Access Time from CLK
tOHZ
tOLZ
tOH
tAC
Max
Min.
Max
Min.
Max
Min.
-7
-6
Unit
Limits
Parameter
Symbol
Note. If tr (CLK rising time) is > 1ns, (tr/2 - 0.5ns) should be added to the parameters.
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
33
Burst Write (Single Bank) [BL=4]
CLK
/CS
/RAS
/CAS
/WE
CKE
DQM
A0-9,11
A10
A12
BA0,1
DQ
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
15 16
X
X
X
0
Y
0
D0
D0
D0
D0
0
X
Y
X
X
0
0
D0
D0
D0
D0
0
tRC
tRCD
tRAS
tWR
tRP
tRCD
tWR
Italic paramater shows minimum case
ACT#0 WRITE#0
PRE#0
ACT #0 WRITE#0
PRE#0
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
34
Burst Write (Multi Bank) [BL=4]
CLK
/CS
/RAS
/CAS
/WE
CKE
DQM
A0-9,11
A10
A12
BA0,1
DQ
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
15 16
X
X
X
0
Y
0
D0
D0
D0
D0
0
X
Y
X
X
0
0
D0
D0
D0
D0
0
tRC
tRCD
tRAS
tWR
tRP
tRCD
tWR
Italic paramater shows minimum case
ACT#0 WRITE#0
PRE#0
ACT #0
WRITE#0
PRE#0
X
X
X
1
ACT#1
tRRD
tRCD
Y
1
D1
D1
D1
D1
WRITEA#1
(Auto-Precharge)
ACT#1
X
X
X
1
tRC
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
35
Burst Read (Single Bank) [CL=2, BL=4]
CLK
/CS
/RAS
/CAS
/WE
CKE
DQM
A0-9,11
A10
A12
BA0,1
DQ
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
15 16
X
X
X
0
Y
0
Q0
Q0
Q0
Q0
0
X
Y
X
X
0
0
Q0
Q0
Q0
Q0
0
tRC
tRCD
tRAS
tRP
tRCD
Italic paramater shows minimum case
ACT#0 READ#0
PRE#0
ACT #0 READ#0
PRE#0
tRAS
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
36
Burst Read (Multi Bank) [CL=2, BL=4]
CLK
/CS
/RAS
/CAS
/WE
CKE
DQM
A0-9,11
A10
A12
BA0,1
DQ
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
15 16
X
X
X
0
Y
0
Q0
Q0
Q0
Q0
1
X
Y
X
X
0
0
Q0
Q0
Q0
Q0
0
tRC
tRCD
tRCD
Italic paramater shows minimum case
ACT#0 READA#0
READA#1
ACT #0 READ#0
PRE#0
X
X
X
1
tRRD
ACT#1
Y
Q1
Q1
Q1
Q1
tRCD
X
X
X
1
ACT #1
tRC
tRAS
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
37
Write Interrupted by Write [BL=4]
CLK
/CS
/RAS
/CAS
/WE
CKE
DQM
A0-9,11
A10
A12
BA0,1
DQ
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
15 16
X
X
X
0
Y
0
D0
D0
D0
D0
1
Y
0
D0
D0
D0
D0
0
tRCD
Italic paramater shows minimum case
ACT#0 WRITE#0
WRITE#0
PRE#0
X
X
X
1
tRRD
ACT#1
Y
D0
D1
D1
D1
X
X
X
1
ACT #1
Y
0
WRITE#0 WRITEA #1
interrupt
same
bank
interrupt
other
bank
interrupt
other
bank
tWR
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
38
Read Interrupted by Read [CL=2, BL=4]
CLK
/CS
/RAS
/CAS
/WE
CKE
DQM
A0-9,11
A10
A12
BA0,1
DQ
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
15 16
X
X
X
0
Y
0
Q0
Q0
1
Y
0
Q1
Q1
Q0
Q0
tRCD
Italic paramater shows minimum case
ACT#0 READ#0
READ#0
X
X
X
1
tRRD
ACT#1
Y
Q0
Q1
Q1
Q1
X
X
X
1
ACT #1
Y
1
READ#1 READA#1
interrupt
other
bank
tRCD
interrupt
same bank
interrupt
other
bank
Q0
Q0
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
39
Write Interrupted by Read, Read Interrupted by Write [CL=2, BL=4]
CLK
/CS
/RAS
/CAS
/WE
CKE
DQM
A0-9,11
A10
A12
BA0,1
DQ
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
15 16
X
X
X
0
Y
0
D0
D0
Y
1
D1
D1
D1
D1
1
tRCD
Italic paramater shows minimum case
ACT#0
WRITE#0
WRITE#1
PRE#1
X
X
X
1
tRRD
ACT#1
Q1
Q1
Y
1
tWR
READ#1
tRCD
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
40
Write / Read Terminated by Precharge [CL=2, BL=4]
CLK
/CS
/RAS
/CAS
/WE
CKE
DQM
A0-9,11
A10
A12
BA0,1
DQ
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
15 16
X
X
X
0
Y
0
D0
D0
Y
0
Q0
Q0
0
tRCD
Italic paramater shows minimum case
ACT#0
WRITE#0
READ#0 PRE#0
0
PRE#0
tWR
X
X
X
0
ACT#0
tRP
0
tRAS
tRCD
tRP
X
X
X
ACT#0
tRC
Terminate
Terminate
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
41
Write / Read Terminated by Burst Terminate [CL=2, BL=4]
CLK
/CS
/RAS
/CAS
/WE
CKE
DQM
A0-9,11
A10
A12
BA0,1
DQ
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
15 16
X
X
X
0
Y
0
D0
D0
Y
0
Q0
Q0
0
tRCD
Italic paramater shows minimum case
ACT#0 WRITE#0
READ#0
TBST
PRE#0
Y
0
TBST
D0
D0
D0
D0
WRITE#0
tWR
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
42
Single Write Burst Read [CL=2, BL=4]
CLK
/CS
/RAS
/CAS
/WE
CKE
DQM
A0-9,11
A10
A12
BA0,1
DQ
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
15 16
X
X
X
0
Y
0
D0
Q0
Q0
tRCD
Italic paramater shows minimum case
ACT#0 WRITE#0 READ#0
Q0
Q0
Y
0
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
43
Power-Up Sequence and Intialize
CLK
/CS
/RAS
/CAS
/WE
CKE
DQM
A0-9,11
A10
A12
BA0,1
DQ
0
Italic paramater shows minimum case
PRE ALL REFA
ACT #0
MRS
REFA
0
0
0
MA
X
X
X
100s
REFA
tRP
tRFC
Minimum 8 REFA cycles
NOP
tRFC
tRSC
Power On
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
44
Auto Refresh
CLK
/CS
/RAS
/CAS
/WE
CKE
DQM
A0-9,11
A10
A12
BA0,1
DQ
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
15 16
Italic paramater shows minimum case
PRE ALL
REFA
Y
0
D0
D0
D0
D0
WRITE#0
X
X
X
0
ACT#0
tRP
tRFC
tRCD
All banks must be idle before REFA is issued.
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
45
Self Refresh
CLK
/CS
/RAS
/CAS
/WE
CKE
DQM
A0-9,11
A10
A12
BA0,1
DQ
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
15 16
Italic paramater shows minimum case
PRE ALL Self Refresh Entry
Self Refresh Exit
X
X
X
0
ACT#0
tRP
All banks must be idle before REFS is issued.
tRFC
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
46
CLK Suspension [CL=2, BL=4]
CLK
/CS
/RAS
/CAS
/WE
CKE
DQM
A0-9,11
A10
A12
BA0,1
DQ
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
15 16
X
X
X
0
Y
0
D0
Q0
Q0
tRCD
Italic paramater shows minimum case
ACT#0 WRITE#0
READ#0
Q0
Y
0
D0
D0
D0
internal
CLK
suspended
Q0
internal
CLK
suspended
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
47
Power Down
CLK
/CS
/RAS
/CAS
/WE
CKE
DQM
A0-9,11
A10
A12
BA0,1
DQ
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
15 16
Italic paramater shows minimum case
PRE ALL
ACT #0
X
0
X
X
Standby Power Down
Active Power Down
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
48
Keep safety first in your circuit designs!
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Mitsubishi
semiconductor product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or
a third party.
2. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any
third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms,
or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Mitsubishi Electric Corporation without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an
authorized Mitsubishi Semiconductor product distributor for the latest product information before
purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors. Mitsubishi
Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these
inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric
Corporation by various means, including the Mitsubishi Semiconductor home page
(http://www.mitsubishichips.com).
4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Mitsubishi
Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.
5. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device
or system that is used under circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in
whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must
be exported under a license from the Japanese government and cannot be imported into a country other
than the approved destination. Any diversion or reexport contrary to the export control laws and
regulations of Japan and/or the country of destination is prohibited.
8. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for further details on these materials or the products contained therein.
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better
and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due
consideration to safety when making your circuit designs, with appropriate measures such as (i)
placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention
against any malfunction or mishap.
Aug '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
256M Synchronous DRAM
M2V56S20/ 30/ 40 ATP -5, -5L, -6, -6L, -7, -7L
49
Revison History
-Add -5L/-6L/-7L spec. forM2V56S20ATP/30ATP/40ATP
Aug./'01
1.1
1st edition
July / '01
1.01
Description
Date
Rev.
PDF 
ZIP