M2V56S20/ 30/ 40 TP 5,-5L, -6,-6L, -7,-7L

SDRAM (Rev.1.5E)

Single Data Rate

Oct.2001

256M Synchronous DRAM

MITSUBISHI LSIs

Preliminary

MITSUBISHI ELECTRIC

Some of contents are subject to change without notice.

DESCRIPTION

M2V56S20TP is a 4-bank x 16777216-word x 4-bit,
M2V56S30TP is a 4-bank x 8388608-word x 8-bit,
M2V56S40TP is a 4-bank x 4194304-word x 16-bit,
synchronous DRAM, with LVTTL interface.All inputs and outputs are referenced to the rising edge of
CLK.The M2V56S20/30/40TP achieve very high speed data rate up to 100MHz(-7) ,133MHz(-6) ,
166MHz(-5) and are suitable for main memory or graphic memory in computer systems.

FEATURES

-Single 3.3v±0.3V power supply
-Max. Clock frequency 5:PC166<3-3-3> / -6:PC133 <3-3-3> / -7:PC100 <2-2-2>
Synchronous operation referenced to clock -Fully rising edge
-Single Data Rate
-4 bank operation controlled by BA0, BA1 (Bank Address)
-/CAS latency- 2/3 (programmable)
-Burst length- 1/2/4/8/full page (programmable)
-Burst type- sequential / interleave (programmable)
-Random column access
-Auto precharge / All bank precharge controlled by A10
-8192 refresh cycles / 64ms (4 banks concurrent refresh)
-Auto refresh and Self refresh
-Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)
-LVTTL Interface
-400-mil, 54-pin Thin Small Outline Package (TSOPII) with 0.8mm lead pitch

Max. Frequency

@CL2

@CL3

M2V56S20/30/40TP-5/-5L

133MHz

166MHz

PC133(CL2)

M2V56S20/30/40TP-6/-6L

100MHz

133MHz

PC133(CL3)

M2V56S20/30/40TP-7/-7L

100MHz

PC100(CL2)

Standard

Note: The 5L/-6L/-7L is selfrefresh low power.

M2V56S20/ 30/ 40 TP 5,-5L, -6,-6L, -7,-7L

SDRAM (Rev.1.5E)

Single Data Rate

Oct.2001

256M Synchronous DRAM

MITSUBISHI LSIs

Preliminary

MITSUBISHI ELECTRIC

Vdd

VddQ

DQ0

VssQ

VddQ

DQ1

VssQ

Vdd

/WE

/CAS

/RAS

/CS

BA0

BA1

A10/AP

Vdd

DQ0

VddQ

DQ1

VssQ

DQ2

VddQ

DQ3

VssQ

Vdd

/WE

/CAS

/RAS

/CS

BA0

BA1

A10/AP

Vdd

DQ0

VddQ

DQ1

DQ2

VssQ

DQ3

DQ4

VddQ

DQ5

DQ6

VssQ

DQ7

Vdd

LDQM

/WE

/CAS

/RAS

/CS

BA0

BA1

A10/AP

Vdd

Vss

DQ15

VssQ

DQ14

DQ13

VddQ

DQ12

DQ11

VssQ

DQ10

DQ9

VddQ

DQ8

Vss

UDQM

CLK

CKE

A12

A11

Vss

DQ7

VssQ

DQ6

VddQ

DQ5

VssQ

DQ4

VddQ

Vss

DQM

CLK

CKE

A12

A11

Vss

VssQ

DQ3

VddQ

VssQ

DQ2

VddQ

Vss

DQM

CLK

CKE

A12

A11

Vss

400

mil x 875mil 54pin 0.8mm pitch TSOP(II)

CLK

CKE

/CS

/RAS

/CAS

/WE

DQ0-15

DQM,DQMU/L

A0-12

BA0,1

Vdd

VddQ

Vss

VssQ

: Master Clock

: Clock Enable

: Chip Select

: Row Address Strobe

: Column Address Strobe

: Write Enable

: Data I/O

: Output Disable / Write Mask

: Address Input

: Bank Address Input

: Power Supply

: Power Supply for Output

: Ground

: Ground for Output

x16

PIN CONFIGURATION

(TOP VIEW)

M2V56S20/ 30/ 40 TP 5,-5L, -6,-6L, -7,-7L

SDRAM (Rev.1.5E)

Single Data Rate

Oct.2001

256M Synchronous DRAM

MITSUBISHI LSIs

Preliminary

MITSUBISHI ELECTRIC

BLOCK DIAGRAM

DQ0-3 (x4), 0-7 (x8), 0-15 (x16)

I/O Buffer

Memory

Array

Bank #0

Memory

Array

Bank #1

Memory

Array

Bank #2

Memory

Array

Bank #3

Control Circuitry

Mode Register

Address Buffer

Clock Buffer

Control Signal Buffer

A0-12

BA0,1

CLK

CKE

/CS /RAS /CAS /WE DQMU/L

Speed Grade 5: 166MHz@CL3, 133MHz@CL2

6: 133MHz@CL3, 100MHz@CL2
7: 100MHz@CL2

Package Type TP: TSOP(II)
Process Generation
Function Reserved for Future Use
Organization 2

2:x4, 3:x8, 4:x16

SDRAM Data Rate Type S:Single Data Rate
Density 56: 256M bits
Interface V:LVTTL
Memory Style(DRAM)
Mitsubishi Main Designation

M 2 V 56 S 4

0 TP - 5

Type Designation Code

This rule is applied to only Synchronous DRAM family.

M2V56S20/ 30/ 40 TP 5,-5L, -6,-6L, -7,-7L

SDRAM (Rev.1.5E)

Single Data Rate

Oct.2001

256M Synchronous DRAM

MITSUBISHI LSIs

Preliminary

MITSUBISHI ELECTRIC

Master Clock: All other inputs are referenced to the rising edge of CLK.

Clock Enable: CKE controls internal clock. When CKE is low,internal
clock for the following cycle is ceased. CKE is also used to select auto
/self refresh. After self refresh mode is started. CKE becomes
asynchronous input. Self refresh is maintained as long as CKE is low.

A0-12 specify the Row/ Column Address in conjunction with BA0,1.
The Row Address is specified by A0-12.The Column Address is
specified by A0-9,11. A10 is also used to indicate precharge option.
When A10 is high at a read / write command, an auto precharge is
performed. When A10 is high at a precharge command, all banks are
precharged.

Bank Address : BA0,1 specifies one of four banks to which a command
is applied. BA0,1 must be set with ACT, PRE, READ, WRITE
commands.

Data In and Data out are referenced to the rising edge of CLK.

DQM

Din Mask / Output Disable: When DQMU/L is high in burst write, Din for

DQMU/L

Input

the current cycle is masked. When DQMU/L is high in burst read, Dout
is disabled at the next but one cycle.

Chip Select: When /CS is high, any command means No Operation

Combination of /RAS, /CAS, /WE defines basic commands.

Power supply for the memory array and peripheral circuitry.

VddQ and VssQ are supplied to the Output Buffers only.

Input

A0-12

BA0,1

Power Supply

DQ0-15

Vdd,Vss

VddQ,VssQ

Input

Input/Output

Power Supply

CLK

CKE

/CS

/RAS,/CAS,/WE

PIN FUNCTION

M2V56S20/ 30/ 40 TP 5,-5L, -6,-6L, -7,-7L

SDRAM (Rev.1.5E)

Single Data Rate

Oct.2001

256M Synchronous DRAM

MITSUBISHI LSIs

Preliminary

MITSUBISHI ELECTRIC

The M2V56S20/30/40TP provides basic functions, bank (row) activate, burst read / write, bank (row)
precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at
CLK rising edge. In addition to 3 signals, /CS,CKE and A10 are used as chip select, refresh option, and
precharge option, respectively. To know the detailed definition of commands, please see the command
truth table.

BASIC FUNCTIONS

CLK

/CS

/RAS

/CAS

/WE

CKE

A10

Chip Select:L=select, H=deselect
Command

Command

Refresh Option @refresh command
Precharge Option @ precharge or read/write command

define basic commands

Activate(ACT)[/RAS=L, /CAS=/WE=H]

ACT command activates a row in an idle bank indicated by BA.

Read(READ)[/RAS=H, /CAS=L, /WE=H]

READ command starts burst read from the active bank indicated by BA. First output data appears after

/CAS latency. When A10=H at this command, the bank is deactivated after the burst read (auto-

precharge,READA)

Write(WRITE[

/RAS=H, /CAS=L, /WE=L]

WRITE command starts burst write to the active bank indicated by BA. Total data length to be written

is set by burst length. When A10=H at this command, the bank is deactivated after the burst write

(auto-precharge, WRITEA).

Precharge(PRE)

[/RAS=L, /CAS=H, /WE=L]

PRE command deactivates the active bank indicated by BA. This command also terminates burst read

/write operation. When A10=H at this command, all banks are deactivated(precharge all, PREA).

Auto-Refresh(REFA)

[/RAS=/CAS=L, /WE=CKE=H]

REFA command starts auto-refresh cycle. Refresh address are generated internally.After this

command, the banks are precharged automatically.

M2V56S20/ 30/ 40 TP 5,-5L, -6,-6L, -7,-7L

SDRAM (Rev.1.5E)

Single Data Rate

Oct.2001

256M Synchronous DRAM

MITSUBISHI LSIs

Preliminary

MITSUBISHI ELECTRIC

CKE CKE

A10 A0-9,

n-1

/AP 11-12

Deselect

DESEL

No Operation

NOP

Row Address Entry&

Bank Activate

Single Bank Precharge

PRE

Precharge All Banks

PREA

Column Address Entry

&Write

Column Address Entry

&Write with

Auto-Precharge

Column Address Entry

&Read

Column Address Entry

&Read with

Auto-Precharge

Auto-Refresh

REFA

Self-Refresh Entry

REFS

Burst Terminate

TBST

Mode Register Set

MRS

COMMAND

MNEMONIC

/CS

/RAS /CAS /WE BA0,1

note

ACT

WRITE

WRITEA

READ

READA

Self-Refresh Exit

REFSX

COMMAND TRUTH TABLE

H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number

NOTE:

1. A7-9, 11-12=L, A0-A6 =Mode Address

M2V56S20/ 30/ 40 TP 5,-5L, -6,-6L, -7,-7L

SDRAM (Rev.1.5E)

Single Data Rate

Oct.2001

256M Synchronous DRAM

MITSUBISHI LSIs

Preliminary

MITSUBISHI ELECTRIC

FUNCTION TRUTH TABLE

Current State /CS /RAS /CAS /WE

Address

Command

Action

IDLE

DESEL

NOP

TBST

ILLEGAL

BA,CA,A10 READ/WRITE ILLEGAL

BA,RA

ACT

Bank Active,Latch RA

BA,A10

PRE/PREA

NOP

REFA

Auto-Refresh

Op-Code,
Mode-Add

ROW ACTIVE

DESEL

NOP

TBST

NOP
Begin Read,Latch CA,
Determine Auto-Precharge

WRITE/

Begin Write,Latch CA,

WRITEA

Determine Auto-Precharge

BA,RA

ACT

Bank Active/ILLEGAL

BA,A10

PRE/PREA

Precharge/Precharge All

REFA

ILLEGAL

Op-Code,
Mode-Add

READ

DESEL

NOP(Continue Burst to END)

NOP

NOP(Continue Burst to END)

TBST

Terminate Burst

Terminate Burst,Latch CA,
Begin New Read,Determine
Auto-Precharge

Terminate Burst,Latch CA,

WRITE/WRITEA Begin Write,Determine

Auto-Precharge

BA,RA

ACT

Bank Active/ILLEGAL

BA,A10

PRE/PREA

Terminate Burst,Precharge

REFA

ILLEGAL

Op-Code,

Mode-Add

MRS

Mode Register Set

BA,CA,A10 READ/READA

BA,CA,A10

MRS

ILLEGAL

BA,CA,A10 READ/READA

ILLEGAL

BA,CA,A10

MRS

M2V56S20/ 30/ 40 TP 5,-5L, -6,-6L, -7,-7L

SDRAM (Rev.1.5E)

Single Data Rate

Oct.2001

256M Synchronous DRAM

MITSUBISHI LSIs

Preliminary

MITSUBISHI ELECTRIC

Current State

/CS

/RAS /CAS

/WE

Address

Command

Action

WRITE

DESEL

NOP(Continue Burst to END)

NOP

NOP(Continue Burst to END)

TBST

Terminate Burst
Terminate Burst,Latch CA,

Begin Read,Determine
Auto-Precharge

Terminate Burst,Latch CA,

WRITE/

Begin Write,Determine

WRITEA

Auto-Precharge

BA,RA

ACT

Bank Active/ILLEGAL

BA,A10

PRE/PREA Terminate Burst,Precharge

REFA

ILLEGAL

Op-Code,

Mode-Add

READ with

DESEL

NOP(Continue Burst to END)

AUTO

NOP

NOP(Continue Burst to END)

PRECHARGE

TBST

ILLEGAL

BA,CA,A10 READ/READA ILLEGAL

WRITE/

WRITEA

BA,RA

ACT

Bank Active/ILLEGAL

BA,A10

PRE/PREA ILLEGAL

REFA

ILLEGAL

Op-Code,
Mode-Add

WRITE with

DESEL

NOP(Continue Burst to END)

AUTO

NOP

NOP(Continue Burst to END)

PRECHARGE

TBST

ILLEGAL

BA,CA,A10 READ/READA ILLEGAL

WRITE/

WRITEA

BA,RA

ACT

Bank Active/ILLEGAL

BA,A10

PRE/PREA ILLEGAL

REFA

ILLEGAL

Op-Code,
Mode-Add

BA,CA,A10

ILLEGAL

BA,CA,A10

ILLEGAL

MRS

ILLEGAL

MRS

BA,CA,A10 READ/READA

ILLEGAL

MRS

BA,CA,A10

ILLEGAL

FUNCTION TRUTH TABLE (continued)

M2V56S20/ 30/ 40 TP 5,-5L, -6,-6L, -7,-7L

SDRAM (Rev.1.5E)

Single Data Rate

Oct.2001

256M Synchronous DRAM

MITSUBISHI LSIs

Preliminary

MITSUBISHI ELECTRIC

Current State

/CS

/RAS /CAS

/WE

Address

Command

Action

PRE-

DESEL

NOP(Idle after tRP)

CHARGING

NOP

NOP(Idle after tRP)

TBST

ILLEGAL

BA,CA,A10 READ/WRITE ILLEGAL

BA,RA

ACT

ILLEGAL

BA,A10

PRE/PREA NOP

4(Idle after tRP)

REFA

ILLEGAL

Op-Code,
Mode-Add

ROW

DESEL

NOP(Row active after tRCD)

ACTIVATING

NOP

NOP(Row active after tRCD)

TBST

ILLEGAL

BA,CA,A10 READ/WRITE ILLEGAL

BA,RA

ACT

ILLEGAL

BA,A10

PRE/PREA ILLEGAL

REFA

ILLEGAL

Op-Code,
Mode-Add

WRITE RE-

DESEL

NOP

COVERING

NOP

TBST

ILLEGAL

BA,CA,A10 READ/WRITE ILLEGAL

BA,RA

ACT

ILLEGAL

BA,A10

PRE/PREA ILLEGAL

REFA

ILLEGAL

Op-Code,
Mode-Add

ILLEGAL

MRS

ILLEGAL

MRS

ILLEGAL

FUNCTION TRUTH TABLE (continued)

M2V56S20/ 30/ 40 TP 5,-5L, -6,-6L, -7,-7L

SDRAM (Rev.1.5E)

Single Data Rate

Oct.2001

256M Synchronous DRAM

MITSUBISHI LSIs

Preliminary

MITSUBISHI ELECTRIC

Current State /CS

/RAS /CAS /WE

Address

Command

Action

RE-

DESEL

NOP(Idle after tRFC)

FRESHING

NOP

NOP(Idle after tRFC)

TBST

ILLEGAL

BA,CA,A10 READ/WRITE ILLEGAL

BA,RA

ACT

ILLEGAL

BA,A10

PRE/PREA ILLEGAL

REFA

ILLEGAL

Op-Code,
Mode-Add

MODE

DESEL

NOP(Idle after tRSC)

NOP

NOP(Idle after tRSC)

SETTING

TBST

ILLEGAL

BA,CA,A10 READ/WRITE ILLEGAL

BA,RA

ACT

ILLEGAL

BA,A10

PRE/PREA ILLEGAL

REFA

ILLEGAL

Op-Code,
Mode-Add

ILLEGAL

MRS

ILLEGAL

FUNCTION TRUTH TABLE (continued)

ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No OPeration

NOTES:
1.All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2.ILLEGAL to bank in specified states ; function may be legal in the bank indicated by BA, depending on the

state that bank.
3.Must satisfy bus contention, bus turn around, write recovery requirements.
4.NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5.ILLEGAL if any bank is not idle.

ILLEGAL=Device operation and/or data-integrity are not guaranteed.

M2V56S20/ 30/ 40 TP 5,-5L, -6,-6L, -7,-7L

SDRAM (Rev.1.5E)

Single Data Rate

Oct.2001

256M Synchronous DRAM

MITSUBISHI LSIs

Preliminary

MITSUBISHI ELECTRIC

CKE CKE

n-1

SELF-

X INVALID

REFRESH

X Exit Self-Refresh(Idle after tRC)

X ILLEGAL

X NOP(Maintain Self-Refresh)

POWER

X INVALID

DOWN

X Exit Power Down to Idle

X NOP(Maintain Power Down)

ALL BANKS

X Refer to Function Truth Table

IDLE

X Enter Self-Refresh

X Enter Power Down

X ILLEGAL

X Refer to Current State=Power Down

ANY STATE

X Refer to Function Truth Table

other than

X Begin CLK Suspend at Next Cycle

listed above

X Exit CLK Suspend at Next Cycle

X Maintain CLK Suspend

/WE Add

Current State

Action

/CS /RAS /CAS

ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care

NOTES:
1.CKE Low to High transition will re-enable CLK and other inputs asynchronously.

A minimum set up time must be satisfied before any command other than EXIT.

2.Self-Refresh can be entered only from the All Banks ldle State.
3.Must be legal command.

FUNCTION TRUTH TABLE For CKE

M2V56S20/ 30/ 40 TP 5,-5L, -6,-6L, -7,-7L

SDRAM (Rev.1.5E)

Single Data Rate

Oct.2001

256M Synchronous DRAM

MITSUBISHI LSIs

Preliminary

MITSUBISHI ELECTRIC

Before starting normal operation, the following power on sequence is necessary to prevent a

SDRAM from damaged or malfunctioning.

1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP condition at the

inputs.

2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 100µs.

3. Issue precharge commands for all banks. (PRE or PREA)

4. After all banks become idle state (after tRP), issue 2 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode register.

After these sequence, the SDRAM is idle state and ready for normal operation.

Burst Length, Burst Type and /CAS Latency can be programmed by

setting the mode register (MRS). The mode register stores these data

until the next MRS command, which may be issued when all banks are in

idle state. After tRSC from a MRS command, the SDRAM is ready for

new command.

POWER ON SEQUENCE

MODE REGISTER

CLK
/CS
/RAS
/CAS
/WE

BA0, 1 A12-A0

BA0 BA1 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3

LTMODE

SEQUENTIAL

INTERLEAVED

BURST

TYPE

LATENCY

MODE

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

/CAS LATENCY

R
R

2
3

R
R
R
R

BURST

LENGTH

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

BT=0

1
2
4
8

R
R
R

Full Page

BT=1

1
2
4
8

R
R
R
R

Burst Write
Single Write

R:Reserved for Future Use

M2V56S20/ 30/ 40 TP 5,-5L, -6,-6L, -7,-7L

SDRAM (Rev.1.5E)

Single Data Rate

Oct.2001

256M Synchronous DRAM

MITSUBISHI LSIs

Preliminary

MITSUBISHI ELECTRIC

Burst Type

Burst Length

Write

CLK

Command

Address

CL=3

BL=4

/CAS=Latency

Read

Initial Address

Column Addressing

Sequential

Interleaved

M2V56S20/ 30/ 40 TP 5,-5L, -6,-6L, -7,-7L

SDRAM (Rev.1.5E)

Single Data Rate

Oct.2001

256M Synchronous DRAM

MITSUBISHI LSIs

Preliminary

MITSUBISHI ELECTRIC

BANK ACTIVATE

One of four banks is activated by an ACT command.
An bank is selected by BA0-1. A row is selected by A0-12.
Multiple banks can be active state concurrently by issuing multiple ACT commands.
Minimum activation interval between one bank and another bank is tRRD.

PRECHARGE

An open bank is deactivated by a PRE command.
A bank to be deactivated is designated by BA0-1.
When multiple banks are active, a precharge all command (PREA, PRE + A10=H) deactivates all of
open banks at the same time. BA0-1 are "Don't Care" in this case.
Minimum delay time of an ACT command after a PRE command to the same bank is tRP.

OPERATIONAL DESCRIPTION

CLK

Command

Bank Activation and Precharge All (BL=4, CL=3)

tRCD

ACT

READ

ACT

PRE

Qb0

Qb1

Qb2

Qb3

A0-9,11-12

A10

BA0-1

Precharge All

tRP

READ

A READ command can be issued to any active bank. The start address is specified by A0-9,11(x4),A0-

9 (x8), A0-8 (x16). 1st output data is available after the /CAS Latency from the READ. The consecutive
data length is defined by the Burst Length .The address sequence of the burst data is defined by the Burst
Type. Minimum delay time of a READ command after an ACT command to the same bank is tRCD.
When A10 is high at a READ command, auto-precharge (READA) is performed. Any command (READ,
WRITE, PRE, ACT, TBST) to the same bank is inhibited till the internal precharge is complete.The
Internal precharge starts at the BL after READA. The next ACT command can be issued after (BL +
tRP) from the previous READA. In any case, tRCD+BL > tRASmin must be met.

tRRD

M2V56S20/ 30/ 40 TP 5,-5L, -6,-6L, -7,-7L

SDRAM (Rev.1.5E)

Single Data Rate

Oct.2001

256M Synchronous DRAM

MITSUBISHI LSIs

Preliminary

MITSUBISHI ELECTRIC

CLK

Command

ACT

READ

ACT

PRE

A0-9,11-12

A10

BA0-1

tRP

Qa0

Qa1

Qa2

Qa3

Qb0

Qb1

Qb2

Qb3

READ

Multi Bank Interleaving Read (CL=2, BL=4)

ACT

READ

ACT

Qa0 Qa1

Qa2

Qa3

Qa0 Qa1

Qa2

Qa3

Internal precharge starts

CL=2

CL=3

CLK

Command

tRCD

tRP

ACT

READ

ACT

CLK

Command

A0-9,11-12

A10

BA0-1

Internal precharge starts

Qa0

Qa1

Qa2

Qa3

Read with Auto-Precharge (CL=2, BL=4)

Auto-Precharge Timing (READ, BL=4)

tRCD

M2V56S20/ 30/ 40 TP 5,-5L, -6,-6L, -7,-7L

SDRAM (Rev.1.5E)

Single Data Rate

Oct.2001

256M Synchronous DRAM

MITSUBISHI LSIs

Preliminary

MITSUBISHI ELECTRIC

A WRITE command can be issued to any active bank.The start address is specified by A0-9,11(x4),
A0-9 (x8), A0-8 (x16). 1st input data is set at the same cycle as the WRITE. The consecutive data length
to be written is defined by the Burst Length. The address sequence of burst data is defined by the Burst
Type. Minimum delay time of a WRITE command after an ACT command to the same bank is tRCD.
From the last input data to the PRE command, the write recovery time (tWR) is required. When A10 is
high at a WRITE command, auto-precharge(WRITEA) is performed. Any command (READ, WRITE,
PRE, ACT, TBST) to the same bank is inhibited till the internal precharge is complete. The internal
precharge starts at tWR after the last input data cycle. The next ACT command can be issued after (BL
+ tWR 1 +tRP) from the previous WRITEA. In any case, tRCD + BL + tWR 1 > tRASmin must be
met.

WRITE

A0-9,11-12

CLK

Command

tRCD

ACT

Write

ACT

PRE

A10

BA0-1

tRP

Da2

Da3

Da0

Da1

CLK

Command

tRCD

ACT

Write

ACT

A0-9,11-12

A10

BA0-1

Da2

Da3

Da0

Da1

Internal precharge starts

Write with Auto-Precharge (BL=4)

Write(BL=4)

tWR

tRP

M2V56S20/ 30/ 40 TP 5,-5L, -6,-6L, -7,-7L

SDRAM (Rev.1.5E)

Single Data Rate

Oct.2001

256M Synchronous DRAM

MITSUBISHI LSIs

Preliminary

MITSUBISHI ELECTRIC

CLK

Command

READ

A0-9,11-12

A10

BA0-1

READ

Qa0

Qa1

Qa2

Qb0

Qc0

Qc1

Qc2

Qc3

Read interrupted by Read(CL=2, BL=4)

READ

BURST INTERRUPUTION

[Read Interrupted by Read ]

Burst read operation can be interrupted by new read of any active bank. Random column access is

allowed. READ to READ interval is minimum 1 CLK.

[Read Interrupted by Write ]

Burst read operation can be interrupted by write of any active bank. Random column access is allowed.

In this case, the DQ should be controlled adequately by using the DQM to prevent the bus contention.

The output is disabled automatically 2 cycle after WRITE assertion.

A0-9,11-12

CLK

Command

ACT

READ

A10

BA0-1

DQM

Da2

Da3

Da0

Da1

Write

Da0

Read interrupted by Write(CL=2, BL=4)

Output disable by DQM by WRITE

M2V56S20/ 30/ 40 TP 5,-5L, -6,-6L, -7,-7L

SDRAM (Rev.1.5E)

Single Data Rate

Oct.2001

256M Synchronous DRAM

MITSUBISHI LSIs

Preliminary

MITSUBISHI ELECTRIC

CLK

Command

Write

A0-9,11-12

A10

BA0-1

Write

Da0

Da1

Da2

Db0

Dc0

Dc1

Dc2

Dc3

Write

[ Write Interrupted by Write ]

Burst write operation can be interruputed by new write of any active bank. Random column access is

allowed. WRITE to WRITE interval is minimum 1 CLK.

Write interrupted by Write(BL=4)

[ Write Interrupted by Read ]

Burst write operation can be interrupted by read of any active bank. Random column access is allowed.

WRITE to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is

"Don't Care".

Command

A0-9,11-12

CLK

ACT

A10

BA0-1

Da0

Da1

Qb0

Qb1

Qb2

Qb3

READ

don't care

Write

Write interrupted by Read(CL=2, BL=4)

M2V56S20/ 30/ 40 TP 5,-5L, -6,-6L, -7,-7L

SDRAM (Rev.1.5E)

Single Data Rate

Oct.2001

256M Synchronous DRAM

MITSUBISHI LSIs

Preliminary

MITSUBISHI ELECTRIC

[ Write Interrupted by Precharge ]

Burst write operation can be interruputed by precharge of the same bank. Write recovery time (tWR) is

required from the last data to PRE command. During write recovery, data inputs must be masked by DQM.

CLK

Command

ACT

A0-9,11-12

A10

BA0-1

Write

Da0

Da1

PRE

ACT

DQM

Write interrupted by Precharge (BL=4)

[ Write Interrupted by Burst Terminate ]

Burst terminate command can terminate burst write operation. In this case, the write recovery time is

not required and the bank remains active. WRITE to TBST interval is minimum 1 CLK.

CLK

Command

ACT

A10

BA0-1

Write

Db0

Db1

Write

Write interrupted by Terminate (BL=4)

A0-9,11-12

tRP

tWR

TBST

Da0

Da1

Db2

Db3

M2V56S20/ 30/ 40 TP 5,-5L, -6,-6L, -7,-7L

SDRAM (Rev.1.5E)

Single Data Rate

Oct.2001

256M Synchronous DRAM

MITSUBISHI LSIs

Preliminary

MITSUBISHI ELECTRIC

[ Write with Auto-Precharge Interrupted by Write / Read to another Bank ]

Burst write with auto-precharge can be interrupted by write or read to another bank. Next ACT

command can be issued after (BL+tWR-1+tRP) from the WRITEA. Auto-precharge interruption by a

command to the same bank is inhibited.

CLK

Command

Write

A0-9,11-12

A10

BA0-1

Da0

Da1

Db0

Db1

Db2

Db3

Write

ACT

auto-precharge

interrupted

activate

WRITEA interrupted by WRITE to another bank (BL=4)

CLK

Command

Write

A0-9,11-12

A10

BA0-1

Da0

Da1

Qb0

Qb1

Qb2

Qb3

Read

ACT

tWR

auto-precharge

interrupted

activate

WRITEA interrupted by READ to another bank (CL=2,BL=4)

tRP

tWR

M2V56S20/ 30/ 40 TP 5,-5L, -6,-6L, -7,-7L

SDRAM (Rev.1.5E)

Single Data Rate

Oct.2001

256M Synchronous DRAM

MITSUBISHI LSIs

Preliminary

MITSUBISHI ELECTRIC

Burst read with auto-precharge can be interrupted by read to another bank. Next ACT command can

be issued after (BL+tRP) from the READA. Auto-precharge interruption by a command to the same
bank is inhibited.

[ Read with Auto-Precharge Interrupted by Read to another Bank ]

CLK

Command

Read

A0-9,11-12

A10

BA0-1

Qa0

Qa1

Qb0

Qb1

Qb2

Qb3

Read

ACT

auto-precharge

interrupted

activate

READA interrupted by READ to another bank (CL=2,BL=4)

Full page burst length is available for only the sequential burst type. Full page burst read / write is

repeated untill a Precharge or a Burst Terminate command is issued. In case of the full page burst,
a read / write with auto-precharge command is illegal.

Full Page Burst

When single write mode is set, burst length for write is always one, independently of Burst Length

defined by (A2-0).

Single Write

tRP

M2V56S20/ 30/ 40 TP 5,-5L, -6,-6L, -7,-7L

SDRAM (Rev.1.5E)

Single Data Rate

Oct.2001

256M Synchronous DRAM

MITSUBISHI LSIs

Preliminary

MITSUBISHI ELECTRIC

AUTO REFRESH

Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /CAS=L, / WE= /CKE=H)

command. The refresh address is generated internally. 8192 REFA cycles within 64ms refresh 256Mbit
memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing an auto-
refresh, all banks must be in idle state. Auto-refresh to auto-refresh interval is minimum tRFC. Any
command must not be issued before tRFC from the REFA command.

Auto-Refresh

CLK

/CS

/RAS

/CAS

/WE

CKE

minimum tRFC

Auto-Refresh on All Banks

Auto Refresh on All Banks

A0-12

BA0-1

NOP or DESELECT

M2V56S20/ 30/ 40 TP 5,-5L, -6,-6L, -7,-7L

SDRAM (Rev.1.5E)

Single Data Rate

Oct.2001

256M Synchronous DRAM

MITSUBISHI LSIs

Preliminary

MITSUBISHI ELECTRIC

SELF REFRESH

Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS=L, /WE=H, CKE=L).

Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode,
CKE is asynchronous and the only enabled input. All other inputs including CLK are disabled and
ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh,
supplying stable CLK inputs, asserting DESEL or NOP command and then asserting CKE=H. After
tRFC from the 1st CLK edge following CKE=H, all banks are in idle state and a new command can be
issued, but DESEL or NOP commands must be asserted till then.

new command

Self-Refresh

CLK

/CS

/RAS

/CAS

/WE

CKE

NOP

Self Refresh Entry

Self Refresh Exit

Stable CLK

A0-12

BA0-1

minimum tRFC

for recovery

M2V56S20/ 30/ 40 TP 5,-5L, -6,-6L, -7,-7L

SDRAM (Rev.1.5E)

Single Data Rate

Oct.2001

256M Synchronous DRAM

MITSUBISHI LSIs

Preliminary

MITSUBISHI ELECTRIC

CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By

negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output
suspend or input suspend. CKE is a synchronous input except during the self-refresh mode. CLK
suspend can be performed either when the banks are active or idle. A command at the suspend cycle is
Ignored.

CLK SUSPEND and POWER DOWN

tIH

tIS

tIH

tIS

ext.CLK

CKE

int. CLK

CLK

Command

CKE

PRE NOP

NOP

CKE

ACT NOP

NOP

Command

CLK

Command

Write

Read

CKE

Active Power Down

DQ Suspend by CKE

Power Down by CKE

Standby Power Down

M2V56S20/ 30/ 40 TP 5,-5L, -6,-6L, -7,-7L

SDRAM (Rev.1.5E)

Single Data Rate

Oct.2001

256M Synchronous DRAM

MITSUBISHI LSIs

Preliminary

MITSUBISHI ELECTRIC

Symbol

Parameter

Conditions

Ratings

Unit

Vdd

Supply Voltage

with respect to Vss

-0.5 ~ 4.6

VddQ

Supply Voltage for Output

with respect to VssQ

-0.5 ~ 4.6

Input Voltage

with respect to Vss

-0.5 ~ Vdd+0.5

Output Voltage

with respect to VssQ

-0.5 ~ Vdd+0.5

Output Current

Power Dissipation

Ta=25°C

1000

Topr

Operating Temprature

0 ~ 70

°C

Tstg

Storage Tempreture

-65 ~ 150

°C

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

(Ta=0 ~ 70 °C, unless otherwise noted)

Min.

Typ.

Max.

Vdd

Supply Voltage

3.0

3.3

3.6

Vss

Supply Voltage

VddQ

Supply Voltage for Output

3.0

3.3

3.6

VssQ

Supply Voltage for Output

VIH

High-Level Input Voltage all inputs

2.0

Vdd+0.3

VIL

Low-Level Input Voltage all inputs

-0.3

0.8

Parameter

Symbol

Unit

Limits

CAPACITANCE

(Ta=0 ~ 70 °C, Vdd= VddQ= 3.3 ± 0.3V, Vss=VssQ=0V, unless otherwise noted)

Min.

Max.

CI(A)

Input Capacitance,address pin

2.5

3.8

CI(C)

Input Capacitance,control pin

VI=1.4V

2.5

3.8

CI(K)

Input Capacitance,CLK pin

f=1MHz

2.5

3.5

CI/O

Input Capacitance,I/O pin

VI=25mVrms

6.5

Unit

Symbol

Parameter

Test Condition

Limits

M2V56S20/ 30/ 40 TP 5,-5L, -6,-6L, -7,-7L

SDRAM (Rev.1.5E)

Single Data Rate

Oct.2001

256M Synchronous DRAM

MITSUBISHI LSIs

Preliminary

MITSUBISHI ELECTRIC

AVERAGE SUPPLY CURRENT from Vdd

(Ta=0 ~ 70°C, Vdd= VddQ= 3.3 ± 0.3V, Vss= VssQ= 0V, Output Open, unless otherwise noted)

Notes
1.

addresses are changed 3 times during tRC, only 1 bank is active & all other banks are idle

all banks are idle

input signals are changed one time during 3xtCLK

input signals are stable

all banks are active

Low Power Version (-5L/-6L/-7L)

Min.

Max.

VOH(DC)

High-Level Output Voltage(DC)

IOH=-2mA

2.4

VOL(DC)

Low-Level Output Voltage(DC)

IOL=2mA

0.4

IOZ

Off-state Output Current

Q floating Vo=0 ~ VddQ

-10

Input Current

VIH=0 ~ VddQ+0.3V, other input pins=0V

-10

Unit

Symbol

Parameter

Test Conditions

Limits

AC OPERATING CONDITIONS AND CHARACTERISTICS

(Ta=0 ~ 70°C, Vdd= VddQ= 3.3 ± 0.3V, Vss= VssQ= 0V, unless otherwise noted)

µA

organi
zation

-5

-6

-7

×4

110

Operating Current

×8

110

(1bank)

×16

120

100

Icc2P

Idle Stanby Current

tCLK=min, CKE<VILmax

1.5

Icc2PS in Power Down Mode CLK=L, CKE<VILmax

Idle Stanby Current

tCLK=min, CKE>VIHmin,

in Normal Mode

/CS>VIHmin

Icc2NS

CLK=L, CKE>VIHmin

2,4

Icc3P

Active Standy

tCLK=min, CKE<VILmax

Current
in Power Down Mode
Active Standy

tCLK=min, CKE>VIHmin

Current

/CS>VIHmin

Icc3NS in Normal Mode

CLK=L, CKE>VIHmin

4,5

×4

140

110

Burst Operating

tCLK=min,BL=4, gapless

×8

140

110

Current

data

×16

150

120

100

Icc5

Auto-Refresh Current

tCLK=min,tRFC=min

220

180

170

-5L/-6L/-7L

Icc6

Self-Refresh Current

Icc2N

2,3

CKE<0.2v -5/-6/-7

Unit

Note

Icc1

tCLK=min, tRC=min, BL=1

Symbol

Parameter

Test Conditions

Limits(max)

Icc3PS

CLK=L, CKE<VILmax

3,5

Icc4

Icc3N

M2V56S20/ 30/ 40 TP 5,-5L, -6,-6L, -7,-7L

SDRAM (Rev.1.5E)

Single Data Rate

Oct.2001

256M Synchronous DRAM

MITSUBISHI LSIs

Preliminary

MITSUBISHI ELECTRIC

AC TIMING REQUIREMENTS

(Ta=0 ~ 70°C, Vdd= VddQ= 3.3 ± 0.3V, Vss= VssQ= 0V, unless otherwise noted)

Input Pulse Levels: 0.8V to 2.0V
Input Timing Measurement Level: 1.4V

1.4V

CLK

Signal

AC timing is referenced to the

input signal crossing through

1.4V.

Min.

Max.

Min.

Max.

Min.

Max.

CL=2

7.5

CL=3

7.5

tCH

CLK High pulse width

2.5

tCL

CLK Low pulse width

2.5

Transition time of CLK

tIS

Input Setup time (all inputs)

1.5

tIH

Input Hold time (all inputs)

0.8

tRC

Row Cycle time

67.5

tRFC

Refresh Cycle time

tRCD

Row to Column Delay

tRP

Row Precharge time

tWR

Write Recovery time

tRRD

ACT to ACT Delay time

Mode Register Set Cycle
time

tREF

Average Refresh Interval

7.8

Unit Note

Limits

Symbol

Parameter

-5

-6

-7

tCLK

tRAS

120000

tRSC

Row Active time

120000

120000 ns

CLK cycle time

µs

M2V56S20/ 30/ 40 TP 5,-5L, -6,-6L, -7,-7L

SDRAM (Rev.1.5E)

Single Data Rate

Oct.2001

256M Synchronous DRAM

MITSUBISHI LSIs

Preliminary

MITSUBISHI ELECTRIC

SWITCHING CHARACTERISTICS

(Ta=0 ~ 70°C, Vdd= VddQ= 3.3 ± 0.3V, Vss= VssQ= 0V, unless otherwise noted)

Min.

Max.

Min.

Max.

Min.

Max.

CL=2

5.4

CL=3

5.4

CL=2

CL=3

Delay Time, Output Low

impedance from CLK

Delay Time, Output High

impedance from CLK

Limits

Symbol

Parameter

-5

-6

-7

CL=2

5.4

tAC

tOH

tOLZ

tOHZ

5.4

CL=3

Access Time from CLK

Output Hold Time from CLK

Unit

Note. If tr (CLK rising time) is > 1ns, (tr/2 0.5ns) should be added to the parameters.

Output Load Condition

Vout

50pF

tOHZ

tOH

tOLZ

tAC

CLK

1.4V

M2V56S20/ 30/ 40 TP 5,-5L, -6,-6L, -7,-7L

SDRAM (Rev.1.5E)

Single Data Rate

Oct.2001

256M Synchronous DRAM

MITSUBISHI LSIs

Preliminary

MITSUBISHI ELECTRIC

1. These materials are intended as a reference to assist our customers in the selection of the Mitsubishi
semiconductor product best suited to the customer's application; they do not convey any license

under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or
a third party.
2. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any
third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms,
or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and

algorithms represents information on products at the time of publication of these materials, and are
subject to change by Mitsubishi Electric Corporation without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an
authorized Mitsubishi Semiconductor product distributor for the latest product information before
purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors. Mitsubishi

Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these
inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric
Corporation by various means, including the Mitsubishi Semiconductor home page
(http://www.mitsubishichips.com).
4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total

system before making a final decision on the applicability of the information and products. Mitsubishi
Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the
Information contained herein.
5. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device
or system that is used under circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi semiconductor product distributor when

considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in
whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must
be exported under a license from the Japanese government and cannot be imported into a country other

than the approved destination. Any diversion or reexport contrary to the export control laws and
regulations of Japan and /or the country of destination is prohibited.
8. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for further details on these materials or the products contained therein.

Notes regarding these materials

Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better
and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due
consideration to safety when making your circuit designs, with appropriate measures such as (i)
placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention
against any malfunction or mishap.

Keep safety first in your circuit designs !

M2V56S20/ 30/ 40 TP 5,-5L, -6,-6L, -7,-7L

SDRAM (Rev.1.5E)

Single Data Rate

Oct.2001

256M Synchronous DRAM

MITSUBISHI LSIs

Preliminary

MITSUBISHI ELECTRIC

Rev.

Date

Description

1.0

July/ '99 1st edition

1.1

Feb. / '00 -Remove "Power-Down" from Function Truth Table for CKE Note2

-Modify Average Supply Current from Vdd
Icc2N,Icc3N Test Condition(/CS > VIHmin)
Icc3PS Limits (from 3mA to 4mA)
Icc5 Limits (from 160/150mA to 180/170mA)

Icc6 Test Condition (CKE<0.2V)
Icc6 Limits (from 2mA to 3mA)
-Change Switching Characteristics tAC of -8 for CL=2 from 6ns to 7ns

-Add Note to Switching Characteristics

-Change Output Load Condition to 50pF only

-Remove tCCD from AC Timing Requirements

1.2

Jan. / '01 -Add -5 spec. for M2V56S20TP only

1.3

Feb. / '01 -Add 166MHz of 3-3-3 for M2V56S20TP only

1.4

Mar. / '01 -Add -5 spec. for M2V56S20TP/30TP/40TP

1.45

May / '01 -Add Low Power Ver. -5L/-6L/-7L spec. for M2V56S20TP/30TP/40TP

1.5

Oct. / '01 -Change POWER ON SEQUENCE

(2. 200us=>100us
4. 8or more auto-refresh commands => 2 or more auto-refresh commands)
-Change AC Timing Requirements tRFC of -5 from 60ns to 66ns

-Change AC Timing Requirements tRSC of (-5/-6/-7)
from (12ns/15ns/20ns) to (10ns/10ns/10ns)

Revision History

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: M2V56S30TP-5

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: M2V56S30TP-5