Feb.'00

MITSUBISHI LSIs

MITSUBISHI ELECTRIC

SDRAM (Rev.3.2)

64M Synchronous DRAM

M2V64S20DTP-6,-6L,-7,-7L,-8,-8L

(4-BANK x 4,194,304-WORD x 4-BIT)
(4-BANK x 2,097,152-WORD x 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)

M2V64S30DTP-6,-6L,-7,-7L,-8,-8L

M2V64S40DTP-6,-6L,-7,-7L,-8,-8L

M 2V64S20DTP is a 4-bank x 4,194,304-word x 4-bit,

M 2V64S30DTP is a 4-bank x 2,097,152-word x 8-bit,

M 2V64S40DTP is a 4-bank x 1,048,576-word x 16-bit,

synchronous DRAM , with LVTTL interface. All inputs and outputs are referenced to the rising edge

of CLK. M 2V64S20DTP, M 2V64S30DTP and M 2V64S40DTP achieve very high speed data rate up

to 133MHz for -6, and are suitable for main memory or graphic memory in computer systems.

- Single 3.3v�0.3V power sup p ly

- Max. Clock frequency -6:133MHz<3-3-3>, -7:100MHz<2-2-2>, -8:100MHz<3-2-2>

- Fully Synchronous operation referenced to clock rising edge

- 4 bank operation controlled by BA0 & BA1 (Bank Address)

- /CAS latency- 2 and 3 (programmable)

- Burst length- 1, 2, 4, 8 and full page (programmable)

- Burst ty p e- sequential and interleave (programmable)

- Byte Control- DQM L and DQMU for M2V64S40DTP

- Random column access

- Auto p recharge and All bank precharge controlled by A10

- Auto refresh and Self refresh

- 4096 refresh cycles every 64ms

- LVTTL Interface

- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch

DESCRIPTION

FEATURES

PRELIMINARY

Some of contents are described for general products and are

subject to change w ithout notice.

ITEM

tCLK

M2V64S20/30/40DTP

-7

-8

tRAS

tRCD

tAC

tRC

Icc1

Icc6

Clock Cycle T ime

(Min.)

Active to Precharge Command Period

(Min.)

Row to Column Delay

(Min.)

Access Time from CLK

(Max.) (CL=3)

Ref /Active Command Period

(Min.)

Operation Current

(Max.)

(Single Bank)

Self Refresh Current

(Max.)

10ns

50ns

20ns

6ns

70ns

1mA

10ns

50ns

20ns

6ns

70ns

1mA

V64S20D

V64S30D

V64S40D

-6

7.5ns

45ns

20ns

5.4ns

67.5ns

1mA

70mA

80mA

70mA

80mA

75mA

85mA

Feb.'00

MITSUBISHI LSIs

MITSUBISHI ELECTRIC

SDRAM (Rev.3.2)

64M Synchronous DRAM

M2V64S20DTP-6,-6L,-7,-7L,-8,-8L

(4-BANK x 4,194,304-WORD x 4-BIT)
(4-BANK x 2,097,152-WORD x 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)

M2V64S30DTP-6,-6L,-7,-7L,-8,-8L

M2V64S40DTP-6,-6L,-7,-7L,-8,-8L

PIN CONFIGURATION (TOP VIEW)

M2V64S30DTP

M2V64S40DTP

PIN CONFIGURATION

(TOP VIEW)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

Vdd
DQ0
VddQ
DQ1
DQ2
VssQ
DQ3
DQ4
VddQ
DQ5
DQ6
VssQ
DQ7
Vdd
DQML
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10(AP)

A2
A3
Vdd

A0
A1

Vss
DQ15
VssQ
DQ14
DQ13
VddQ
DQ12
DQ11
VssQ
DQ10
DQ9
VddQ
DQ8
Vss

DQMU
CLK
CKE
NC
A11

A8
A7
A6
A5
A4
Vss

Vdd
DQ0
VddQ
NC
DQ1
VssQ
NC
DQ2
VddQ
NC
DQ3
VssQ
NC
Vdd
NC
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10(AP)

A2
A3
Vdd

A0
A1

Vdd
NC
VddQ
NC
DQ0
VssQ
NC
NC
VddQ
NC
DQ1
VssQ
NC
Vdd
NC
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10(AP)

A2
A3
Vdd

A0
A1

Vss
DQ7
VssQ
NC
DQ6
VddQ
NC
DQ5
VssQ
NC
DQ4
VddQ
NC
Vss

DQM
CLK
CKE
NC
A11

A8
A7
A6
A5
A4
Vss

Vss
NC
VssQ
NC
DQ3
VddQ
NC
NC
VssQ
NC
DQ2
VddQ
NC
Vss

DQM
CLK
CKE
NC
A11

A8
A7
A6
A5
A4
Vss

M2V64S20DTP

CLK

: Master Clock

CKE

: Clock Enable

/CS

: Chip Select

/RAS

: Row Address Strobe

/CAS

: Column Address Strobe

/WE

: Write Enable

DQ0-15

: Data I/O

DQM

: Output Disable/ Write Mask

A0-11

: Address Input

BA0,1

: Bank Address

Vdd

: Power Supply

VddQ

: Power Supply for Output

Vss

: Ground

VssQ

: Ground for Output

Feb.'00

MITSUBISHI LSIs

MITSUBISHI ELECTRIC

SDRAM (Rev.3.2)

64M Synchronous DRAM

M2V64S20DTP-6,-6L,-7,-7L,-8,-8L

(4-BANK x 4,194,304-WORD x 4-BIT)
(4-BANK x 2,097,152-WORD x 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)

M2V64S30DTP-6,-6L,-7,-7L,-8,-8L

M2V64S40DTP-6,-6L,-7,-7L,-8,-8L

BLOCK DIAGRAM

Type Designation Code

M2 V 64 S 3 0

-8

Access Item

P ackage T ype

P rocess Generation

Interface

Organization

Synchronous DRAM

Density

Function

Mitsubishi DRAM

These rules are only applied to the Synchronous DRAM family.

Note : This figure shows the M2V64S30DTP.

The M2V64S20DTP configration is 4096x1024x4 of cell array and DQ 0-3.
The M2V64S40DTP configration is 4096x256x16 of cell array and DQ 0-15.

Address Buffer

A0-11

BA0,1

Control Signal Buffer

/CS

/RAS

/CAS

/WE

CLK

CKE

Clock Buffer

Control Circuitry

I/O Buffer

DQ0-7

Mode

DQM

Memory Array

Bank #0

4096 x512 x8

Cell Array

Memory Array

Bank #1

4096 x512 x8

Cell Array

Memory Array

Bank #2

4096 x512 x8

Cell Array

Memory Array

Bank #3

4096 x512 x8

Cell Array

-6 : 7.5ns (PC133 3-3-3),

-7 : 10ns (PC100 2-2-2),

-8 : 10ns (PC100 3-2-2)

T P : T S O P (II)

D : 5th gen.

R eserved for Future Use

2 : x4, 3 : x8, 4 : x16

64 : 64Mbit

V : LVT T L

Feb.'00

MITSUBISHI LSIs

MITSUBISHI ELECTRIC

SDRAM (Rev.3.2)

64M Synchronous DRAM

M2V64S20DTP-6,-6L,-7,-7L,-8,-8L

(4-BANK x 4,194,304-WORD x 4-BIT)
(4-BANK x 2,097,152-WORD x 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)

M2V64S30DTP-6,-6L,-7,-7L,-8,-8L

M2V64S40DTP-6,-6L,-7,-7L,-8,-8L

PIN FUNCTION

CLK

Input

Master Clock:

All other inputs are referenced to the rising edge of CLK.

CKE

Input

Clock Enable:

CKE controls internal clock. When CKE is low, internal clock for the

following cycle is ceased. CKE is also used to select auto /

selfrefresh. After self refresh mode is started, CKE becomes

asynchronous input. Self refresh is maintained as long as CKE is low.

/CS

Input

Chip Select:

When /CS is high, any command means No Operation.

/RAS, /CAS, /WE

Input

Combination of /RAS, /CAS, /WE defines basic commands.

A0-11

Input

A0-11 specify the Row / Column Address in conjunction with BA0,1.

The Row Address is specified by A0-11. The Column Address is

specified by A0-9 (x4) / A0-8 (x8) / A0-7 (x16).

A10 is also used to indicate precharge option. When A10 is high at a

read / write command, an auto precharge is performed. When A10 is

high at a precharge command, all banks are precharged.

BA0,1

Input

Bank Address:

BA0,1 specifies one of four banks to which a command is applied.

BA0,1 must be set with ACT, PRE, READ, WRITE commands.

Input / Output

Input

Din Mask and Output Disable:

When DQM(U, L) is high in burst write, Din for the current cycle is

masked. When DQM(U, L) is high in burst read, Dout is disabled at

the next but one cycle.

Vdd, Vss

Power Supply

Power Supply for the memory array and peripheral circuitry.

VddQ, VssQ

Power Supply

VddQ and VssQ are supplied to the Output Buffers only.

Data In and Data out are referenced to the rising edge of CLK.

DQ0-3(x4),

DQ0-7(x8),

DQ0-15(x16)

DQM(x4,x8),

DQM(U, L)(x16)

Feb.'00

MITSUBISHI LSIs

MITSUBISHI ELECTRIC

SDRAM (Rev.3.2)

64M Synchronous DRAM

M2V64S20DTP-6,-6L,-7,-7L,-8,-8L

(4-BANK x 4,194,304-WORD x 4-BIT)
(4-BANK x 2,097,152-WORD x 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)

M2V64S30DTP-6,-6L,-7,-7L,-8,-8L

M2V64S40DTP-6,-6L,-7,-7L,-8,-8L

BASIC FUNCTIONS

The M 2V64S20, 30 and 40DTP p rovides basic functions, bank (row) activate, burst read and write, bank
(row) precharge, and auto and self refresh. Each command is defined by control signals of /RAS, /CAS and
/WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option,
and precharge option, respectively. To know the detailed definition of commands, please see the command
truth table.

Activate (ACT) [/RAS =L, /CAS =/WE =H]

ACT command activates a row in an idle bank indicated by BA.

Read (READ) [/RAS =H, /CAS =L, /WE =H]

READ command starts burst read from the active bank indicated by BA. First output data appears after
/CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-
precharge,

READA

)

Write (WRITE) [/RAS =H, /CAS =/WE =L]

WRITE command starts burst write to the active bank indicated by BA. Total data length to be written
is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write
(auto-p recharge,

WRITEA

Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]

PRE command deactivates the active bank indicated by BA. This command also terminates burst read
/write operation. When A10 =H at this command, all banks are deactivated (p recharge all,

PREA

Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]

REFA command starts auto-refresh cy cle. Refresh address are generated internally. After this
command, the banks are precharged automatically.

/CS

Chip Select : L=select, H=deselect

/RAS

Command

/CAS

Command

/WE

Command

CKE

Ref resh Option @ref resh command

A10

Precharge Option @precharge or read/write command

CLK

def ine basic commands

Электронный компонент: M2V64S20DTP-8