MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
1
DESCRIPTION
M2V64S20BTP is organized as 4-bank x4,194,304-word x 4-bit,and M2V64S30BTP is organized
as 4-bank x 2097152-word x 8-bit ,and M2V64S40BTP is organized as 4-bank x 1048576-word x 16-bit
Synchronous DRAM with LVTTL interface. All inputs and outputs are referenced to the rising edge of
CLK. M2V64S20BTP,M2V64S30BTP,M2V64S40BTP achieves very high speed data rates up to
133MHz, and is suitable for main memory or graphic memory in computer systems.
FEATURES
- Single 3.3V 0.3V power supply
- Max. Clock frequency
-6 : 133MHz [PC133<3-3-3> ]
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0,BA1(Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Auto and self refresh
- 4096 refresh cycles /64ms
- LVTTL Interface
- Package 400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
PRELIMINARY
Some of contents are described for general products and are
subject to change without notice.
ITEM
tCLK
M2V64S20TP
tRAS
tRCD
tAC
tRC
Icc1
Icc6
Clock Cycle Time
(Min.)
Active to Precharge Command Period
(Min.)
Row to Column Delay
(Min.)
Access Time from CLK
(Max.) (CL=3)
Ref/Active Command Period
(Min.)
Operation Current (Max.) [Single Bank]
Self Refresh Current
(Max.)
-6
7.5ns
45ns
20.0ns
5.4ns
67.5ns
1mA
120mA
M2V64S30TP
M2V64S40TP
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
2
CLK
: Master Clock
CKE
: Clock Enable
/CS
: Chip Select
/RAS
: Row Address Strobe
/CAS
: Column Address Strobe
/WE
: Write Enable
DQ0-3(x4), DQ0-7(x8), DQ0-15(x16) : Data I/O
DQM (x4, x8) ,DQML/U (x16)
: Output Disable/ Write Mask
A0-11
: Address Input
BA0,1
: Bank Address
Vdd
: Power Supply
VddQ
: Power Supply for Output
Vss
: Ground
VssQ
: Ground for Output
PIN CONFIGURATION (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Vdd
DQ0
VddQ
DQ2
VssQ
DQ4
VddQ
DQ6
VssQ
Vdd
DQML
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10
Vss
DQ15
VssQ
DQ13
VddQ
DQ11
VssQ
DQ9
VddQ
Vss
NC
DQMU
CLK
CKE
NC
A11
A8
A7
23
32
24
31
25
30
26
29
27
28
A2
A3
Vdd
A0
A1
A6
A5
A4
Vss
A9
DQ1
DQ3
DQ5
DQ7
DQ8
DQ10
DQ12
DQ14
VddQ
DQ0
VssQ
VddQ
DQ1
VssQ
/CAS
/RAS
BA0(A13)
BA1(A12)
Vdd
NC
NC
NC
NC
Vdd
NC
/WE
/CS
A10
A2
A3
Vdd
A0
A1
NC
NC
Vss
VssQ
NC
DQ3
VddQ
NC
VssQ
NC
DQ2
VddQ
NC
Vss
NC
DQM
CLK
CKE
NC
A11
A8
A7
A6
A5
A4
Vss
A9
NC
NC
Vss
DQ7
VssQ
NC
DQ6
VddQ
NC
DQ5
VssQ
NC
DQ4
VddQ
NC
Vss
NC
DQM
CLK
CKE
NC
A11
A8
A7
A6
A5
A4
Vss
A9
Vdd
DQ0
VddQ
NC
DQ1
VssQ
NC
DQ2
VddQ
NC
DQ3
VssQ
NC
Vdd
NC
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10
A2
A3
Vdd
A0
A1
M2V64S40BTP
M2V64S30BTP
M2V64S20BTP
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
3
BLOCK DIAGRAM
Address Buffer
A0-11 BA0,1
Control Signal Buffer
/CS /RAS /CAS /WE DQM
CLK CKE
Clock Buffer
Memory Array
Bank #0
Control Circuitry
I/O Buffer
DQ0-3 (x4)
DQ0-7 (x8)
DQ0-15 (x16)
Mode
Register
Memory Array
Bank #1
Memory Array
Bank #2
Memory Array
Bank #3
Type Designation Code
M2 V 64 S 2 0 B TP - 7
Access Item
Package Type TP: TSOP(II)
Process Generation
Function 0: Random Column
Organization 2n 2: x4, 3: x8, 4: x16
Synchronous DRAM
Density 64:64M bits
Interface S: SSTL, V:LVTTL
Mitsubishi Semiconductor Memory
This rule is applied only to Synchronous DRAM families beyond 64M B-version.
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
4
PIN FUNCTION
CLK
Input
Master Clock: All other inputs are referenced to the rising edge of CLK.
CKE
Input
Clock Enable: CKE controls internal clock. When CKE is low, internal clock
for the following cycle is ceased. CKE is also used to select auto / self
refresh. After self refresh mode is started, CKE becomes asynchronous
input. Self refresh is maintained as long as CKE is low.
/CS
Input
Chip Select: When /CS is high, any command means No Operation.
/RAS, /CAS, /WE
Input
Combination of /RAS, /CAS, /WE defines basic commands.
A0-11
Input
A0-11 specify the Row / Column Address in conjunction with BA0,1. The
Row Address is specified by A0-11. The Column Address is specified by
A0-A9(x4), A0-A8(x8), A0-7(x16) . A10 is also used to indicate precharge
option. When A10 is high at a read / write command, an auto precharge
is performed. When A10 is high at a precharge command, all banks are
precharged.
BA0,1
Input
Bank Address: BA0,1 specifies one of four banks to which a command is
applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.
DQ0-3(x4),
DQ0-7(x8),
DQ0-15(x16)
Input / Output
Data In and Data out are referenced to the rising edge of CLK.
DQM(x4,x8),
DQMU/L(x16)
Input
Din Mask / Output Disable: When DQMU/L is high in burst write, Din for the
current cycle is masked. When DQMU/L is high in burst read,
Dout is disabled at the next but one cycle.
Vdd, Vss
Power Supply
Power Supply for the memory array and peripheral circuitry.
VddQ, VssQ
Power Supply
VddQ and VssQ are supplied to the Output Buffers only.
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
5
BASIC FUNCTIONS
The M2V64S20(30,40)BTP provides basic functions, bank (row) activate, burst read / write,
bank (row) precharge, and auto / self refresh.
Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In
addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and
precharge option, respectively. To know the detailed definition of commands, please see the
command truth table.
/CS
Chip Select : L=select, H=deselect
/RAS
Command
/CAS
Command
/WE
Command
CKE
Refresh Option @refresh command
A10
Precharge Option @precharge or read/write command
CLK
define basic commands
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data
appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the
burst read (auto-precharge,
READA).
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be
written is set by burst length. When A10 =H at this command, the bank is deactivated after the
burst write (auto-precharge,
WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates
burst read /write operation. When A10 =H at this command, both banks are deactivated
(precharge all,
PREA).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address are
generated inter-nally. After this command, the banks are precharged automatically.
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
6
COMMAND TRUTH TABLE
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE:
1. A7-A9 =0, A0-A6 =Mode Address
COMMAND
MNEMONIC
CKE
n-1
CKE
n
/CS
/RAS
/CAS
/WE
BA0,1
A11
A10
A0-9
Deselect
DESEL
H
X
H
X
X
X
X
X
X
X
No Operation
NOP
H
X
L
H
H
H
X
X
X
X
Row Address Entry &
Bank Activate
ACT
H
X
L
L
H
H
V
V
V
V
Single Bank Precharge
PRE
H
X
L
L
H
L
V
X
L
X
Precharge All Banks
PREA
H
X
L
L
H
L
X
H
X
Column Address Entry
& Write
WRITE
H
X
L
H
L
L
V
X
L
V
Column Address Entry
& Write with Auto-
Precharge
WRITEA
H
X
L
H
L
L
V
X
H
V
Column Address Entry
& Read
READ
H
X
L
H
L
H
V
X
L
V
Column Address Entry
& Read with Auto-
Precharge
READA
H
X
L
H
L
H
V
X
H
V
Auto-Refresh
REFA
H
H
L
L
L
H
X
X
X
X
Self-Refresh Entry
REFS
H
L
L
L
L
H
X
X
X
X
Self-Refresh Exit
REFSX
L
H
H
X
X
X
X
X
X
X
L
H
L
H
H
H
X
X
X
X
Burst Terminate
TBST
H
X
L
H
H
L
X
Mode Register Set
MRS
H
X
L
L
L
L
L
L
L
V*1
X
X
X
X
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
7
FUNCTION TRUTH TABLE
Current State
/CS
/RAS
/CAS
/WE
Address
Command
Action
IDLE
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
TBST
ILLEGAL*2
L
H
L
X
BA, CA, A10
READ / WRITE ILLEGAL*2
L
L
H
H
BA, RA
ACT
Bank Active, Latch RA
L
L
H
L
BA, A10
PRE / PREA
NOP*4
L
L
L
H
X
REFA
Auto-Refresh*5
L
L
L
L
Op-Code,
Mode-Add
MRS
Mode Register Set*5
ROW ACTIVE
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
TBST
NOP
L
H
L
H
BA, CA, A10
READ / READA
Begin Read, Latch CA,
Determine Auto-Precharge
L
H
L
L
BA, CA, A10
WRITE /
WRITEA
Begin Write, Latch CA,
Determine Auto-Precharge
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
Precharge / Precharge All
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
READ
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
BA
TBST
Terminate Burst
L
H
L
H
BA, CA, A10
READ / READA
Terminate Burst, Latch CA,
Begin New Read, Determine
Auto-Precharge*3
L
H
L
L
BA, CA, A10
WRITE /
WRITEA
Terminate Burst, Latch CA,
Begin Write, Determine Auto-
Precharge*3
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
Terminate Burst, Precharge
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
8
FUNCTION TRUTH TABLE (continued)
Current State
/CS
/RAS
/CAS
/WE
Address
Command
Action
WRITE
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
BA
TBST
Terminate Burst
L
H
L
H
BA, CA, A10
READ / READA
Terminate Burst, Latch CA,
Begin Read, Determine Auto-
Precharge*3
L
H
L
L
BA, CA, A10
WRITE /
WRITEA
Terminate Burst, Latch CA,
Begin Write, Determine Auto-
Precharge*3
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
Terminate Burst, Precharge
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
READ with
AUTO
PRECHARGE
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
BA
TBST
ILLEGAL
L
H
L
H
BA, CA, A10
READ / READA ILLEGAL
L
H
L
L
BA, CA, A10
WRITE /
WRITEA
ILLEGAL
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL*2
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
WRITE with
AUTO
PRECHARGE
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
BA
TBST
ILLEGAL
L
H
L
H
BA, CA, A10
READ / READA ILLEGAL
L
H
L
L
BA, CA, A10
WRITE /
WRITEA
ILLEGAL
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL*2
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
9
FUNCTION TRUTH TABLE (continued)
Current State
/CS
/RAS
/CAS
/WE
Address
Command
Action
PRE -
CHARGING
H
X
X
X
X
DESEL
NOP (Idle after tRP)
L
H
H
H
X
NOP
NOP (Idle after tRP)
L
H
H
L
BA
TBST
ILLEGAL*2
L
H
L
X
BA, CA, A10
READ / WRITE ILLEGAL*2
L
L
H
H
BA, RA
ACT
ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
NOP*4 (Idle after tRP)
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
ROW
ACTIVATING
H
X
X
X
X
DESEL
NOP (Row Active after tRCD)
L
H
H
H
X
NOP
NOP (Row Active after tRCD)
L
H
H
L
BA
TBST
ILLEGAL*2
L
H
L
X
BA, CA, A10
READ / WRITE ILLEGAL*2
L
L
H
H
BA, RA
ACT
ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL*2
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
WRITE RE-
COVERING
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
TBST
ILLEGAL*2
L
H
L
X
BA, CA, A10
READ / WRITE ILLEGAL*2
L
L
H
H
BA, RA
ACT
ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL*2
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
10
FUNCTION TRUTH TABLE (continued)
Current State
/CS
/RAS
/CAS
/WE
Address
Command
Action
RE-
FRESHING
H
X
X
X
X
DESEL
NOP (Idle after tRC)
L
H
H
H
X
NOP
NOP (Idle after tRC)
L
H
H
L
BA
TBST
ILLEGAL
L
H
L
X
BA, CA, A10
READ / WRITE ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
MODE
REGISTER
SETTING
H
X
X
X
X
DESEL
NOP (Idle after tRSC)
L
H
H
H
X
NOP
NOP (Idle after tRSC)
L
H
H
L
BA
TBST
ILLEGAL
L
H
L
X
BA, CA, A10
READ / WRITE ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No OPeration
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the
state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and/or data-integrity are not guaranteed.
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
11
Current State
CKE
n-1
CKE
n
/CS
/RAS /CAS
/WE
Add
Action
SELF-
REFRESH*1
H
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
Exit Self-Refresh (Idle after tRC)
L
H
L
H
H
H
X
Exit Self-Refresh (Idle after tRC)
L
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP (Maintain Self-Refresh)
POWER
DOWN
H
X
X
X
X
X
X
INVALID
L
H
X
X
X
X
X
Exit Power Down to Idle
L
L
X
X
X
X
X
NOP (Maintain Self-Refresh)
ALL BANKS
IDLE*2
H
H
X
X
X
X
X
Refer to Function Truth Table
H
L
L
L
L
H
X
Enter Self-Refresh
H
L
H
X
X
X
X
Enter Power Down
H
L
L
H
H
H
X
Enter Power Down
H
L
L
H
H
L
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
X
X
X
ILLEGAL
L
X
X
X
X
X
X
Refer to Current State =Power Down
ANY STATE
other than
listed above
H
H
X
X
X
X
X
Refer to Function Truth Table
H
L
X
X
X
X
X
Begin CLK Suspend at Next Cycle*3
L
H
X
X
X
X
X
Exit CLK Suspend at Next Cycle*3
L
L
X
X
X
X
X
Maintain CLK Suspend
FUNCTION TRUTH TABLE for CKE
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
NOTES:
1. CKE Low to High transition will re-enable CLK and other inputs
asynchronously. A minimum setup
time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
3. Must be legal command.
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
12
ROW
ACTIVE
IDLE
PRE
CHARGE
AUTO
REFRESH
SELF
REFRESH
MODE
REGISTER
SET
POWER
DOWN
READ
READA
WRITE
WRITEA
READ
SUSPEND
READA
SUSPEND
WRITE
SUSPEND
WRITEA
SUSPEND
POWER
ON
CLK
SUSPEND
CKEL
CKEH
CKEL
CKEH
CKEL
CKEH
CKEL
CKEH
ACT
REFA
REFS
REFSX
CKEL
CKEH
MRS
CKEL
CKEH
WRITE
READ
WRITEA
WRITEA
READA
WRITE
READ
PRE
READA
WRITEA
READA
PRE
PRE
PRE
POWER
APPLIED
Automatic Sequence
Command Sequence
SIMPLIFIED STATE DIAGRAM
TBST (for Full Page)
TBST (for Full Page)
MITSUBISHI ELECTRIC
Oct. '99
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PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
13
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a
SDRAM from damaged or malfunctioning.
1.Clock will be applied at power up along with power. Attempt to maintain CKE high,
DQM (x4,x8), DQMU/L (x16) high and NOP condition at the inputs along with power.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200us.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be
programmed by setting the mode register (MRS). The mode
register stores these data until the next MRS command, which
may be issued when both banks are in idle state. After tRSC
from a MRS command, the SDRAM is ready for new command.
R: Reserved for Future Use
BL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
BURST
LENGTH
BT= 0
BT= 1
1
2
4
8
R
R
R
FP
1
2
4
8
R
R
R
R
0
1
BURST
TYPE
SEQUENTIAL
INTERLEAVE
A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA1
BA0
0
0
WM
0
0
LTMODE
BT
BL
0
0
CL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
LATENCY
MODE
/CAS LATENCY
2
3
R
R
R
R
R
R
/CS
/RAS
/CAS
/WE
BA0,1 A11-A0
CLK
V
FP: Full Page
0
1
WRITE
MODE
BURST
SINGLE BIT
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PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
14
[ /CAS LATENCY ]
/CAS latency, CL, is used to synchronize the first output data with the CLK frequency, i.e., the
speed of CLK determines which CL should be used. First output data is available after CL
cycles from READ command.
/CAS Latency Timing(BL=4)
CLK
Command
Address
X
ACT
READ
Y
tRCD
DQ
Q0
Q1
Q2
Q3
DQ
Q0
Q1
Q2
Q3
CL=2
CL=3
CL=2
CL=3
[ BURST LENGTH ]
The burst length, BL, determines the number of consecutive writes or reads that will be
automatically performed after the initial write or read command. For BL=1,2,4,8, full page the
output data is tristated (Hi-Z) after the last read. For BL=FP (Full Page), the TBST (Burst
Terminate) command should be issued to stop the output of data.
Burst Length Timing( CL=2 )
CLK
Command
Address
tRCD
DQ
Q0
BL=1
DQ
Q0
Q1
BL=2
DQ
Q0
Q1
Q2
Q3
BL=4
DQ
Q0
Q1
Q2
Q3
BL=8
Q4
Q5
Q6
Q7
ACT
READ
X
Y
DQ
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Qm
Q0
Q1
M2V64S20B : m=1023
M2V64S30B : m=511
M2V64S40B : m=255
Full Page counter rolls over
and continues to count.
BL=FP
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PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
15
Command
Address
CLK
Read
Y
Q0
Q1
Q2
Q3
Write
Y
D0
D1
D2
D3
/CAS Latency
Burst Length
Burst Length
DQ
Burst Type
CL= 3
BL= 4
A2
A1
A0
Initial Address
BL
Sequential
Interleaved
Column Addressing
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
-
0
0
-
0
1
-
1
0
-
1
1
-
-
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
7
0
1
2
0
1
2
3
1
2
3
0
2
3
0
1
3
0
0
1
7
6
5
4
0
1
2
3
1
0
3
2
2
3
0
1
3
2
0
1
-
-
1
1
2
1
0
3
4
5
6
3
2
1
0
1
0
1
0
8
4
2
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
16
OPERATIONAL DESCRIPTION
BANK ACTIVATE
The SDRAM has four independent banks. Each bank is activated by the ACT command with
the bank addresses (BA0,1). A row is indicated by the row addresses A11-0. The minimum
activation interval between one bank and the other bank is tRRD.The number of banks which
are active concurrently is not limited.
PRECHARGE
The PRE command deactivates the bank indicated by BA0,1. When multiple banks are active,
the precharge all command (PREA, PRE + A10=H) is available to deactivate them at the same
time. After tRP from the precharge, an ACT command to the same bank can be issued.
READ
After tRCD from the bank activation, a READ command can be issued. 1st output data is
available after the /CAS Latency from the READ, followed by (BL -1) consecutive data when the
Burst Length is BL. The start address is specified by A9-0(x4), A8-0(x8), A7-0(X16), and the
address sequence of burst data is defined by the Burst Type. A READ command may be
applied to any active bank, so the row precharge time (tRP) can be hidden behind continuous
output data by interleaving the multiple banks. When A10 is high at a READ command, the auto-
precharge (READA) is performed. Any command (READ, WRITE, PRE, ACT) to the same bank
is inhibited till the internal precharge is complete. The internal precharge starts at BL after
READA. The next ACT command can be issued after (BL + tRP) from the previous READA.
Command
Bank Activation and Precharge All (BL=4, CL=3)
CLK
A0-9
A10
BA0,1
DQ
ACT
Xa
Xa
00
READ
Y
0
00
Qa0
Qa1
Qa2
Qa3
ACT
Xb
Xb
01
PRE
tRRD
tRCD
1
ACT
Xb
Xb
01
Precharge all
tRAS
tRP
tRCmin
A11
Xa
Xb
Xb
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MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
17
Multi Bank Interleaving READ (BL=4, CL=3)
CLK
Command
A0-9
A10
BA0,1
DQ
ACT
Xa
Xa
00
READ
Y
0
00
READ
Y
0
10
Qa0
Qa1
Qa2
Qa3
Qb0
Qb1
Qb2
ACT
Xb
Xb
10
PRE
0
00
tRCD
/CAS latency
Burst Length
A11
Xa
Xb
READ with Auto-Precharge (BL=4, CL=3)
CLK
Command
A0-9
A10
BA0,1
DQ
ACT
Xa
Xa
00
READ
Y
1
00
Qa0
Qa1
Qa2
Qa3
ACT
Xa
Xa
00
Internal precharge start
tRCD
tRP
A11
Xa
Xa
BL
BL + tRP
READ Auto-Precharge Timing (BL=4)
CLK
Command
ACT
READ
Internal Precharge Start Timing
DQ
DQ
CL=3
CL=2
Qa1
Qa2
Qa3
Qa0
BL
Qa1
Qa2
Qa3
Qa0
MITSUBISHI ELECTRIC
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PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
18
WRITE
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set at the same
cycle as the WRITE. Following (BL -1) data are written into the RAM, when the Burst Length is BL. The start
address is specified by A9-0 (x 4), A8-0 (x 8) and A7-0 (x 16), and the address sequence of burst data is
defined by the Burst Type. A WRITE command may be applied to any active bank, so the row precharge
time (tRP) can be hidden behind continuous input data by interleaving the multiple banks. From the last
input data to the PRE command, the write recovery time (tWR) is required. When A10 is high at a WRITE
command, the auto-precharge (WRITEA) is performed. Any command (READ, WRITE, PRE, ACT) to the
same bank is inhib-ited till the internal precharge is complete. The internal precharge begins at tWR after the
last input data cycle. The next ACT command can be issued after tRP from the internal precharge timing.
The Mode Register can be programmed for burst read and single write. In this mode the write data is only
clocked in when the WRITE command is issued and the remaining burst length is ignored. The read data
burst length os unaffected while in this mode
Multi Bank Interleaving WRITE (BL=4)
CLK
Command
A0-9
A10
BA0,1
DQ
ACT
Xa
Xa
00
Write
Y
00
Write
Y
0
0
10
Da0
ACT
Xb
Xb
10
0
10
tRCD
tRCD
PRE
Xa
A11
Xa
Xb
0
Xa
0
00
PRE
0
Da1
Da2
Da3
Db0
Db1
Db2
Db3
WRITE with Auto-Precharge (BL=4)
tWR
CLK
Command
A0-9
A10
BA0,1
DQ
ACT
Xa
Xa
00
Write
Y
1
00
Da0
Da1
Da2
Da3
ACT
Xa
Xa
00
Internal precharge starts
tRCD
tRP
A11
Xa
Xa
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PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
19
[ BURST WRITE ]
A burst write operation is enabled by setting A9=0 at MRS. A burst write starts in
the same cycle as a write command set. (The latency of data input is 0.) The
burst length can be set to 1,2,4,8, and full-page, like burst read operations.
CLK
Command
Address
tRCD
DQ
D0
BL=1
DQ
D0
D1
BL=2
DQ
D0
D1
D2
D3
BL=4
DQ
D0
D1
D2
D3
BL=8
D4
D5
D6
D7
ACT
WRITE
DQ
D0
D1
D2
D3
D4
D5
D6
D7
D8
Dm
D0
D1
M2V64S20B : m=1023
M2V64S30B : m=511
M2V64S40B : m=255
Full Page counter rolls over
and continues to count.
D9
D10
BL=FP
A single write operation is enabled by setting A9=1 at MRS. In a single write
operation, data is written only to the column address specified by the write
command set cycle without regard to the burst length setting. (The latency of data
input is 0.)
[ SINGLE WRITE ]
CLK
Command
Address
X
ACT
WRITE
Y
tRCD
DQ
D0
MITSUBISHI ELECTRIC
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PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
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M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
20
BURST INTERRUPTION
[ Read Interrupted by Read ]
Burst read operation can be interrupted by new read of any bank. Random column access
is allowed. READ to READ interval is minimum 1 CLK.
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of any bank. Random column access is
allowed. In this case, the DQ should be controlled adequately by using the DQM to prevent
the bus contention. The output is disabled automatically 1 cycle after WRITE assertion.
Read Interrupted by Read (BL=4, CL=3)
CLK
Command
A0-9
A10
BA0,1
DQ
Yi
Qai0
Qaj1 Qbk0 Qbk1
Qaj0
Qbk2
Qal0
Qal1
Qal2
Qal3
READ READ
READ
READ
Yj
Yk
Yl
0
0
0
0
00
10
00
01
A11
DQM control
Write control
Read Interrupted by Write (BL=4, CL=3)
CLK
Command
A0-9
A10
BA0,1
Q
READ
Yi
0
00
Qai0
Write
Yj
0
00
D
Daj0
Daj1
Daj2
Daj3
DQM(x4,x8)
DQMU/L(x16)
A11
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PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
21
[ Read Interrupted by Precharge ]
Burst read operation can be interrupted by precharge of
the same bank . READ to PRE
interval is mini-mum 1 CLK. A PRE command to output disable latency is equivalent to
the /CAS Latency. As a result, READ to PRE interval determines valid data length to be
output. The figure below shows examples of BL=4.
Read Interrupted by Precharge (BL=4)
CLK
CL=3
Command
DQ
READ
PRE
Q0
Q1
Q2
Command
DQ
READ
PRE
Q0
CL=2
Command
DQ
READ
PRE
Q0
Q1
Q2
Command
DQ
READ
PRE
Q0
Command
DQ
READ PRE
Q0
Q1
Command
DQ
READ PRE
Q0
Q1
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PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
22
[ Read Interrupted by Burst Terminate ]
Similar to a precharge, the burst terminate command, TBST, can interrupt the burst
read operation and disable the data output. The READ to TBST interval is a minimum
of one CLK. TBST is mainly used to interrupt FP bursts. The figures below show
examples, of how the output data is terminated with TBST.
Read Interrupted by Burst Terminate(BL=4)
CLK
Command
READ
TBST
DQ
Q0
Q1
Q2
Command
READ
TBST
DQ
Q0
Q1
Q2
Q3
Command
READ
TBST
DQ
Q0
Command
READ
TBST
DQ
Q0
Q1
Q2
Command
READ
TBST
DQ
Q0
Q1
Q2
Q3
Command
READ
TBST
DQ
Q0
CL=3
CL=2
MITSUBISHI ELECTRIC
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PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
23
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of any bank. Random column access
is allowed. WRITE to WRITE interval is minimum 1 CLK.
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of the same or the other bank. Random
column access is allowed. WRITE to READ interval is minimum 1 CLK. The input data on
DQ at the interrupting READ cycle is "don't care".
Write Interrupted by Write (BL=4)
CLK
Command
A0-9
A10
BA0,1
DQ
Write
Yi
0
00
Write
Yk
0
10
Dai0
Daj0
Daj1
Dbk0
Write
Yj
0
00
Dbk1 Dbk2
Write
Yl
0
00
Dal0
Dal1
Dal2
Dal3
A11
Write Interrupted by Read (BL=4, CL=3)
CLK
Command
A0-9
A10
BA0,1
DQ
Write
Yi
0
00
Qaj0
READ
Yj
0
00
Qaj1
Dai0
Dbk0 Dbk1
Write
Yk
0
10
READ
Yl
0
00
Qal0
A11
DQM(x4,x8)
DQMU/L(x16)
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PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
24
[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of
the same bank. Random
column access is allowed. Write recovery time (tWR) is required from the last data to
PRE command.
Write Interrupted by Precharge (BL=4)
CLK
Command
A0-9
A10
BA0,1
DQ
Write
Yi
0
00
PRE
0
00
ACT
Xb
Xb
00
tWR
tRP
A11
Xb
Dai0
Dai1
Dai2
[ Write Interrupted by Burst Terminate ]
A burst terminate command TBST can be used to terminate a burst write operation. In this
case, the write recovery time is not required and the bank remains active (Please see the
waveforms below). The WRITE to TBST minimum interval is one CLK.
Write Interrupted by Burst Terminate(BL=4)
CLK
Command
A0-9
A10
BA
DQ
WRITE
Yi
0
0
Dai0
DQM(x4,x8)
DQMU/L(x16)
TBST
Dai1
Dai2
DQM(x4,x8)
DQMU/L(x16)
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
25
AUTO REFRESH
Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /CAS= L, /WE= /CKE= H)
command. The refresh address is generated internally. 4096 REFA cycles within 64ms
refresh 64Mbit memory cells. The auto-refresh is performed on 4 banks concurrently. Before
performing an auto-refresh, all banks must be in the idle state. Auto-refresh to auto-refresh
interval is minimum tRC. Any command must not be supplied to the device before tRC from
the REFA command.
Auto-Refresh
CLK
/CS
/RAS
/CAS
/WE
CKE
A0-11
BA0,1
Auto Refresh on All Banks
minimum tRC
NOP or DESELECT
Auto Refresh on All Banks
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
26
SELF REFRESH
Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H,
CKE= L). Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During
the self-refresh mode, CKE is asynchronous and the only enabled input ,all other inputs
including CLK are disabled and ignored, so that power consumption due to synchronous
inputs is saved. To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP
command and then asserting CKE (REFSX) for longer than tSRX. After tRC from REFSX all
banks are in the idle state and a new command can be issued, but DESEL or NOP
commands must be asserted till then.
Self-Refresh
CLK
/CS
/RAS
/CAS
/WE
CKE
A0-11
BA0,1
Self Refresh Entry
Self Refresh Exit
X
00
Stable CLK
NOP
new command
tSRX
minimum tRC
+1 CLOCK
for recovery
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
27
CLK SUSPEND
CKE controls the internal CLK at the following cycle. Figure below shows how CKE works.
By negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power
down, output suspend or input suspend. CKE is a synchronous input except during the self-
refresh mode. CLK suspend can be performed either when the banks are active or idle. A
command at the suspended cycle is ignored.
Power Down by CKE
CLK
Command
PRE
CKE
Command
CKE
ACT
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Standby Power Down
Active Power Down
NOP
NOP
ext.CLK
CKE
int.CLK
DQ Suspend by CKE
CLK
Command
DQ
Write
D0
CKE
READ
Q0
Q1
Q2
Q3
D1
D2
D3
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
28
DQM CONTROL
For x16, DQMU/L are dual function signals defined as the data mask for writes and the
output disable for reads. During writes, DQMU/L mask input data word by word. DQMU/L to
write mask latency is 0. During reads, DQMU/L force outputs to Hi-Z word by word. DQMU/L
to output Hi-Z latency is 2. DQML and DQMU control lower byte (DQ0-7), and upper byte
(DQ8-15), respectively.
DQM Function
CLK
Command
DQ0-7
Write
D0
D2
D3
DQML
READ
Q0
Q1
Q3
masked by DQML=H
disabled by DQMU=H
DQ8-15
D0
D2
D3
Q0
Q1
Q3
DQMU
D1
Q2
For x4/x8, DQM is a dual function signal defined as the data mask for writes and the
output disable for reads. During writes, DQM masks input data word by word. DQM to write
mask latency is 0. During reads, DQM forces output to Hi-Z word by word. DQM to output
Hi-Z latency is 2.
DQM Function
CLK
Command
DQ
Write
D0
D2
D3
DQM
READ
Q0
Q1
Q3
masked by DQM=H
disabled by DQM=H
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
29
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
CAPACITANCE
NOTES)
1. VIH(max)= Vdd+2.0V AC for pulse width less than 3ns acceptable.
2. VIL(min) = -2.0V AC for pulse width less than 3ns acceptable.
Symbol
Parameter
Limits
Unit
Min.
Typ.
Max.
Vdd
Supply Voltage
3.0
3.3
3.6
V
Vss
Supply Voltage
0
0
0
V
VddQ
Supply Voltage for Output
3.0
3.3
3.6
V
VssQ
Supply Voltage for Output
0
0
0
V
VIH*1
High-level Input Voltage all inputs
2.0
VddQ +0.3
V
VIL*2
Low-level Input Voltage all inputs
-0.3
0.8
V
Symbol
Parameter
Conditions
Ratings
Unit
Vdd
Supply Voltage
with respect to Vss
-0.5 - 4.6
V
VddQ
Supply Voltage for Output
-0.5 - 4.6
V
VI
Input Voltage
-0.5 - 4.6
V
VO
Output Voltage
-0.5 - 4.6
V
IO
Output Current
50
mA
Pd
Power Dissipation
Ta = 25C
1000
mW
Topr
Operating Temperature
0 - 70
Tstg
Storage Temperature
-65 - 150
C
with respect to VssQ
with respect to Vss
with respect to VssQ
C
Symbol
Parameter
Test Condition
Limits (max.)
Unit
CI(A)
Input Capacitance, address pin
3.8
pF
CI(C)
Input Capacitance, contorl pin
1MHz,
1.4v bias
200mV swing
3.8
pF
CI(K)
Input Capacitance, CLK pin
3.5
pF
CI/O
Input Capacitance, I/O pin
6.5
pF
(Ta=0 70C, unless otherwise noted )
Limits (min.)
2.5
2.5
2.5
4.0
(Ta=0 70C, Vdd= VddQ= 3.3 0.3V, Vss= VssQ= 0V, unless otherwise noted )
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
30
AVERAGE SUPPLY CURRENT from Vdd
AC OPERATING CONDITIONS AND CHARACTERISTICS
NOTE)
1. Icc(max) is specified at the output open condition.
2.Input signal are changed one time during 30ns
Symbol
Parameter
Test Conditions
Limits
unit
Min.
Max.
VOH (DC)
High-Level Output Voltage (DC)
IOH=-2mA
2.4
V
VOL (DC)
Low-level Output Voltage (DC)
IOL= 2mA
0.4
V
IOZ
Off-state Output Current
Q floating VO=0 -- VddQ
-10
10
A
Input Current
VIH = 0 -- VddQ +0.3V
-10
10
A
I
I
(Ta=0 70C, Vdd= VddQ= 3.3 0.3V, Vss= VssQ= 0V, unless otherwise noted )
(Ta=0 70C, Vdd= VddQ= 3.3 0.3V, Vss= VssQ= 0V, unless otherwise noted )
Symbol
ITEM
Limits (max.)
Unit
Icc1
operating current
mA
Icc2N
tCLK = 15ns
CKE = VIHmin
Icc2P
mA
Icc4
All Bank Active,tCLK = min
BL=4, CL=3,I
OL
=0mA
Organi-
zation
Note
x4/x8
single bank operation
*1
tCLK = 15ns
CKE = VILmax
*1,2
*1,2
*1,2
*1
mA
mA
mA
-6
145
120
25
2
tRC=min, tCLK =min,
BL=1 , CL=3,IOL=0mA
precharge standby
current in Non Power
down mode
active standby current
in Non Power Down
Mode
burst current
Icc5
tRFC=min, tCLK=min
*1
mA
auto-refresh current
Icc2NS
CLK = VILmax
CKE = VIHmin
*1
mA
20
Icc2PS
CLK = CKE =VILmax(fixed)
*1
mA
1
Icc6
self-refresh current
*1
mA
1
CKE < 0.2V
150
Icc3NS
40
Icc3N
CKE = /CS=VIHmin,
tCLK=15ns
55
precharge standby
current in Power down
mode
x4/x8/x16
x4/x8/x16
x4/x8/x16
x4/x8/x16
x4/x8/x16
x4/x8/x16
x4/x8
x4/x8/x16
x4/x8/x16
(fixed)
mA
*1
active standby current
in Power Down Mode
CKE = /CS=VIHmin,
CLK=VILmax (fixed)
Icc3P
tCLK = 15ns
CKE = VILmax
*1,2
mA
2
Icc3PS
CLK = CKE =VILmax(fixed)
*1
mA
1
x4/x8/x16
x4/x8/x16
x16
130
160
x16
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
31
AC TIMING REQUIREMENTS
Any AC timing is referenced
to the input signal passing
through 1.4V.
(Ta=0 70C, Vdd= VddQ= 3.3 0.3V, Vss= VssQ= 0V, unless otherwise noted )
Input Pulse Levels:
0.8V 2.0V
Input Timing Measurement Level:
1.4V
CLK
DQ
1.4V
1.4V
Symbol
Parameter
Limits
Unit
tCLK
CLK cycle time
CL=3
ns
CL=2
ns
tCH
CLK High pulse width
ns
tCL
CLK Low pulse width
ns
tT
Transition time of CLK
ns
tIS
Input Setup time
(all inputs)
ns
tIH
Input Hold time
(all inputs)
ns
tRC
Row Cycle time
ns
tRCD
Row to Column Delay
ns
tRAS
Row Active time
ns
tRP
Row Precharge time
ns
tWR
Write Recovery time
ns
tRRD
Act to Act Delay time
ns
tRSC
Mode Register Set Cycle time
ns
tSRX
Self-refresh Exit time
ns
tREF
Refresh Interval time
ms
tPDE
Power Down Exit time
ns
Min.
Max.
7.5
2.5
1
10
1.5
0.8
67.5
20
45
100K
20
15
15
15
7.5
64
7.5
-6
10
2.5
tRFC
Row Refresh Cycle time
ns
75
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
32
SWITCHING CHARACTERISTICS
Output Load Condition
(Ta=0 70C, Vdd= VddQ= 3.3 0.3V, Vss= VssQ= 0V, unless otherwise noted )
NOTE)
1. If clock rising time is longer than 1ns, (tr /20.5ns) should be added to the parameter.
V
OUT
Ext.CL=50pF
Output Timing Measurement
Reference Point
CLK
1.4V
1.4V
DQ
Symbol
Parameter
Limits
Unit
tAC
Access time from CLK
CL=3
ns
CL=2
ns
tOH
Output Hold time from CLK
ns
tOLZ
Delay time, output low-
impedance from CLK
ns
tOHZ
Delay time, output high-
impedance from CLK
2.7
ns
Note
*1
-6
Min.
Max.
5.4
2.7
0
5.4
6.0
tOHZ
tAC
CLK
DQ
1.4V
1.4V
tOH
tOLZ
CL=3
CL=2
3.0
ns
A
0-9 *
A
10
DQM(U/L)
A
11
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
33
Burst Write (single bank) @BL=4
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
X
X
X
0
Y
0
0
D0
D0
D0
D0
X
X
X
0
Y
0
D0
D0
D0
D0
ACT#0
WRITE#0
PRE#0
ACT#0
WRITE#0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
tRCD
tWR
tRP
tRC
tRCD
CLK
Italic parameter indicates minimum case
tRAS
A
0-9 *
A
10
DQM(U/L)
A
11
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
34
Burst Write (multi bank) @BL=4
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
X
X
X
0
Y
0
1
D0
D0
D0
D0
X
X
0
Y
0
D0
D0
D0
D0
ACT#0
WRITE#0
PRE#0
ACT#0
WRITE#0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
tRCD
tRAS
tWR
tRP
tRC
tRCD
D1
D1
D1
D1
X
X
X
1
tRRD
Y
tWR
0
X
1
X
X
X
2
tRRD
ACT#1
WRITE#1
PRE#1
ACT#2
CLK
Italic parameter indicates minimum case
A
0-9 *
A
10
DQM(U/L)
A
11
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
35
Burst Read (single bank) @BL=4 CL=3
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
X
X
X
0
Y
0
0
Q0
Q0
Q0
Q0
X
X
X
0
Y
0
Q0
Q0
ACT#0
READ#0
PRE#0
ACT#0
READ#0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
tRCD
tRAS
tRP
tRC
tRCD
CL=3
READ to PRE BL allows full data out
DQM read latency =2
CLK
Italic parameter indicates minimum case
A
0-9 *
A
10
DQM(U/L)
A
11
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
36
Burst Read (multiple bank) @BL=4 CL=3
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
X
X
X
0
Y
0
0
Q0
Q0
Q0
Q0
X
X
X
0
Y
0
Q0
ACT#0
READ#0
PRE#0
ACT#0
READ#0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
tRCD
tRAS
tRP
tRC
tRCD
CL=3
DQM read latency =2
tRRD
X
X
X
1
ACT#1
Y
1
tRRD
Q1
Q1
Q1
Q1
X
X
X
2
1
CL=3
READ#1
PRE#1
ACT#2
CLK
Italic parameter indicates minimum case
A
0-9 *
A
10
DQM(U/L)
A
11
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
37
Burst Write (multi bank) with Auto-Precharge @BL=4
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
X
X
X
0
Y
0
1
D0
D0
D0
D0
X
X
0
Y
0
D0
D0
D0
D0
ACT#0
WRITE#0 with
AutoPrecharge
ACT#0
WRITE#0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
tRCD
tRC
tRCD
D1
D1
D1
D1
X
X
X
1
tRRD
Y
X
1
X
X
X
tRRD
ACT#1
WRITE#1 with
AutoPrecharge
BL-1+
tWR + tRP
Y
1
D1
tRCD
ACT#1
WRITE#1
CLK
BL-1+
tWR + tRP
Italic parameter indicates minimum case
A
0-9 *
A
10
DQM(U/L)
A
11
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
38
Burst Read (multiple bank) with Auto-Precharge @BL=4 CL=3
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
X
X
X
0
Y
0
Q0
Q0
Q0
Q0
X
X
X
0
Y
0
Q0
ACT#0
READ#0 with
Auto-Precharge
ACT#0
READ#0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
tRCD
tRC
tRCD
CL=3
DQM read latency =2
tRRD
X
X
X
1
ACT#1
Y
1
tRRD
Q1
Q1
Q1
Q1
CL=3
READ#1 with
Auto-Precharge
ACT#1
BL+
tRP
BL+
tRP
X
X
X
1
Y
1
CLK
Q0
CL=3
tRCD
Italic parameter indicates minimum case
A
0-9 *
A
10
DQM(U/L)
A
11
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
39
Page Mode Burst Write (multi bank) @BL=4
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
X
X
X
0
Y
0
0
D0
D0
D0
D0
ACT#0
WRITE#0
WRITE#0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
tRCD
D1
D1
D1
D1
Y
Y
0
WRITE#1
CLK
X
X
X
1
tRRD
1
Y
D0
D0
D0
D0
D0
D0
D0
ACT#1
WRITE#0
Italic parameter indicates minimum case
A
0-9 *
A
10
DQM(U/L)
A
11
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
40
Page Mode Burst Read (multi bank) @BL=4 CL=3
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
X
X
X
0
Y
0
0
Q0
Q0
Q0
ACT#0
READ#0
READ#0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
tRCD
Q1
Q1
Q1
Q1
Y
Y
0
READ#1
CLK
X
X
X
1
tRRD
1
Y
Q0
Q0
Q0
Q0
ACT#1
READ#0
Q0
CL=3
CL=3
CL=3
DQM read latency=2
Italic parameter indicates minimum case
A
0-9 *
A
10
DQM(U/L)
A
11
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
41
Write Interrupted by Write / Read @BL=4
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
X
X
X
0
Y
0
D0
D0
D0
D0
ACT#0
WRITE#0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
tRCD
Q0
WRITE#1
CLK
X
X
X
1
tRRD
1
Y
D0
D0
D1
D1
Q0
Q0
Q0
ACT#1
WRITE#0
Y
Y
0
0
0
Y
tCCD
CL=3
WRITE#0
READ#0
Burst Write can be interrupted by Write or Read of any active bank.
Italic parameter indicates minimum case
A
0-9 *
A
10
DQM(U/L)
A
11
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
42
Read Interrupted by Read / Write @BL=4 CL=3
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
X
X
X
0
Y
0
0
Q0
Q0
Q0
ACT#0
READ#0
WRITE#0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
tRCD
Q0
D0
D0
Y
Y
0
READ#1
CLK
X
X
X
1
tRRD
0
Y
Q0
Q0
Q1
Q1
ACT#1
READ#0
Q0
DQM read latency=2
0
Y
1
Y
Burst Read can be interrupted by Read or Write of any active bank.
READ#0
READ#0
blank to prevent bus contention
Italic parameter indicates minimum case
A
0-9 *
A
10
DQM(U/L)
A
11
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
43
Write Interrupted by Precharge @BL=4
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
X
X
X
0
Y
0
D0
D0
D0
D0
ACT#0
WRITE#0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
tRCD
WRITE#1
CLK
X
X
X
1
tRRD
1
D1
D1
D1
D1
D1
ACT#1
Y
1
1
Y
Burst Write is not interrupted
by Precharge of the other bank.
0
X
X
X
1
PRE#1
PRE#0
ACT#1
WRITE#1
Burst Write is interrupted by
Precharge of the same bank.
Italic parameter indicates minimum case
A
0-9 *
A
10
DQM(U/L)
A
11
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
44
Read Interrupted by Precharge @BL=4 CL=3
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
X
X
X
0
Y
0
Q0
Q0
Q0
ACT#0
READ#0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
tRCD
Y
1
PRE#1
CLK
X
X
X
1
tRRD
Q1
Q1
ACT#1
PRE#0
Q0
DQM read latency=2
1
Y
1
Burst Read is not interrupted
by Precharge of the other bank.
0
X
X
X
1
tRCD
tRP
READ#1
ACT#1
READ#1
Burst Read is interrupted
by Precharge of the same bank.
Italic parameter indicates minimum case
A
0-9 *
A
10
DQM(U/L)
A
11
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
45
Mode Register Setting
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
Auto-Ref (last of 8 cycles)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Y
0
CLK
tRC
D0
Mode
Register
Setting
M
0
X
X
X
0
tRCD
tRSC
ACT#0
WRITE#0
D0
D0
D0
Italic parameter indicates minimum case
A
0-9 *
A
10
DQM(U/L)
A
11
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
46
Auto-Refresh @BL=4
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
Auto-Refresh
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
Before Auto-Refresh,
all banks must be idle state.
Y
0
D0
X
X
X
0
tRCD
ACT#0
WRITE#0
D0
D0
D0
After tRC from Auto-Refresh,
all banks are idle state.
Italic parameter indicates minimum case
A
0-9 *
A
10
DQM(U/L)
A
11
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
47
Self-Refresh
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
Self-Refresh Entry
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
Before Self-Refresh Entry,
all banks must be idle state.
X
X
X
0
Self-Refresh Exit
ACT#0
After tRC from Self-Refresh Exit,
all banks are idle state.
tRC+1
tSRX
CLK can be stopped
CKE must be low to maintain Self-Refresh
Italic parameter indicates minimum case
A
0-9 *
A
10
DQM(U/L)
A
11
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
48
DQM Write Mask @BL=4
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
X
X
X
0
Y
0
0
D0
D0
D0
D0
Y
0
D0
D0
D0
ACT#0
WRITE#0
WRITE#0
WRITE#0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
tRCD
CLK
Y
masked
masked
Italic parameter indicates minimum case
A
0-9 *
A
10
DQM(U/L)
A
11
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
49
DQM Read Mask @BL=4 CL=3
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
X
X
X
0
Y
0
0
Q0
Q0
Q0
Q0
Y
0
Q0
Q0
Q0
ACT#0
READ#0
READ#0
READ#0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
tRCD
CLK
Y
masked
masked
DQM read latency=2
Italic parameter indicates minimum case
A
0-9 *
A
10
DQM(U/L)
A
11
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
50
Power Down
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
0
Precharge All
ACT#0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
X
X
X
Standby Power Down
Active Power Down
CKE latency=1
Italic parameter indicates minimum case
A
0-9 *
A
10
DQM(U/L)
A
11
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
51
CLK Suspend @BL=4 CL=3
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
X
X
X
0
Y
0
0
Q0
Q0
Q0
Q0
ACT#0
WRITE#0
READ#0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
tRCD
CLK
Y
D0
D0
D0
D0
CLK suspended
CLK suspended
CKE latency=1
CKE latency=1
Italic parameter indicates minimum case
A
0-9 *
A
10
DQM(U/L)
A
11
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
Oct. '99
MITSUBISHI LSIs
PC133 SDRAM (Rev.0.5)
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
52
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products
better and more reliable,but there is always the possibility that trouble may occur with them.
Trouble with semiconductors consideration to safety when making your circuit designs,with
appropriate measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of
non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.These materials are intended as a reference to assist our customers in the selection of the
Mitsubishi semiconductor product best suited to the customer's application;they do not convey any
license under any intellectual property rights,or any other rights,belonging to Mitsubishi
Electric Corporation or a third party.
2.Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any
third-party's rights,originating in the use of any product data,diagrams,charts or circuit application
examples contained in these materials.
3.All information contained in these materials,including product data, diagrams and
charts,represent information on products at the time of publication of these materials,and are
subject to change by Mitsubishi Electric Corporation without notice due to product improvements
or other reasons. It is therefore recommended that customers contact Mitsubishi Electric
Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product
information before purchasing a product listed herein.
4.Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a
device or system that is used under circumstances in which human life is potentially at stake.
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor when considering the use of a product contained herein for special applications,such as
apparatus or systems for transportation, vehicular, medical,aerospace,nuclear,or undersea repeater
use.
5.The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce
in whole or in part these materials.
6.If these products or technologies are subject the Japanese export control restrictions,they must
be exported under a license from the Japanese government and cannot be imported into a
country other than the approved destination. Any diversion or reexport contrary to the export
control laws and regulations of Japan and/or the country of destination is prohibited.
7.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for further details on these materials or the products contained therein.
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