DESCRIPTION
The M35047-XXXSP/FP is a character pattern display control IC
can display on the CRT display the liquid crystal display and the
plasma display. It uses a silicon gate CMOS process and it
housed in a 20-pin shrink DIP package (M35047-XXXSP) or a 20-
pin shrink SOP package (M35047-XXXFP).
For M35047-002SP/FP that is a standard ROM version of
M35047-XXXSP/FP respectively, the character pattern is also
mentioned.
FEATURES
Screen composition ................................ 24 characters
!
12 lines
Number of characters displayed ................................... 288 (Max.)
Character composition ..................................... 12
!
18 dot matrix
Characters available ..................... ROM character:255 characters
RAM character:8 characters
Character sizes available .................... 4 (vertical)
!
4 (horizontal)
Display locations available
Horizontal direction .............................................. 2007 locations
Vertical direction .................................................. 2047 locations
Blinking .................................................................. Character units
Cycle : division of vertical synchronization signal into 32 or 64
Duty
: 25%, 50%, or 75%
Data input ............................. By the I
2
C-BUS serial input function
Coloring for ROM character
Character color ..................................... 8 colors (Character unit)
Background coloring ............................. 8 colors (Character unit)
Border (shadow) coloring ..................... 8 colors (unit of screen /
character unit)
Raster coloring.......................................8 colors (unit of screen)
Blanking for ROM character
Character size blanking
Border size blanking
Matrix-outline blanking
All blanking (all raster area)
Coloring for RAM character................................8 colors (dot by dot)
Blanking for RAM character
Character size blanking
Matrix-outline blanking
All blanking (all raster area)
Output ports
4 shared output ports (toggled between RGB output)
4 dedicated output ports
Display RAM erase function
Display input frequency range ....... F
OSC
= 20.0MHz to 100.0MHz
Horizontal synchronous input frequency
........................................................ H.sync = 15 kHz to 130 kHz
Display oscillation stop function
APPLICATION
CRT display, Liquid crystal display, Plasma display
Outline 20P4B
PIN CONFIGURATION (TOP VIEW)
Outline 20P2Q-A
MITSUBISHI MICROCOMPUTERS
M35047-XXXSP/FP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
Rev.1.1
CPOUT
V
SS2
AC
TEST
SCL
SDA
TCK
VDD1
P6
P7
1
2
3
4
5
6
7
8
9
10
M35047-XXXSP
11
12
13
14
15
16
17
18
19
20
V
DD2
VERT
HOR
P5/B
P4
P3/G
P2
P1/R
P0/BLNK0
V
SS1
M35047-XXXFP
CPOUT
V
SS2
AC
TEST
SCL
SDA
TCK
VDD1
P6
P7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
V
DD2
VERT
HOR
P5/B
P4
P3/G
P2
P1/R
P0/BLNK0
V
SS1
MITSUBISHI MICROCOMPUTERS
M35047-XXXSP/FP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
2
Symbol
CPOUT
V
SS2
__
AC
TEST
SCL
SDA
TCK
V
DD1
P6
P7
V
SS1
P0/BLNK0
P1/R
P2
P3/G
P4
P5/B
HOR
VERT
V
DD2
Input/
Output
Output
Input
Input
Input
I/O
Input
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Function
Filter output. Connect loop filter to this pin.
Connect to GND.
When "L", this pin resets the internal IC circuit. Hysteresis input. Built-in pull-up resistor.
Test pin. Connect to +5V.
SDA pin serial data is taken in when SCL rises. Hysteresis input.
This is the pin for serial input of display control register and display RAM data. Also, this
pin output acknowledge signal. Hysteresis input. Nch opendrain output.
This is the pin for external clock input.
Please connect to +5V with the power pin.
This is the output port.
This is the output port.
Please connect to GND using circuit earthing pin.
This pin can be toggled between port pin output and BLNK0 signal output.
This pin can be toggled between port pin output and R signal output.
This is the output port.
This pin can be toggled between port pin output and G signal output.
This is the output port.
This pin can be toggled between port pin output and B signal output.
This pin inputs the horizontal synchronous signal. Hysteresis input.
This pin inputs the vertical synchronous signal. Hysteresis input.
Please connect to +5V with the power pin.
Pin name
Filter output
Earthing pin
Auto-clear input
Test input
Clock input
Data I/O
External clock
Power pin
Port P6 output
Port P7 output
Earthing pin
Port P0 output
Port P1 output
Port P2 output
Port P3 output
Port P4 output
Port P5 output
Horizontal synchro-
nous signal input
Vertical synchro-
nous signal input
Power pin
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIN DESCRIPTION
MITSUBISHI MICROCOMPUTERS
M35047-XXXSP/FP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
3
BLOCK DIAGRAM
5
7
6
8
20
4
SCL
SD
A
V
DD1
V
DD2
3
AC
11
V
SS1
2
V
SS2
TEST
Cloc
k oscillation
circuit displa
y
Timing gener
ator
P
olar
ity s
witching circuit
Address control
circuit
Data control
circuit
Displa
y control
register
Displa
y RAM
Shift register
Blinking circuit
Reading address
control circuit
Displa
y location
detection circuit
H counter
TCK
1
CPOUT
18
HOR
19
12
VER
T
Synchronous signal
s
witching circuit
Displa
y control
circuit
P
o
r
t
output
control circuit
P0/BLNK0
13
P1/R
15
P3/G
17
P5/B
14
P2
16
P4
9P
6
10
P7
Input control circuit
Polarity switching circuit
Displa
y char
acter
RAM
Displa
y char
acter
R
OM
MITSUBISHI MICROCOMPUTERS
M35047-XXXSP/FP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
4
DAF
DAE
DAD
DAC
DAB
DAA
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
0
BB
BG
BR
BLINK
B
G
R
C7
C6
C5
C4
C3
C2
C1
C0
0
BB
BG
BR
BLINK
B
G
R
C7
C6
C5
C4
C3
C2
C1
C0
0
BB
BG
BR
BLINK
B
G
R
C7
C6
C5
C4
C3
C2
C1
C0
0
BB
BG
BR
BLINK
B
G
R
C7
C6
C5
C4
C3
C2
C1
C0
0
SPACE2 SPACE1 SPACE0 TEST10 DIV10
DIV9
DIV8
DIV7
DIV6
DIV5
DIV4
DIV3
DIV2
DIV1
DIV0
0
EXCK1 EXCK0 RSEL1 RSEL0
DIVS2
DIVS1
DIVS0
PTC7
PTC6
PTC5
PTC4
PTC3
PTC2
PTC1
PTC0
0
TEST17 TEST16 TEST15 TEST14 TEST13 TEST12 TEST11
PTD7
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
0
TEST3
TEST2
TEST1
TEST0
HP10
HP9
HP8
HP7
HP6
HP5
HP4
HP3
HP2
HP1
HP0
0
TEST20
RBLK0
TEST19 TEST18
VP10
VP9
VP8
VP7
VP6
VP5
VP4
VP3
VP2
VP1
VP0
0
TEST23 TEST22 TEST21 DSP11 DSP10
DSP9
DSP8
DSP7
DSP6
DSP5
DSP4
DSP3
DSP2
DSP1
DSP0
0
TEST24 VSZ1H1 VSZ1H0 VSZ1L1 VSZ1L0 V1SZ1
V1SZ0
LIN9
LIN8
LIN7
LIN6
LIN5
LIN4
LIN3
LIN2
0
TEST25 VSZ2H1 VSZ2H0 VSZ2L1 VSZ2L0 V18SZ1 V18SZ0 LIN17
LIN16
LIN15
LIN14
LIN13
LIN12
LIN11
LIN10
0
TEST29 HSZ21
HSZ20
HSZ11
HSZ10 BETA14 TEST28 TEST27 TEST26
FB
FG
FR
RB
RG
RR
0
TEST30
BLINK2 BLINK1 BLINK0
DSPON
STOP
RAMERS
SYAD
BLK1
BLK0
POLH
POLV VMASK
B/F
BCOL
MEMORY CONSTITUTION
Address 000
16
to 11F
16
are assigned to the display RAM, address
120
16
to 129
16
are assigned to the display control registers and
address 200
16
to 2F1
16
are assigned to the RAM characters. The
internal circuit is reset and all display control registers (address
120
16
to 129
16
) are set to "0" when the AC pin level is "L". And
then, RAM is not erased and be undefinited. For detail, see "DATA
INPUT EXAMPLE". Memory constitution is shown in Figure 1 to 9.
Fig.1 Memory constitution (Display RAM, Display Control register)
.........
.........
Addresses
Background
coloring
Blink-
ing
Character color
Character code
000
16
001
16
11E
16
11F
16
120
16
121
16
122
16
123
16
124
16
125
16
126
16
127
16
128
16
129
16
MITSUBISHI MICROCOMPUTERS
M35047-XXXSP/FP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
5
DAF
DAE
DAD
DAC
DAB
DAA
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
0
BS
GS
RS
FR000B FR000A FR0009 FR0008 FR0007 FR0009 FR0005 FR0004 FR0003 FR0002 FR0001 FR0000
0
BS
GS
RS
FR001B FR001A FR0019 FR0018 FR0017 FR0019 FR0015 FR0014 FR0013 FR0012 FR0011 FR0010
0
BS
GS
RS
FR002B FR002A FR0029 FR0028 FR0027 FR0026 FR0025 FR0024 FR0023 FR0022 FR0021 FR0020
0
BS
GS
RS
FR003B FR003A FR0039 FR0038 FR0037 FR0036 FR0035 FR0034 FR0033 FR0032 FR0031 FR0030
0
BS
GS
RS
FR004B FR004A FR0049 FR0048 FR0047 FR0046 FR0045 FR0044 FR0043 FR0042 FR0041 FR0040
0
BS
GS
RS
FR005B FR005A FR0059 FR0058 FR0057 FR0056 FR0055 FR0054 FR0053 FR0052 FR0051 FR0050
0
BS
GS
RS
FR006B FR006A FR0069 FR0068 FR0067 FR0066 FR0065 FR0064 FR0063 FR0062 FR0061 FR0060
0
BS
GS
RS
FR007B FR007A FR0079 FR0078 FR0077 FR0076 FR0075 FR0074 FR0073 FR0072 FR0071 FR0070
0
BS
GS
RS
FR008B FR008A FR0089 FR0088 FR0087 FR0086 FR0085 FR0084 FR0083 FR0082 FR0081 FR0080
0
BS
GS
RS
FR009B FR009A FR0099 FR0098 FR0097 FR0096 FR0095 FR0094 FR0093 FR0092 FR0091 FR0090
0
BS
GS
RS
FR00AB FR00AA FR00A9 FR00A8 FR00A7 FR00A6 FR00A5 FR00A4 FR00A3 FR00A2 FR00A1 FR00A0
0
BS
GS
RS
FR00BB FR00BA FR00B9 FR00B8 FR00B7 FR00B6 FR00B5 FR00B4 FR00B3 FR00B2 FR00B1 FR00B0
0
BS
GS
RS
FR00CB FR00CA FR00C9 FR00C8 FR00C7 FR00C6 FR00C5 FR00C4 FR00C3 FR00C2 FR00C1 FR00C0
0
BS
GS
RS
FR00DB FR00DA FR00D9 FR00D8 FR00D7 FR00D6 FR00D5 FR00D4 FR00D3 FR00D2 FR00D1 FR00D0
0
BS
GS
RS
FR00EB FR00EA FR00E9 FR00E8 FR00E7 FR00E6 FR00E5 FR00E4 FR00E3 FR00E2 FR00E1 FR00E0
0
BS
GS
RS
FR00FB FR00FA FR00F9 FR00F8 FR00F7 FR00F6 FR00F5 FR00F4 FR00F3 FR00F2 FR00F1 FR00F0
0
BS
GS
RS
FR010B FR010A FR0109 FR0108 FR0107 FR0106 FR0105 FR0104 FR0103 FR0102 FR0101 FR0100
0
BS
GS
RS
FR011B FR011A FR0119 FR0118 FR0117 FR0116 FR0115 FR0114 FR0113 FR0112 FR0111 FR0110
200
16
201
16
202
16
203
16
204
16
205
16
206
16
207
16
208
16
209
16
20A
16
20B
16
20C
16
20D
16
20E
16
20F
16
210
16
211
16
212
16
21F
16
Address
DAF
DAE
DAD
DAC
DAB
DAA
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
0
BS
GS
RS
FR100B FR100A FR1009 FR1008 FR1007 FR1006 FR1005 FR1004 FR1003 FR1002 FR1001 FR1000
0
BS
GS
RS
FR111B FR111A FR1119 FR1118 FR1117 FR1116 FR1115 FR1114 FR1113 FR1112 FR1111 FR1110
220
16
221
16
230
16
231
16
232
16
23F
16
RAM character 1 data
Fig.2 Memory constitution (RAM character 0)
Fig.3 Memory constitution (RAM character 1)
Can not be used
Address
........
........
........
Can not be used
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