PIN CONFIGURATION (TOP VIEW)
MITSUBISHI MICROCOMPUTERS
M35060-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
DESCRIPTION
M35060-XXXSP is CATV screen display control IC which can dis-
play 40 (horizontal)
!
16 (vertical). It has built-in SYRAM which can
be used with character ROM.
It uses a silicon gate CMOS process and it housed in a small 32-pin
shrink DIP package. For M35060-001SP and M35060-002SP that
are standard ROM versions of M35060-XXXSP, the character pat-
terns are also mentioned.
FEATURES
Screen composition ................................ 40 characters
!
16 lines
Number of characters displayed ................................... 680 (Max.)
Character composition ..................................... 12
!
13 dot matrix
Characters available
character ROM ................ 256 characters
SYRAM .............................. 63 characters
Character sizes available horizontal ..................... 2 (once, twice)
vertical ......................... 2 (once, twice)
setting by every line
Display locations available
Horizontal direction ................................................ 480 locations
Vertical direction .................................................... 235 locations
Blinking ................................................................... character units
Cycle .... approximately 1 second, or approximately 0.5 seconds
Duty ............................................................... 25%, 50% or 75%
Data input ............................................................ 8-bit parallel
!
3
Coloring Character coloring ......... 8 colors choices per character
Background coloring ..... 8 colors choices per character
Raster coloring .................. 8 colors choices per screen
Blanking
Character size blanking
Border size blanking
Matrix-outline
Halftone blanking
Can be set by every line
General-purpose output ports
Combined port output ............ 6
(switching to RGB output)
RAM erase ............................. Display RAM erasing by every line
SYRAM erasing separately
Scrolling ............ Bit by bit smooth scroll implemented by software
Composite synchronizating signal generation .................... Built-in
(PAL, NTSC, M-PAL)
Display oscillation circuit .................................................... Built-in
Synchronous separation circuit .......................................... Built-in
Synchronous correction circuit ........................................... Built-in
Outline 32P4B
SCK
TESTA
P5
P4
P3
P2
P1
P0
TESTB
OSCIN
OSCOUT
LP2
V
DD2
LP1
VREF
CS
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
V
DD1
V
SS
CVIDEO
LECHA
LEBK
CVIN
HOR
AC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
M35060-XXXSP
REV.1.1
2
MITSUBISHI MICROCOMPUTERS
M35060-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
PIN DESCRIPTION
These input pins determine address and data of the Display RAM, Control RAM, and
Overlay RAM (SYRAM) by 8-bit parallel. Hysteresis input is required.
When this input pin transitions from "H" to "L", the device is reset. Built-in a pull-up
resistor. Hysteresis input is required.
Digital power supply pin. This pin must be connected to + 5V.
Ground pin. This pin must be connected to 0V.
This pin outputs the composite video signal. The output signal is 2Vp-p. In superim-
pose mode, this pin's signal consists of the OSD signal combined with the input
composite signal CVIN.
This input pin is used for controlling the "white" character color level of the OSD signal.
This input pin is used for controlling the "black" character color level of the OSD signal.
This input pin is used for the superimpose mode. An external composite signal may be
input through this pin and mixed with the internally generated OSD signal.
This input pin is used to input the same signal as CVIN. The horizontal and vertical
sync signals are then extracted internally within the device.
This input pin is used to determine the slice voltage for extracting the sync signals from
the video composite signal.
This is filter output pin 1.
Analog power supply pin. This pin must be connected to +5V.
This is filter output pin 2.
These are the pins for attaching an external oscillator circuit for generating the
synchronization signal:
NTSC (3.580MHz), PAL (4.434MHz), M-PAL (3.576MHz).
Factory test pin. The pin must be connected to GND.
This output pin can be configured to port P0 or YM output.
This output pin can be configured to port P1 or BLNK output.
This output pin can be configured to port P2 or B output.
This output pin can be configured to port P3 or G output.
This output pin can be configured to port P4 or R output.
This output pin can be configured to port P5 or CSYN output.
Factory test pin. The pin must be connected to GND.
This pin is enabled when the CS pin is "L". Data input to pins AD0 to AD7 is latched at
the rising edge of this signal. This pin is hysteresis input.
This is chip selection input pin. When this pin is "L", transmission is enabled. This pin is
hysteresis input.
Function
Symbol
AD0~AD7
AC
V
DD1
V
SS
CVIDEO
LECHA
LEBK
CVIN
HOR
VREF
LP1
V
DD2
LP2
OSCOUT
OSCIN
TESTB
P0
P1
P2
P3
P4
P5
TESTA
SCK
CS
Parallel data input
Auto-clear input
Power pin
Earthing pin
Composite video
signal output
Character level input
Black level input
Composite video
signal input
Synchronous signal
input
Slice level input
Filter output 1
Power pin
Filter output 2
The pins for attaching an exter-
nal oscillator circuit for genera-
ting the synchronization signal.
Test input
Port output
Port output
Port output
Port output
Port output
Port output
Test input
Clock input for data
input
Chip select input
Pin name
Input/Output
Input
Input
--
--
Output
Input
Input
Input
Input
Input
Output
--
Output
Output
Input
Input
Output
Output
Output
Output
Output
Output
Input
Input
Input
MITSUBISHI MICROCOMPUTERS
M35060-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
3
BLOCK DIAGRAM
Write access
control
Read access
control
Display
position
detection
Timing
generator
Sync
separation
Vsync
separation
Synchronous
correction circuit
Quadruple
frequency circuit
Display control register
Display RAM
Character
Pattern ROM
SYRAM
Blinking
Shift
TESTB
CVIN
LEBK
LECHA
CVIDEO
LP1
OSCOUT
OSCIN
LP2
SCK
CS
TESTA
HOR
VREF
P0
/YM
P1
/BLNK
P2
/B
P3
/G
P4
/R
P5
/CSYN
Port output/Selection
Display control
Sync
generation
Video signal
output
NTSC, PAL,
M-PAL
V
DD2
V
SS
AC
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
32
31
30
16
17
18
21
22
20
23
15
14
13
12
29
28
27
26
25
24
9
11
19
8
7
6
5
4
3
2
1
V
DD1
10
Input control circuit
4
MITSUBISHI MICROCOMPUTERS
M35060-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
: Name or value changes by definite ratio.
: The same name or value continues.
MEMORY CONSTRUCTION
Address 000
16
to 2A7
16
are assigned to the display RAM, 2A8
16
to
2B0
16
are assigned to the display control registers and 300
16
to
6EC
16
are assigned to SYRAM.
The internal circuit is reset and all display control registers (address
2A8
16
to 2B0
16
) are set to "0". The memory constitution of display
RAM and register is shown in Figure 1 and the memory constitution
of SYRAM is shown in Figure 2.
add-
ress
000
16
2A7
16
2A8
16
2A9
16
2AA
16
2AB
16
2AC
16
2AD
16
2AE
16
2AF
16
2B0
16
DA17
SB
SB
PC7
DA16
SG
SG
TEST
3
TEST
23
PC6
TEST
19
DA15
SR
SR
TEST
2
TEST
26
TEST
22
PC5
TEST
18
DA14
SYC5
SYC5
TEST
1
BLINK
3
TEST
12
TEST
25
TEST
21
SERS
3
PC4
TEST
17
DA13
SYC4
SYC4
TEST
0
BLINK
2
EQP
PHASE
2
LINE
B
SERS
2
PC3
TEST
24
DA12
SYC3
SYC3
TEST
11
BLINK
1
TEST
20
PHASE
1
LINE
G
SERS
1
SEND
4
PC2
LEVEL
2
DA10
SYC1
SYC1
HP8
HSZ
16
VSZ
16
DSP0
16
DSP1
16
ERS
16
SEND
2
PC0
LEVEL
0
DAF
SYC0
SYC0
HP7
HSZ
15
VSZ
15
DSP0
15
DSP1
15
ERS
15
SEND
1
ALL24
INT
NON
DAE
BB
BB
HP6
HSZ
14
VSZ
14
DSP0
14
DSP1
14
ERS
14
SEND
0
SRAND
2
PAL
NTSC
DAD
BG
BG
HP5
HSZ
13
VSZ
13
DSP0
13
DSP1
13
ERS
13
SST
4
SRAND
1
MPAL
DAC
BR
BR
HP4
HSZ
12
VSZ
12
DSP0
12
DSP1
12
ERS
12
SST
3
SRAND
0
PALH
DAB
BLINK
BLINK
BLINK
HP3
HSZ
11
VSZ
11
DSP0
11
DSP1
11
ERS
11
SST
2
PTD
5
TEST
16
DAA
CB
CB
HP2
HSZ
10
VSZ
10
DSP0
10
DSP1
10
ERS
10
SST
1
PTD
4
TEST
15
DA9
CG
CG
HP1
HSZ
9
VSZ
9
DSP0
09
DSP1
09
ERS
9
SST
0
PTD
3
SEPV1
DA8
CR
CR
HP0
HSZ
8
VSZ
8
DSP0
08
DSP1
08
ERS
8
SLIN
4
PTD
2
SEPV0
DA7
C7
C7
VP7
HSZ
7
VSZ
7
DSP0
07
DSP1
07
ERS
7
SLIN
3
PTD
1
BLK
DA6
C6
C6
VP6
HSZ
6
VSZ
6
DSP0
06
DSP1
06
ERS
6
SLIN
2
PTD
0
DA5
C5
C5
VP5
HSZ
5
VSZ
5
DSP0
05
DSP1
05
ERS
5
SLIN
1
PTC
5
DSP
ONV
DA4
C4
C4
VP4
HSZ
4
VSZ
4
DSP0
04
DSP1
04
ERS
4
SLIN
0
PTC
4
DSP
ON
DA3
C3
C3
VP3
HSZ
3
VSZ
3
DSP0
03
DSP1
03
ERS
3
SBIT
3
PTC
3
DA2
C2
C2
VP2
HSZ
2
VSZ
2
DSP0
02
DSP1
02
ERS
2
SBIT
2
PTC
2
SEL
COR
DA1
C1
C1
VP1
HSZ
1
VSZ
1
DSP0
01
DSP1
01
ERS
1
SBIT
1
PTC
1
DA0
C0
C0
VP0
HSZ
0
VSZ
0
DSP0
00
DSP1
00
ERS
0
SBIT
0
PTC
0
EX
SY color setting
SYRAM setting
DA11
SYC2
SYC2
TEST
10
BLINK
0
HIDE
PHASE
0
LINE
R
SERS
0
SEND
3
PC1
LEVEL
1
Raster color setting
Character color setting
Character setting
~
Table 1 The memory constitution of display RAM and register
Table 2 The memory constitution of SYRAM
add-
ress
300
16
30C
16
310
16
31C
16
6D0
16
6DC
16
6E0
16
6EC
16
0
0
DA17 ~ DAD
0
0
DAC
SYEX
SYEX
SYEX
SYEX
SYEX
SYEX
SYEX
SYEX
DAB
S00B
S00B
S01B
S01B
S3DB
S3DB
S3EB
S3EB
DAA
S00A
S00A
S01A
S01A
S3DA
S3DA
S3EA
S3EA
DA9
S009
S009
S019
S019
S3D9
S3D9
S3E9
S3E9
DA8
S008
S008
S018
S018
S3D8
S3D8
S3E8
S3E8
DA7
S007
S007
S017
S017
S3D7
S3D7
S3E7
S3E7
DA6
S006
S006
S016
S016
S3D6
S3D6
S3E6
S3E6
DA5
S005
S005
S015
S015
S3D5
S3D5
S3E5
S3E5
DA4
S004
S004
S014
S014
S3D4
S3D4
S3E4
S3E4
DA3
S003
S003
S013
S013
S3D3
S3D3
S3E3
S3E3
DA2
S002
S002
S012
S012
S3D2
S3D2
S3E2
S3E2
DA1
S001
S001
S011
S011
S3D1
S3D1
S3E1
S3E1
DA0
S000
S000
S010
S010
S3D0
S3D0
S3E0
S3E0
SYRAM code
00
16
01
16
3D
16
3E
16
...
...
...
......
...
...
......
...
...
......
...
...
......
...
...
......
...
...
......
...
...
......
...
...
......
...
...
......
...
...
......
...
...
......
...
...
......
...
...
......
...
...
......
...
~
~
~
~~
~
~
TEST
n
(n = number) is MITSUBISHI test memory. Set 0 to all bits.
~
...
MITSUBISHI MICROCOMPUTERS
M35060-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
5
SCREEN CONSTITUTION
The screen lines and rows are determined from each address of the display RAM.
The screen constitution is shown in Figure 1.
Fig. 1 Screen constitution
001
002
003
004
005
006
007
008
009
00A
00B
00C
00D
00E
00F
010
011
012
013
014
015
016
017
018
019
01A
01B
01C
01D
01E
01F
020
021
022
023
024
025
026
027
000
079
07A
07B
07C
07D
07E
07F
080
081
082
083
084
085
086
087
088
089
08A
08B
08C
08D
08E
08F
090
091
092
093
094
095
096
097
098
099
09A
09B
09C
09D
09E
09F
078
0A1
0A2
0A3
0A4
0A5
0A6
0A7
0A8
0A9
0AA
0AB
0AC
0AD
0AE
0AF
0B0
0B1
0B2
0B3
0B4
0B5
0B6
0B7
0B8
0B9
0BA
0BB
0BC
0BD
0BE
0BF
0C0
0C1
0C2
0C3
0C4
0C5
0C6
0C7
0A0
0C9
0CA
0CB
0CC
0CD
0CE
0CF
0D0
0D1
0D2
0D3
0D4
0D5
0D6
0D7
0D8
0D9
0DA
0DB
0DC
0DD
0DE
0DF
0E0
0E1
0E2
0E3
0E4
0E5
0E6
0E7
0E8
0E9
0EA
0EB
0EC
0ED
0EE
0EF
0C8
0F1
0F2
0F3
0F4
0F5
0F6
0F7
0F8
0F9
0FA
0FB
0FC
0FD
0FE
0FF
100
101
102
103
104
105
106
107
108
109
10A
10B
10C
10D
10E
10F
110
111
112
113
114
115
116
117
0F0
141
142
143
144
145
146
147
148
149
14A
14B
14C
14D
14E
14F
150
151
152
153
154
155
156
157
158
159
15A
15B
15C
15D
15E
15F
160
161
162
163
164
165
166
167
140
169
16A
16B
16C
16D
16E
16F
170
171
172
173
174
175
176
177
178
179
17A
17B
17C
17D
17E
17F
180
181
182
183
184
185
186
187
188
189
18A
18B
18C
18D
18E
18F
168
1B9
1BA
1BB
1BC
1BD
1BE
1BF
1C0
1C1
1C2
1C3
1C4
1C5
1C6
1C7
1C8
1C9
1CA
1CB
1CC
1CD
1CE
1CF
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1D9
1DA
1DB
1DC
1DD
1DE
1DF
1B8
259
25A
25B
25C
25D
25E
25F
260
261
262
263
264
265
266
267
268
269
26A
26B
26C
26D
26E
26F
270
271
272
273
274
275
276
277
278
279
27A
27B
27C
27D
27E
27F
258
119
11A
11B
11C
11D
11E
11F
120
121
122
123
124
125
126
127
128
129
12A
12B
12C
12D
12E
12F
130
131
132
133
134
135
136
137
138
139
13A
13B
13C
13D
13E
13F
118
191
192
193
194
195
196
197
198
199
19A
19B
19C
19D
19E
19F
1A0
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1A9
1AA
1AB
1AC
1AD
1AE
1AF
1B0
1B1
1B2
1B3
1B4
1B5
1B6
1B7
190
1E1
1E2
1E3
1E4
1E5
1E6
1E7
1E8
1E9
1EA
1EB
1EC
1ED
1EE
1EF
1F0
1F1
1F2
1F3
1F4
1F5
1F6
1F7
1F8
1F9
1FA
1FB
1FC
1FD
1FE
1FF
200
201
202
203
204
205
206
207
1E0
231
232
233
234
235
236
237
238
239
23A
23B
23C
23D
23E
23F
240
241
242
243
244
245
246
247
248
249
24A
24B
24C
24D
24E
24F
250
251
252
253
254
255
256
257
230
281
282
283
284
285
286
287
288
289
28A
28B
28C
28D
28E
28F
290
291
292
293
294
295
296
297
298
299
29A
29B
29C
29D
29E
29F
2A0
2A1
2A2
2A3
2A4
2A5
2A6
2A7
280
051
052
053
054
055
056
057
058
059
05A
05B
05C
05D
05E
05F
060
061
062
063
064
065
066
067
068
069
06A
06B
06C
06D
06E
06F
070
071
072
073
074
075
076
077
050
029
02A
02B
02C
02D
02E
02F
030
031
032
033
034
035
036
037
038
039
03A
03B
03C
03D
03E
03F
040
041
042
043
044
045
046
047
048
049
04A
04B
04C
04D
04E
04F
028
208
209
20A
20B
20C
20D
20E
20F
210
211
212
213
214
215
216
217
218
219
21A
21B
21C
21D
21E
21F
220
221
222
223
224
225
226
227
228
229
22A
22B
22C
22D
22E
22F
The hexadecimal numbers in the boxes show the display RAM address
Line 16
Row
Line 0
Line 1
Line 15
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