Chapter 1
Features
This Audio Decoder for Dolby Digital (AC-3)
*1
M65863FP is a single device. The device decodes AC-3
bitstreams into PCM audio. Dolby Digital (AC-3) is a multi-channel audio coding algorithm developed by
Dolby Laboratories, Inc.
Decoding
1) 5.1 ch AC-3 bitstream
2) Dolby Pro Logic
*1
encoded 2ch Dolby Digital (AC-3) bitstream
3) Dolby Pro Logic encoded 2ch PCM data
All input combinations from 1 to 5.1 channels
Output : mono 5.1 surround
Sampling rates : 32kHz, 44.1 kHz, 48 kHz and 96 kHz (96 kHz is for linear PCM only)
Supports a maximum bit rate of 640 kbps at a full service (up to 448 kbps when 32 kHz sampling rates)
2 DIR (Digital Audio Interface Receiver)/ADC input interfaces
Serial input bitstream interface for DEMUX
PCM output interface
Standard 3-wire DAC output interface (data,clock,LR clock), 16/18/20/24 bit DAC word size
Supports IEC958 digital audio output for Dolby Digital (AC-3) data stream
I
2
C
*2
interface and clocked serial (4 line) interface for host microcontroller
Generates audio test noise
2nd DSP I/F (twice higher PCM transfer rate)
Controllable dynamic range compression
Programmable center and surround channel delays
Dialogue level control
No external memory required (M65863FP doos not have memory space for surround delay)
M65863FP
MCU
I C/Clocked serial
2
DAC
DIR
ADC
IEC958
Analog
IEC958
DSP
Figure 1.1 M65863FP Configuration Diagram (DIR I/F)
*1
Dolby, Dolby Digital (AC-3), and Pro Logic are registered trademarks of Dolby Laboratories Licensing Corp.
Available only to licensees of Dolby Laboratories Licensing Corporation, San Francisco, CA 94111, USA, (415) 558-
0200, from whom licensing and application information must be obtained.
*2
Phillips Semiconductors, "I
2
C bus specification",January,1992
Product Note
M65863FP
April 1998
Dolby Digital Decoder
MITSUBISHI ELECTRIC CORPORATION
1
Chapter 3
Input/Output Pins
Table 3.1 shows input/output pins. "low active" pins are added "_" to tail of pin name (ex. _AERR).
Table 3.1 Input/Output Pins
Pin
No.
Pin Name
Pins I/O
Out Voltage
Description
1 VDD5V
7
-
Voltage supply 5V (I/O)
2 ASOUT
1
I/O 2mA
D5
Indication of audio data output timing (main chip output / sub chip
input)
3 CDATA
1
I/O 2mA
D5
Dynamic range compression data input from sub chip / output to main
chip
4 CCLK
1
I/O 2mA
D5
Dynamic range compression data transfer clock input from sub chip /
output to main chip
5 RSYCREQ
1
O
2mA
D5
Indication of sync word lock condition
6 SYNCRST
1
I
D5
Sync world detection start signal
7 ADVLDS
1
I
D5
Indication of valid data
8 ADATAS
1
I
D5
Data input from DEMUX
9 ACLKS
1
I
D5
Clock input from DEMUX
10 VDD3V
3
-
Voltage supply 3.3V
11 GND
7
I
GND
12 VDD5V
13 _ADREQ
1
O
2mA
D5
Data Request for DEMUX
14 _AMUTE
1
I
D5
Mute sound0 (0 : Mute ON, 1 : Mute OFF)
15 DOTX
1
O
2mA
D5
Digital audio interface IEC958 output
16 DIRX
1
I
D5
Digital audio interface IEC958 input
17 ALRCK1
1
I
D5
L/R clock from DIR/ADC
18 ACLK1
1
I
D5
Data from DIR
19 ADATA1
1
I
D5
Bit clock from DIR/ADC
20 GND
21 VDD5V
22 DEMPH
1
I
D5
De-emphasis control
23 ALRCK2
1
I
D5
L/R clock from DIR/ADC
24 ACLK2
1
I
D5
Bit clock from DIR
25 ADATA2
1
I
D5
Data from DIR
26 MCLKI
1
I
D5
Audio master clock input
27 GND
28 VDD5V
29 MCLKO
1
I
D5
Audio master clock output
30 HMCLKO
1
I
D5
Audio master clock output (1/2MCLKI)
31 DOLR
1
O
2mA
D5
PCM output for L ch and R ch
32 DOCW
1
O
2mA
D5
PCM output for C channel SW ch
33 DOSS
1
O
2mA
D5
PCM output for SL ch and SR ch
Product Note
M65863FP
April 1998
Dolby Digital Decoder
MITSUBISHI ELECTRIC CORPORATION
4
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