MITSUBISHI LSIs
( / 55 )
MITSUBISHI
ELECTRIC
16.Mar.2000
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0358-0.2
MH32S64APFB -7,-8
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
1
DESCRIPTION
The MH32S64APFB is 33554432 - word by 64-bit
Synchronous DRAM module. This consists of
sixteen industry standard 16Mx8 Synchronous
DRAMs in Small TSOP and one industory
standard EEPROM in TSSOP.
The mounting of Small TSOP on a card edge
Dual Inline package provides any application
where high densities and large quantities of
memory are required.
This is a socket type - memory modules, suitable
for easy interchange or addition of modules.
FEATURES
Clock frequency 100MHz(max.)
single 3.3V0.3V power supply
Fully synchronous operation referenced to clock rising
edge
Burst length- 1/2/4/8/Full Page(programmable)
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
APPLICATION
main memory or graphic memory in computer systems
Auto precharge / All bank precharge controlled by A10
Burst type- sequential / interleave(programmable)
Column access - random
LVTTL Interface
Auto refresh and Self refresh
4096 refresh cycle /64ms
Utilizes industry standard 16M x 8 Sy nchronous DRAMs
Small TSOP and industry standard EEPROM in TSSOP
144-pin (72-pin dual in-line package)
(Front)
(Back)
1
2
143
144
PCB Outline
Frequency
CLK Access Time
-8,-8L
100MHz
6.0ns(CL=3)
(Component SDRAM)
6.0ns(CL=3)
100MHz
-7,-7L
PC100 Compliant
MITSUBISHI LSIs
( / 55 )
MITSUBISHI
ELECTRIC
16.Mar.2000
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0358-0.2
MH32S64APFB -7,-8
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
2
NC = No Connection
PIN CONFIGURATION
PIN
Number
Front side
Pin Name
Back side
Pin Name
PIN
Number
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
PIN
Number
Front side
Pin Name
Back side
Pin Name
PIN
Number
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
21
22
93
94
23
24
95
96
25
26
97
98
27
28
99
100
29
30
101
102
31
32
103
104
33
34
105
106
35
36
107
108
37
38
109
110
39
40
111
112
41
42
113
114
43
44
115
116
45
46
117
118
47
48
119
120
49
50
121
122
51
52
123
124
53
54
125
126
55
56
127
128
57
58
129
130
59
60
131
132
61
62
133
134
63
64
135
136
65
66
137
138
67
68
139
140
69
70
141
142
71
72
143
144
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
NC
CLK1
Vss
Vss
NC
NC
NC
NC
Vcc
Vcc
DQ16
DQ48
DQ17
DQ49
DQ18
DQ50
DQ19
DQ51
Vss
Vss
Vss
Vss
DQ20
DQ52
DQMB0
DQMB4
DQ21
DQ53
DQMB1
DQMB5
DQ22
DQ54
Vcc
Vcc
DQ23
DQ55
A0
A3
Vcc
Vcc
A1
A4
A6
A7
A2
A5
A8
BA0
Vss
Vss
Vss
Vss
DQ8
DQ40
A9
BA1
DQ9
DQ41
A10
A11
DQ10
DQ42
Vcc
Vcc
DQ11
DQ43
DQMB2
DQMB6
Vcc
Vcc
DQMB3
DQMB7
DQ12
DQ44
Vss
Vss
DQ13
DQ45
DQ24
DQ56
DQ14
DQ46
DQ25
DQ57
DQ15
DQ47
DQ26
DQ58
Vss
Vss
DQ27
DQ59
NC
NC
Vcc
Vcc
NC
NC
DQ28
DQ60
CLK0
CKE0
DQ29
DQ61
Vcc
Vcc
DQ30
DQ62
/RAS
/CAS
DQ31
DQ63
/WE
CKE1
Vss
Vss
/S0
NC
SDA
SCL
/S1
NC
Vcc
Vcc
MITSUBISHI LSIs
( / 55 )
MITSUBISHI
ELECTRIC
16.Mar.2000
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0358-0.2
MH32S64APFB -7,-8
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
3
Block Diagram
CK0
Vcc
Vss
D0 - D15
D0 - D15
/S0
DQMB0
DQMB4
DQMB1
DQMB5
DQMB2
DQMB6
DQMB3
DQMB7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
CKE0
D0 - D7
/RAS
D0 - D15
/CAS
D0 - D15
/WE
D0 - D15
BA0,BA1,A<11:0>
D0 - D15
CK1
CK,DQ=10
8SDRAMs
8SDRAMs
CKE1
D8 - D15
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D0
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D1
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D8
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D9
I/O 4
I/O 5
I/O 6
I/O 7
/S1
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D4
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D5
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D12
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D13
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D2
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D3
I/O 4
I/O 5
I/O 6
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D10
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D11
I/O 4
I/O 5
I/O 6
I/O 7
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D6
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D7
I/O 4
I/O 5
I/O 6
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D14
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D15
I/O 4
I/O 5
I/O 6
I/O 7
I/O 7
SERIAL PD
SCL
SDA
A0
A1
A2
MITSUBISHI LSIs
( / 55 )
MITSUBISHI
ELECTRIC
16.Mar.2000
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0358-0.2
MH32S64APFB -7,-8
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
4
Serial Presence Detect Table I
Byte
Function described
SPD enrty data
SPD DATA(hex)
0
Defines # bytes written into serial memory at module mfgr
128
80
1
Total # bytes of SPD memory device
256 Bytes
08
2
Fundamental memory type
SDRAM
04
3
# Row Addresses on this assembly
A0-A11
0C
4
# Column Addresses on this assembly
A0-A9
0A
5
# Module Banks on this assembly
2BANK
02
6
Data Width of this assembly...
x64
40
7
... Data Width continuation
0
00
8
Voltage interface standard of this assembly
LVTTL
01
9
SDRAM Cycletime at Max. Supported CAS Latency (CL).
A0
Cycle time for CL=3
10
SDRAM Access from Clock
6ns
60
tAC for CL=3
11
DIMM Configuration type (Non-parity,Parity,ECC)
Non-PARITY
00
12
Refresh Rate/Type
self refresh(15.625uS)
80
13
SDRAM width,Primary DRAM
x8
08
14
Error Checking SDRAM data width
N/A
00
15
Minimum Clock Delay,Back to Back Random Column Addresses
1
01
16
Burst Lengths Supported
1/2/4/8/Full page
8F
17
# Banks on Each SDRAM device
4bank
04
18
CAS# Latency
19
CS# Latency
0
01
20
Write Latency
0
01
21
SDRAM Module Attributes
non-buffered,non-registered
00
22
SDRAM Device Attributes:General
Precharge All,Auto precharge
0E
23
SDRAM Cycle time(2nd highest CAS latency)
13ns
D0
Cycle time for CL=2
24
SDRAM Access form Clock(2nd highest CAS latency)
7ns
70
tAC for CL=2
25
SDRAM Cycle time(3rd highest CAS latency)
N/A
00
N/A
00
26
SDRAM Access form Clock(3rd highest CAS latency)
27
Precharge to Active Minimum
20ns
14
28
Row Active to Row Active Min.
10ns
-8,8L
-8,8L
-7,7L
10ns
A0
6ns
60
-7,7L
29
RAS to CAS Delay Min
30
Active to Precharge Min
50ns
32
2/3
06
20ns
14
20ns
14
MITSUBISHI LSIs
( / 55 )
MITSUBISHI
ELECTRIC
16.Mar.2000
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0358-0.2
MH32S64APFB -7,-8
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
5
Serial Presence Detect Table II
31
Density of each bank on module
128MByte
20
36-61
Superset Information (may be used in future)
option
00
62
SPD Revision
63
Checksum for bytes 0-62
Check sum for -8,8L
57
64-71
Manufactures Jedec ID code per JEP-108E
MITSUBISHI
1CFFFFFFFFFFFFFF
72
Manufacturing location
Miyoshi,Japan
01
Tajima,Japan
02
NC,USA
03
Germany
04
73-90
Manufactures Part Number
MH32S64APFB-8
91-92
Revision Code
PCB revision
rrrr
93-94
Manufacturing date
year/week code
yyww
95-98
Assembly Serial Number
serial number
ssssssss
99-125
Manufacture Specific Data
option
00
126
Intetl specification frequency
100MHz
64
127
Intel specification CAS# Latency support
128+
Unused storage locations
open
00
32
Command and Address signal input setup time
2ns
20
20
33
Command and Address signal input hold time
1ns
10
34
Data signal input setup time
2ns
35
Data signal input hold time
1ns
10
rev 1.2A
12
Check sum for -7,7L
17
MH32S64APFB-7
4D483136533634415046422D372020202020
-7,7L
CF
CL=2/3,AP,CK0,1
--8,8L
CD
CL=3,AP,CK0,1
MH32S64APFB-7L
4D483136533634415046422D374C20202020
4D483136533634415046422D382020202020
MH32S64APFB-8L
4D483136533634415046422D384C20202020
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