MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM

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Preliminary Spec.

Some contents are subject to change without notice.

DESCRIPTION

The MH8S64AQFC is 8388608 - word by 64-bit
Synchronous DRAM module. This consists of four
industry standard 8Mx16 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual
Inline package provides any application where
high densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable
for easy interchange or addition of modules.

FEATURES

Max. Clock frequency -6:133MHz,-7,8:100MHz

single 3.3V±0.3V power supply

Fully synchronous operation referenced to clock rising
edge

Burst length- 1/2/4/8/Full Page(programmable)

4 bank operation controlled by BA0,1(Bank Address)

/CAS latency- 2/3(programmable)

APPLICATION

main memory or graphic memory in computer systems

Auto precharge / All bank precharge controlled by A10

Burst type- sequential / interleave(programmable)

Column access - random

LVTTL Interface

Auto refresh and Self refresh

4096 refresh cycle /64ms

Utilizes industry standard 8M x 16 Sy nchronous DRAMs
TSOP and industry standard EEPROM in TSSOP

144-pin (72-pin dual in-line package)

(Front)
(Back)

1
2

143
144

PCB Outline

Frequency

CLK Access Time

-8,-8L

100MHz

6.0ns(CL=2)

(Component SDRAM)

6.0ns(CL=3)

100MHz

-7,-7L

5.4ns(CL=3)

-6,-6L

133MHz

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM

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Preliminary Spec.

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NC = No Connection

PIN CONFIGURATION

PIN

Number

Front side

Pin Name

Back side

Pin Name

PIN

Number

1
3
5

7
9

11
13
15
17
19

2
4
6

10
12
14
16
18
20

PIN

Number

Front side

Pin Name

Back side

Pin Name

PIN

Number

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

Vss

DQ0
DQ1

DQ2
DQ3

Vcc

DQ4
DQ5
DQ6
DQ7

Vss

DQ32
DQ33

DQ34
DQ35

Vcc

DQ36
DQ37
DQ38
DQ39

CLK1

Vss

Vcc

DQ16

DQ48

DQ17

DQ49

DQ18

DQ50

DQ19

DQ51

Vss

DQ20

DQ52

DQMB0

DQMB4

DQ21

DQ53

DQMB1

DQMB5

DQ22

DQ54

Vcc

DQ23

DQ55

Vcc

BA0

Vss

DQ8

DQ40

BA1

DQ9

DQ41

A10

A11

DQ10

DQ42

Vcc

DQ11

DQ43

DQMB2

DQMB6

Vcc

DQMB3

DQMB7

DQ12

DQ44

Vss

DQ13

DQ45

DQ24

DQ56

DQ14

DQ46

DQ25

DQ57

DQ15

DQ47

DQ26

DQ58

Vss

DQ27

DQ59

Vcc

DQ28

DQ60

CLK0

CKE0

DQ29

DQ61

Vcc

DQ30

DQ62

/RAS

/CAS

DQ31

DQ63

/WE

CKE1

Vss

/S0

SDA

SCL

/S1

Vcc

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM

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Preliminary Spec.

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Block Diagram

CLK0

SERIAL PD

SCL

SDA

Vcc

Vss

D0 - D3

/S0

DQMB0

DQMB4

DQMB1

DQMB5

DQMB2

DQMB6

DQMB3

DQMB7

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

CKE0

D0 - D3

/RAS

D0 - D3

/CAS

D0 - D3

/WE

D0 - D3

BA0,BA1,A<11:0>

D0 - D3

CLK1

I/O 0
I/O 1
I/O 2
I/O 3

DQML /CS

I/O 4

I/O 5
I/O 6

I/O 7

I/O 8
I/O 9

I/O 10
I/O 11

DQMU

I/O 12

I/O 13
I/O 14

I/O 15

I/O 0
I/O 1
I/O 2
I/O 3

DQML /CS

I/O 4

I/O 5
I/O 6

I/O 7

I/O 8
I/O 9

I/O 10
I/O 11

DQMU

I/O 12

I/O 13
I/O 14

I/O 15

I/O 0
I/O 1
I/O 2
I/O 3

DQML /CS

I/O 4

I/O 5
I/O 6

I/O 7

I/O 8
I/O 9

I/O 10
I/O 11

DQMU

I/O 12

I/O 13
I/O 14

I/O 15

I/O 0
I/O 1
I/O 2
I/O 3

DQML /CS

I/O 4

I/O 5
I/O 6

I/O 7

I/O 8
I/O 9

I/O 10
I/O 11

DQMU

I/O 12

I/O 13
I/O 14

I/O 15

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM

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Preliminary Spec.

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Serial Presence Detect Table I

Byte

Function described

SPD enrty data

SPD DATA(hex)

Defines # bytes written into serial memory at module mfgr

128

Total # bytes of SPD memory device

256 Bytes

Fundamental memory type

SDRAM

# Row Addresses on this assembly

A0-A11

# Column Addresses on this assembly

A0-A8

# Module Banks on this assembly

1BANK

Data Width of this assembly...

x64

... Data Width continuation

Voltage interface standard of this assembly

LVTTL

SDRAM Cycletime at Max.Supported CAS Latency (CL).

Cycle time for CL=3

SDRAM Access from Clock

6ns

tAC for CL=3

DIMM Configuration type (Non-parity,Parity,ECC)

Non-PARITY

Refresh Rate/Type

self refresh(15.625uS)

SDRAM width,Primary DRAM

x16

Error Checking SDRAM data width

N/A

Minimum Clock Delay,Back to Back Random Column Addresses

Burst Lengths Supported

1/2/4/8/Full page

# Banks on Each SDRAM device

4bank

CAS# Latency

2/3

CS# Latency

Write Latency

SDRAM Module Attributes

non-buffered,non-registered

SDRAM Device Attributes:General

Precharge All,Auto precharge

SDRAM Cycle time(2nd highest CAS latency)

13ns

Cycle time for CL=2

SDRAM Access form Clock(2nd highest CAS latency)

7ns

tAC for CL=2

SDRAM Cycle time(3rd highest CAS latency)

N/A

SDRAM Access form Clock(3rd highest CAS latency)

10ns

-8,-8L

10ns

6ns

7.5ns

5.4ns

-6,-6L

-7,-7L,-8,-8L

-6,-6L

-7,-7L,-8,-8L

-6,-6L,-7,-7L

Precharge to Active Minimum

20ns

Row Active to Row Active Min.

15ns

RAS to CAS Delay Min

22.5ns

Active to Precharge Min

50ns

22.5ns

20ns

45ns

-6,-6L

-7,-7L,-8,-8L

-6,-6L

-7,-7L,-8,-8L

-6,-6L

-7,-7L,-8,-8L

-6,-6L

-7,-7L,-8,-8L

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM

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Preliminary Spec.

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Serial Presence Detect Table II

Density of each bank on module

64MByte

36-61

Superset Information (may be used in future)

option

SPD Revision

Checksum for bytes 0-62

Check sum for -8,-8L

64-71

Manufactures Jedec ID code per JEP-108E

MITSUBISHI

1CFFFFFFFFFFFFFF

Manufacturing location

Miyoshi,Japan

Tajima,Japan

NC,USA

Germany

73-90

Manufactures Part Number

MH8S64AQFC-8

MH8S64AQFC-8L

91-92

Revision Code

PCB revision

rrrr

93-94

Manufacturing date

year/week code

yyww

95-98

Assembly Serial Number

serial number

ssssssss

99-125

Manufacture Specific Data

option

126

Intetl specification frequency

100MHz

127

Intel specification CAS# Latency support

128+

Unused storage locations

open

Command and Address signal input setup time

Command and Address signal input hold time

Data signal input setup time

Data signal input hold time

rev 1.2B

Check sum for -7,-7L

MH8S64AQFC-7

4D4838533634415146432D37202020202020

-6,-6L,-7,7L

-8,8L

MH8S64AQFC-7L

4D4838533634415146432D374C2020202020

4D4838533634415146432D38202020202020

4D4838533634415146432D384C2020202020

2ns

1ns

2ns

1ns

1.5ns

0.8ns

1.5ns

0.8ns

Check sum for -6,-6L

MH8S64AQFC-6

MH8S64AQFC-6L

-6,-6L

-7,-7L,-8,-8L

-6,-6L

-7,-7L,-8,-8L

-6,-6L

-7,-7L,-8,-8L

-6,-6L

-7,-7L,-8,-8L

CL=2/3,AP,CK0,1

CL=3,AP,CK0,1

4D4838533634415146432D364C2020202020

4D4838533634415146432D36202020202020

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM

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Preliminary Spec.

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PIN FUNCTION

Input

Master Clock:All other inputs are referenced to the rising
edge of CK

CKE0

Input

Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE E becomes asynchronous input.Self
refresh is maintained as long as CKE is low.

/S0

Input

Chip Select: When /S is high,any command means
No Operation.

/RAS,/CAS,/WE

Input

Combination of /RAS,/CAS,/WE defines basic commands.

A0-11

Input

A0-11 specify the Row/Column Address in conjunction with
BA0,1.The Row Address is specified by A0-11.The Column
Address is specified by A0-8.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.

BA0,1

Input

Bank Address:BA0,1 is not simply BA.BA specifies the
bank to which a command is applied.BA0,1 must be set
with ACT,PRE,READ,WRITE commands

DQ0-63

Input/Output Data In and Data out are referenced to the rising edge

of CK

DQMB0-7

Input

Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is
high in burst read,Dout is disabled at the next but one cycle.

Vdd,Vss

Power Supply Power Supply for the memory mounted module.

SCL

SDA

Input

Output

Serial clock for serial PD

Serial data for serial PD

CLK0

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM

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Preliminary Spec.

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BASIC FUNCTIONS

Chip Select : L=select, H=deselect

/RAS

Command

/CAS

Command

/WE

Command

CKE

Ref resh Option @ref resh
command

A10

Precharge Option @precharge or read/write
command

def ine basic commands

The MH8S64AQFC provides basic functions ,bank(row)activate,burst read / write,
bank(row)precharge,and auto / self refresh.
Each command is defined by control s ignals of /RAS,/CAS and /WE at CK rising edge.
In addition to 3 s ignals,/S,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
To know the detailed definition of commands please see the command truth table.

Activate(ACT) [/RAS =L, /CAS = /WE =H]

Read(READ) [/RAS =H,/CAS =L, /WE =H]

Write(WRITE) [/RAS =H, /CAS = /WE =L]

Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]

Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]

ACT command activates a row in an idle bank indicated by BA.

READ command starts burst read from the active bank indicated by BA.Firs t output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,

READA).

WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank is
deactivated after the burst write(auto-precharge,

WRITEA).

PRE command deactivates the active bank indicated by BA. This command also
term inates burst read / write operation. When A10 =H at this command, both banks
are deactivated(precharge all,

PREA).

PEFA command starts auto-refresh cycle. Refresh address including bank address
are generated internally. After this command, the banks are precharged automatically.

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM

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Preliminary Spec.

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H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number

NOTE:
1.A7-9 = 0, A0-6 = Mode Address

COMMAND TRUTH TABLE

COMMAND

MNEMONIC

CKE

n-1

CKE

/RAS /CAS

/WE BA0,1

A10

A0-9

Deselect

DESEL

No Operation

NOP

Row Adress Entry &

Bank Activate

ACT

Single Bank Precharge

PRE

Precharge All Bank

PREA

Column Address Entry

& Write

WRIT E

Column Address Entry

& Write with Auto-

Precharge

WRITEA

Column Address Entry

& Read

READ

Column Address Entry

& Read with Auto

Precharge

READA

Auto-Refresh

REFA

Self-Refresh Entry

REFS

Self-Refresh Exit

REFSX

Burst Terminate

TERM

Mode Register Set

MRS

V*1

A11

X
X

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM

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Preliminary Spec.

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Current State

/RAS /CAS

/WE

Address

Command

Action

IDLE

DESEL

NOP

TBST

ILLEGAL*2

BA,CA,A10

READ/WRITE ILLEGAL*2

BA,RA

ACT

Bank Active,Latch RA

BA,A10

PRE/PREA

NOP*4

REFA

Auto-Refresh*5

Op-Code,

Mode-Add

MRS

Mode Register Set*5

ROW ACTIVE

DESEL

NOP

TBST

NOP

BA,CA,A10

READ/READA

Begin Read,Latch CA,

Determine Auto-Precharge

BA,CA,A10

WRITE/

WRITEA

Begin Write,Latch CA,

Determine Auto-Precharge

BA,RA

ACT

Bank Active/ILLEGAL*2

BA,A10

PRE/PREA

Precharge/Precharge All

REFA

ILLEGAL

Op-Code,

Mode-Add

MRS

ILLEGAL

READ

DESEL

NOP(Continue Burst to END)

NOP

NOP(Continue Burst to END)

TBST

Terminate Burst

BA,CA,A10

READ/READA

Terminate Burst,Latch CA,

Begin New Read,Determine

Auto-Precharge*3

BA,CA,A10 WRITE/WRITEA

Terminate Burst,Latch CA,

Begin Write,Determine Auto-

Precharge*3

BA,RA

ACT

Bank Active/ILLEGAL*2

BA,A10

PRE/PREA

Terminate Burst,Precharge

REFA

ILLEGAL

Op-Code,

Mode-Add

MRS

ILLEGAL

FUNCTION TRUTH TABLE

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM

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Preliminary Spec.

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FUNCTION TRUTH TABLE(continued)

Current State

/RAS /CAS

/WE

Address

Command

Action

WRIT E

DESEL

NOP(Continue Burst to END)

NOP

NOP(Continue Burst to END)

TBST

Terminate Burst

BA,CA,A10

READ/READA

Terminate Burst,Latch CA,

Begin Read,Determine Auto-

Precharge*3

BA,CA,A10

WRITE/

WRITEA

Terminate Burst,Latch CA,

Begin Write,Determine Auto-

Precharge*3

BA,RA

ACT

Bank Active/ILLEGAL*2

BA,A10

PRE/PREA

Terminate Burst,Precharge

REFA

ILLEGAL

Op-Code,

Mode-Add

MRS

ILLEGAL

READ with

DESEL

NOP(Continue Burst to END)

AUT O

NOP

NOP(Continue Burst to END)

PRECHARGE

TBST

ILLEGAL

BA,CA,A10

READ/READA ILLEGAL

BA,CA,A10

WRITE/

WRITEA

ILLEGAL

BA,RA

ACT

Bank Active/ILLEGAL*2

BA,A10

PRE/PREA

ILLEGAL*2

REFA

ILLEGAL

Op-Code,

Mode-Add

MRS

ILLEGAL

WRITE with

DESEL

NOP(Continue Burst to END)

AUT O

NOP

NOP(Continue Burst to END)

PRECHARGE

TBST

ILLEGAL

BA,CA,A10

READ/READA ILLEGAL

BA,CA,A10

WRITE/

WRITEA

ILLEGAL

BA,RA

ACT

Bank Active/ILLEGAL*2

BA,A10

PRE/PREA

ILLEGAL*2

REFA

ILLEGAL

Op-Code,

Mode-Add

MRS

ILLEGAL

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM

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Preliminary Spec.

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FUNCTION TRUTH TABLE(continued)

Current State

/RAS

/CAS

/WE

Address

Command

Action

PRE -

DESEL

NOP(Idle after tRP)

CHARGING

NOP

NOP(Idle after tRP)

TBST

ILLEGAL*2

BA,CA,A10

READ/WRITE ILLEGAL*2

BA,RA

ACT

ILLEGAL*2

BA,A10

PRE/PREA

NOP*4(Idle after tRP)

REFA

ILLEGAL

Op-Code,

Mode-Add

MRS

ILLEGAL

ROW

DESEL

NOP(Row Active after tRCD

ACT IVATING

NOP

NOP(Row Active after tRCD

TBST

ILLEGAL*2

BA,CA,A10

READ/WRITE ILLEGAL*2

BA,RA

ACT

ILLEGAL*2

BA,A10

PRE/PREA

ILLEGAL*2

REFA

ILLEGAL

Op-Code,

Mode-Add

MRS

ILLEGAL

WRITE RE-

DESEL

NOP

COVERING

NOP

TBST

ILLEGAL*2

BA,CA,A10

READ/WRITE ILLEGAL*2

BA,RA

ACT

ILLEGAL*2

BA,A10

PRE/PREA

ILLEGAL*2

REFA

ILLEGAL

Op-Code,

Mode-Add

MRS

ILLEGAL

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM

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Preliminary Spec.

Some contents are subject to change without notice.

FUNCTION TRUTH TABLE(continued)

Current State

/RAS /CAS

/WE

Address

Command

Action

RE-

DESEL

NOP(Idle after tRC)

FRESHING

NOP

NOP(Idle after tRC)

TBST

ILLEGAL

BA,CA,A10

READ/WRITE ILLEGAL

BA,RA

ACT

ILLEGAL

BA,A10

PRE/PREA

ILLEGAL

REFA

ILLEGAL

Op-Code,

Mode-Add

MRS

ILLEGAL

MODE

DESEL

NOP(Idle after tRSC)

NOP

NOP(Idle after tRSC)

SETTING

TBST

ILLEGAL

BA,CA,A10

READ/WRITE ILLEGAL

BA,RA

ACT

ILLEGAL

BA,A10

PRE/PREA

ILLEGAL

REFA

ILLEGAL

Op-Code,

Mode-Add

MRS

ILLEGAL

ABBREVIATIONS:
H = Hige Level, L = Low Level, X = Don't Care
BA = Bank Address , RA = Row Address, CA = Column Address, NOP = No Operation

NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current
clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA,
depending on the state of that bank.
3. Mus t satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.

ILLEGAL = Device operation and / or date-integrity are not guaranteed.

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM

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Preliminary Spec.

Some contents are subject to change without notice.

FUNCTION TRUTH TABLE FOR CKE

Current State

n-1

/RAS /CAS

/WE

Add

Action

SELF -

INVALID

REFRESH*1

Exit Self-Refresh(Idle after tRC)

ILLEGAL

NOP(Maintain Self-Refresh)

POWER

INVALID

DOWN

Exit Power Down to Idle

NOP(Maintain Self-Refresh)

ALL BANKS

Refer to Function Truth Table

IDLE*2

Enter Self-Refresh

Enter Power Down

ILLEGAL

Refer to Current State = Power Down

ANY STATE

Refer to Function Truth Table

other than

Begin CK0 Suspend at Next Cycle*3

listed above

Exit CK0 Suspend at Next Cycle*3

Maintain CK0 Suspend

ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care

NOTES:
1. CKE Low to High transition will re-enable CK and other inputs

asynchronously.

A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only form the All banks idle State.
3. Mus t be legal command.

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM

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Preliminary Spec.

Some contents are subject to change without notice.

POWER ON SEQUENCE

Before starting normal operation, the following power on sequence is necessary to prevent
a SDRAM from damaged or malfunctioning.

1. Apply power and start clock.Attempt to maintain CKE high,DQM0-7 high and NOP
condition at the inputs .
2. Maintain stable power, s table cock, and NOP input conditions for a m inimum of 200us.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.

After these sequence, the SDRAM is idle state and ready for normal operation.

MODE REGISTER

Burst Length, Burs t Type and /CAS Latency can be programmed by setting the mode
register(MRS). The mode register stores these date until the next MRS command, which
may be issued when both banks are in idle state. After tRSC from a MRS command, the
SDRAM is ready for new command.

R:Reserved for Future Use

/RAS

/CAS

/WE

BA0,1 A11-0

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0
1 1 1

BURST

LENGTH

BT= 0

BT= 1

R
R

BURST

TYPE

SEQUENTIAL

INTERLEAVED

A11 A10 A9

BA1

BA0

LTMODE

0 0 0

0 0 1

0 1 0

0 1 1
1 0 0

1 0 1

1 1 0

1 1 1

LATENCY

MODE

/CAS LATENCY

WRIT E

MODE

BURST

SINGLE BIT

FP: Full Page

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM

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Preliminary Spec.

Some contents are subject to change without notice.

Command

Address

Read

Write

/CAS Latency

Burst Length

Burst Type

CL= 3
BL= 4

Initial Address

Sequential

Interleaved

Column Addressing

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

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Preliminary Spec.

Some contents are subject to change without notice.

Bank Activation and Precharge All (BL=4, CL=2)

Command

A0-9,11

A10

BA0,1

ACT

READ

Y b

Qa0

Qa1

Qa2

Qa3

ACT

PRE

tRRD

tRCD

ACT

Precharge all

tRP

OPERATION DESCRIPTION

BANK ACTIVATE
One of four banks is activated by an ACT command.
An bank is selected by BA0-1. A row is selected by A0-11.
Multiple banks can be active state concurrently by issuing multiple ACT commands.
Minimum activation interval between one bank and another bank is tRRD.

PRECHARGE
An open bank is deactivated by a PRE command.
A bank to be deactivated is designated by BA0-1.
When multiple banks are active, a precharge all command (PREA, PRE + A10=H)
deactivates all of open banks at the same time. BA0-1 are "Don't Care" in this case.
Minimum delay time of an ACT command after a PRE command to the same bank is tRP.

READ
A READ command can be issued to any active bank. The start address is specified by A0-8
(x16) . 1s t output data is available after the /CAS Latency from the READ. The consecutive
data length is defined by the Burst Length. The address sequence of the burst data is
defined by the Burs t Type. Minimum delay time of a READ command after an ACT command
to the same bank is tRCD.
When A10 is high at a READ command, auto-precharge (READA) is performed. Any
command (READ, WRITE, PRE, ACT, TBST) to the same bank is inhibited till the internal
precharge is complete. The internal precharge starts at the BL after READA. The next ACT
command can be issued after (BL + tRP) from the previous READA. In any case, tRCD+BL >
tRASmin must be met.

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM

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Preliminary Spec.

Some contents are subject to change without notice.

Multi Bank Interleaving READ (BL=4, CL=2)

Command

A0-9, 11

A10

BA0,1

ACT

READ

Y a

READ

Y b

Qa0

Qa1

Qa2

Qa3

Qb0

Qb1

Qb2

ACT

PRE

tRCD

READ with Auto-Precharge (BL=4, CL=2)

Command

A10

ACT

READ

Y a

Qa0

Qa1

Qa2

Qa3

ACT

Internal precharge starts

tRCD

tRP

Auto-Precharge Timing (READ BL=4)

Command

ACT

READ

Internal precharge starts

Qa0

Qa1

Qa2

Qa3

Qa0

Qa1

Qa2

Qa3

CL=3

CL=2

A0-9, 11

BA0,1

tRCD

ACT

tRP

tRCD

ACT

Qb3

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

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Preliminary Spec.

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WRITE (BL=4)

Command

A10

ACT

Write

Y a

Da0

Da1

Da2

Da3

PRE

tRCD

Command

A10

ACT

Write

Y a

Da0

Da1

Da2

Da3

ACT

Internal precharge begins

tRCD

tRP

WRITE with Auto-Precharge (BL=4)

WRITE
A WRITE command can be issued to any active bank. The start address is specified by A0-8
(x16). 1st input data is set at the same cycle as the WRITE. The consecutive data length to
be written is defined by the Burs t Length. The address sequence of burst data is defined by
the Burs t Type. Minimum delay time of a WRITE command after an ACT command to the
same bank is tRCD. From the last input data to the PRE command, the write recovery time
(tWR) is required. When A10 is high at a WRITE command, auto-precharge (WRITEA) is
performed. Any command (READ, WRITE, PRE, ACT, TBST) to the same bank is inhibited till
the internal precharge is complete. The internal precharge starts at tWR after the last input
data cycle. The next ACT command can be issued after (BL + tWR -1 + tRP) from the
previous WRITEA. In any case, tRCD + BL + tWR -1 > tRASm in must be met.

A0-9, 11

BA0,1

A0-9, 11

BA0,1

ACT

tWR

tRP

tWR

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

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Preliminary Spec.

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BURST INTERRUPTION
[ Read Interrupted by Read ]
Burst read oparation can be interrupted by new read of the same or the other bank. Random
column access is allowed READ to READ interval is minimum 1 CK

Read Interrupted by Read (BL=4, CL=2)

Command

A10

READ

Y a

READ

Y b

Qa0

Qa2

Qb0

Qc0

Qa1

Qc1

Qc2

READ

Y c

Qc3

[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of any active bank. Random column access
is allowed. In this case, the DQ should be controlled adequately by us ing the DQMB0-7 to
prevent the bus contention. The output is disabled automatically 1 cycle after WRITE
assertion.

Read Interrupted by Write (BL=4, CL=2)

Command

A10

READ

Y a

Qa0

Write

Y a

Da0

Da1

Da2

Da3

DQMB0-7

A0-9,11

BA0,1

A0-9,11

BA0,1

ACT

Output disable by DQM by WRITE

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

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Preliminary Spec.

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[ Read Interrupted by Burst Terminate ]
Similarly to the precharge, burst terminate command can interrupt burst read operation
and disable the data output. The term inated bank remains active,READ to TBST interval is
minimum of 1 CK. A TBSTcommand to output disable latency is equivalent to the /CAS
Latency.

Read Interrupted by Terminate (BL=4)

Command

READ

TBST

CL=3

Command

READ

TBST

Command

READ TBST

Command

READ

TBST

CL=2

Command

READ

TBST

Command

READ TBST

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

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Preliminary Spec.

Some contents are subject to change without notice.

[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of any active bank. Random
column access is allowed. WRITE to WRITE interval is minimum 1 CK.

Write Interrupted by Write (BL=4)

Command

A10

Write

Y a

Write

Y b

Da0

Da1

Da2

Db0

Dc0

Dc1

Write

Y c

Dc2

Dc3

[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of any active bank. Random column
access is allowed. WRITE to READ interval is minimum 1 CK. The input data on DQ
at the interrupting READ cycle is "don't care".

Write Interrupted by Read (BL=4, CL=2)

Command

A10

Write

Y a

Qb0

READ

Y b

Qb1

Da0

Qb2

Qb3

A0-9, 11

BA0,1

A0-9,11

BA0,1

ACT

Da1

don't care

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM

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Preliminary Spec.

Some contents are subject to change without notice.

[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of the same bank . Write
recovery time(tWR) is required from the last data to PRE command. During write
recovery, data inputs must be masked by DQM.

Write Interrupted by Precharge (BL=4)

Command

A10

ACT

Write

Da0

Da1

DQMB0-7

ACT

tRP

[ Write Interrupted by Burst Terminate ]
Burst terminate command can terminate burst write operation. In this case, the
write recovery time is not required and the bank remains active.The WRITE to TBST
minimum interval is 1CK.

Write Interrupted by Burst Terminate (BL=4)

Command

A10

ACT

TBST

Da0

Da1

A0-9,11

BA0,1

A0-9,11

BA0,1

Y a

PRE

tWR

Write

Y a

Write

Y b

Db0

Db1

Db2

Db3

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM

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MIT-DS-0374-0.3

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Preliminary Spec.

Some contents are subject to change without notice.

[ Write with Auto-Precharge interrupted by Write or Read to anotehr Bank ]
Burst write with auto-precharge can be interrupted by write or read toanother bank .
Next ACT command can be issued after (BL+tWR-1+tRP) from the WRITEA. Auto-
precharge interrrupted by a command to the same bank is inhibited.

WRITEA Interrupted by WRITE to another bank (BL=4)

Command

A10

Write

Y a

Write

Da0

Da1

ACT

tRP

WRITEA interrupted by READ to another bank (CL=2,BL=4)

Command

A10

Write

Y a

Da0

Da1

A0-9,11

BA0,1

A0-9,11

BA0,1

Y a

Read

Y b

ACT

Db0

Db1

Db2

Db3

Db0

Db1

Db2

Db3

auto-precharge interrupted

activate

tWR

tRP

tWR

auto-precharge interrupted

activate

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM

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Preliminary Spec.

Some contents are subject to change without notice.

[ Read with Auto-Precharge interrupted by Read to anotehr Bank ]
Burst read with auto-precharge can be interrupted by read toanother bank . Next
ACT command can be issued after (BL+tRP) from the READA. Auto-precharge
interrrupted by a command to the same bank is inhibited.

READA Interrupted by READ to another bank (CL=2,BL=4)

Command

A10

Read

Y a

Read

Qa0

Qa1

ACT

tRP

A0-9,11

BA0,1

Y a

Qb0

Qb1

Qb2

Qb3

auto-precharge interrupted

activate

tWR

Full Page Burst
Full page burst length is available for only the sequential burst type. Full page burst
read or write is repeated untill aPrecharge or a Burst Terminate command is
issued. In case of the full page burst , a read or write with auto-precharge command
is illegal.

Single Write
When single write mode is set, burst length for write is always one, independently
of Burst Length defined by (A2-0).

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

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Preliminary Spec.

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AUTO REFRESH
Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,
/WE=/CKE=H) command. The refresh address is generated internally. 4096 REFA
cycle within 64m s refresh 128Mbit memory cells. The auto-refresh is performed on
4banks concurrently. Before performing an auto-refresh, all banks must be in the
idle state. Auto-refresh to auto-refresh interval is minimum tRFC. Any command
must not be issued before tRFC from the REFA command.

Auto-Refresh

/RAS

/CAS

/WE

CKE

A0-11

BA0,1

Auto Refresh on All Banks

minimum tRFC

NOP or DESLECT

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

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Preliminary Spec.

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SELF REFRESH
Self-refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L,
/WE=H, CKE=L). Once the self-refresh is initiated, it is maintained as log as CKE is
kept low.During the self-refresh mode, CKE is asynchronous and the only enabled
input , all other inputs including CK are disabled and ignored, so that power
consumption due to synchronous inputs is saved. To exit the self-refresh, supplying
stable CK inputs , asserting DESEL or NOP command and then asserting CKE=H.
After tRFC from the 1s t CK edge follwing CKE=H, all banks are in the idle state and
a new command can be issued after, but DESEL or NOP commands must be
asserted till then.

Self-Refresh

/RAS

/CAS

/WE

CKE

A0-11

BA0,1

Self Refresh Entry

Self Refresh Exit

minimum tRFC
for recovery

Stable CK

NOP

new command

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM

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Preliminary Spec.

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CLK SUSPEND and POWER DOWN
CKE controls the internal CLK at the following cycle. Figure below shows how CKE
works. By negating CKE, the next internal CLK is suspended. The purpose of CLK
suspend is power down, output suspend or input suspend. CKE is a synchronous
input except during the self-refresh mode. CLK suspend can be performed either
when the banks are active or idle. A command at the suspended cycle is ignored.

CK
(ext.CLK)

CKE

int.CLK

Power Down by CKE

Command

PRE

CKE

Command

CKE

ACT

NOP

Standby Power Down

Activ e Power Down

NOP

DQ Suspend by CKE

Command

Write

CKE

READ

tIH

tIS

tIH

tIS

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

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Preliminary Spec.

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ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Condition

Ratings

Unit

Vdd

Topr

Tstg

Supply Voltage

Input Voltage

Output Voltage

Output Current

Power Dissipation

Operating Temperature

Storage Temperature

with respect to Vs s

Ta=25°C

-0.5 ~ 4.6

0 ~ 70

-40 ~ 100

°C

RECOMMENDED OPERATING CONDITION

(Ta=0 ~ 70°C, unless otherwise noted)

Symbol

Vdd

Vss

VIH

VIL

Parameter

Supply Voltage

High-Level Input Voltage all inputs

Supply Voltage

Low-Level Input Voltage all inputs

Limits

Unit

Min.

Typ.

Max.

3.0

2.0

-0.3

3.3

3.6

Vdd+0.3

0.8

CAPACITANCE

(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)

Symbol

CI(A)

CI(C)

CI(K)

CI/O

Parameter

Input Capacitance, address pin

Input Capacitance, /RAS,/CAS,/WE

Input Capacitance, CK pin

Input Capacitance, I/O pin

Tes t Condition

Limits(max.)

Unit

@1MHz

1.4V bias

200mV swing

Note)
1:VIH(max)=5.5V f or pulse width less than 10ns.
2.VIL(min)=-1.0 f or pulse width less than 10ns.

-0.5 ~ 4.6

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

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Preliminary Spec.

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AVERAGE SUPPLY CURRENT from Vdd

(Ta=0 ~70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)

AC OPERATING CONDITIONS AND CHARACTERISTICS

(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)

Symbol

Parameter

Test Condition

Limits

Unit

Min. Max.

VOH(DC) High-Level Output Voltage(DC) IOH=-2mA

2.4

VOL(DC) Low-Level Output Voltage(DC) IOL=2mA

0.4

VOH(AC) High-Level Output Voltage(AC) CL=50pF, IOH=-

2mA

VOL(AC) Low-Level Output Voltage(AC) CL=50pF, IOL=2mA

0.8

IOZ

Off-stare Output Current

Q floating VO=0 ~ Vdd

-10

Input Current

VIH=0 ~ Vdd+0.3V

-40

Note)
1:Icc(max) is specif ied at the output open condition.
2.Input signals are changed one time during 30ns.

480

100

520

640

120

Test Condition

Unit

tRC=min.tCLK=min, BL=1,CL=3

CKE=L,tCLK=15ns, /CS>Vcc-0.2V

CKE=CLK=L, /CS>Vcc-0.2V

mA
mA

tCLK=min, BL=4, CL=3,all banks activ e(discerte)

tRC=min, tCLK=min

CKE <0.2V

CKE=H,tCLK=15ns,VIH>Vcc-0.2V,VIL<0.2V

Symbol

Icc1

Icc2P

Icc2PS

Icc2NS

Icc4
Icc5

Icc6

Icc2N

Parameter

operating current
one bank activ e (discrete)

precharge stanby
current
in power-down mode

burst current

auto-refresh current

self-refresh current

CKE=H,CLK=L,VIH>Vcc-0.2V,VIL<0.2V(f ixed)

precharge stanby current
in non power-down mode

CKE=H,tCLK=15ns

Icc3NS

Icc3N

CKE=H,CLK=L

active stanby current
in non power-down mode

one bank activ e (discrete)

3.2

-6,-7,-8

-6L,-7L,-8L

520

100

640

120

Limits
(max)

3.2

-7,-7L

-6,-6L

-8,-8L

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

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Preliminary Spec.

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AC TIMING REQUIREMENTS (SDRAM Component)

(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Input Pulse Levels: 0.8V to 2.0V
Input Timing Measurement Level: 1.4V

Signal

1.4V

Any AC timing is

referenced to the input

signal crossing

through 1.4V.

Limits

Symbol Parameter

-7,-7L

Unit

Min.

Max.

tCLK

CK cycle time

tCH

CK High pulse width

tCL

CK Low pilse width

Transition time of CK

tIS

Input Setup time(all inputs)

tIH

Input Hold time(all inputs)

tRC

Row cycle tim e

tRCD Row to Column Delay

tRAS

Row Active time

100K

tRP

Row Precharge tim e

tWR

Write Recovery time

tRRD Act to Act Deley time

tRSC Mode Register Set Cycle time

tSRX Self Refresh Exit tim e

tREF

Refresh Interval time

-8,-8L

Min.

Max.

3
1

2
1

70
20
50

100K

20
12
20
10
10

CL=2

CL=3

tPDE Power Down Exit time

-6,-6L

Min.

Max.

2.5

7.5

1.5
0.8

67.5

20
45

100K

15
10

7.5

2.5

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM

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Preliminary Spec.

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1.4V

tAC

tOH

tOHZ

SWITCHING CHARACTERISTICS (SDRAM Component)

(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise note3)

Output Load Condition

Output Timing
Measurement
Reference Point

1.4V

Note)
1 If clock rising time is longer than 1ns,(tT/2-0.5)ns should be added to parameter.

Limits

Symbol Parameter

-8

Unit

Min.

Max.

tAC

Access time from CK

tOH

Output Hold tim e

from CK

tOLZ

Delay time, output low

impedance from CK

tOHZ

Delay time, output high

impedance from CK

-7

Min.

Max.

CL=2

CL=3

CL=2

OUT

50pF

tOLZ

CL=3

-6

Min.

2.7

5.4

Max.

5.4

2.7

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM

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Preliminary Spec.

Some contents are subject to change without notice.

Burst Write (multi bank) with Auto-Precharge @BL=4

/CS

/RAS

/CAS

/WE

CKE

BA0,1

ACT#0

WRITE#0 with
AutoPrecharge

ACT#0

WRITE#0

tRCD

tRC

tRCD

tRRD

tRRD

ACT#1

WRITE#1 with
AutoPrecharge

BL-1+

tWR + tRP

tRCD

ACT#1

WRITE#1

CLK

BL-1+

tWR + tRP

Italic parameter indicates minimum case

A0-8

A10

DQM

A9,11

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM

MITSUBISHI LSIs

( / 55 )

22.Sep.2000

MIT-DS-0374-0.3

MITSUBISHI
ELECTRIC

Preliminary Spec.

Some contents are subject to change without notice.

Burst Read (multiple bank) with Auto-Precharge @BL=4 CL=3

/CS

/RAS

/CAS

/WE

CKE

BA0,1

ACT#0

READ#0 with
Auto-Precharge

ACT#0

READ#0

tRCD

tRC

tRCD

CL=3

DQM read latency =2

tRRD

ACT#1

tRRD

CL=3

READ#1 with
Auto-Precharge

ACT#1

BL+

tRP

BL+

tRP

CLK

CL=3

tRCD

Italic parameter indicates minimum case

A0-8

A10

DQM

A9,11

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM

MITSUBISHI LSIs

( / 55 )

22.Sep.2000

MIT-DS-0374-0.3

MITSUBISHI
ELECTRIC

Preliminary Spec.

Some contents are subject to change without notice.

Read Interrupted by Read / Write @BL=4 CL=3

/CS

/RAS

/CAS

/WE

CKE

BA0,1

ACT#0

READ#0

WRITE#0

tRCD

READ#1

CLK

tRRD

ACT#1

READ#0

DQM read latency=2

Burst Read can be interrupted by Read or Write of any active bank.

READ#0

blank to prevent bus contention

Italic parameter indicates minimum case

A0-8

A10

DQM

A9,11

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM

MITSUBISHI LSIs

( / 55 )

22.Sep.2000

MIT-DS-0374-0.3

MITSUBISHI
ELECTRIC

Preliminary Spec.

Some contents are subject to change without notice.

Read Interrupted by Precharge @BL=4 CL=3

/CS

/RAS

/CAS

/WE

CKE

BA0,1

ACT#0

READ#0

tRCD

PRE#1

CLK

tRRD

ACT#1

PRE#0

DQM read latency=2

Burst Read is not interrupted
by Precharge of the other bank.

tRCD

tRP

READ#1

ACT#1

READ#1

Burst Read is interrupted
by Precharge of the same bank.

Italic parameter indicates minimum case

A0-8

A10

DQM

A9,11

MH8S64AQFC -6,-6L,-7,-7L,-8,-8L

536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM

MITSUBISHI LSIs

( / 55 )

22.Sep.2000

MIT-DS-0374-0.3

MITSUBISHI
ELECTRIC

Preliminary Spec.

Some contents are subject to change without notice.

Keep safety first in your circuit designs!

Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products
better and more reliable, but there is always the possibility that trouble may occur with them.
Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with
appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-
flammable material or (iii) prevention against any malfunction or mishap.

Notes regarding these materials

1.These materials are intended as a reference to assist our customers in the selection of the
Mitsubishi semiconductor product best suited to the customer's application; they do not
convey any license under any intellectual property rights, or any other rights, belonging to
Mitsubishi Electric Corporation or a third party.

2.Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement
of any third-party's rights, originating in the use of any product data, diagrams, charts,
programs, algorithms, or circuit application examples contained in these materials.

3.All information contained in these materials, including product data, diagrams, charts,
programs and algorithms represents information on products at the time of publication of
these materials, and are subject to change by Mitsubishi Electric Corporation without notice
due to product improvements or other reasons. It is therefore recommended that customers
contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
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The information described here may contain technical inaccuracies or typographical errors.
Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other
loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by
various means, including the Mitsubishi Semiconductor home page
(http://www.mitsubishichips.com).

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loss resulting from the information contained herein.

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a device or system that is used under circumstances in which human life is potentially at stake.
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor when considering the use of a product contained herein for any specific
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6.The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or
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Any diversion or reexport contrary to the export control laws and regulations of Japan and/or
the country of destination is prohibited.

8.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for further details on these materials or the products contained therein.

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