MOSEL VITELIC

V29C51000T/V29C51000B
512K BIT (65,536 x 8 BIT)
5 VOLT CMOS FLASH MEMORY

PRELIMINARY

V29C51000T/V29C51000B Rev. 0.5 October 2000

Features

64Kx8-bit Organization

Address Access Time: 45, 70, 90 ns

Single 5V

10% Power Supply

Sector Erase Mode Operation

8KB Boot Block (lockable)

512 bytes per Sector, 128 Sectors
Sector-Erase Cycle Time: 10ms (Max)
Byte-Program Cycle Time: 20

s (Max)

Minimum 10,000 Erase-Program Cycles

Low power dissipation
Active Read Current: 20mA (Typ)
Active Program Current: 30mA (Typ)
Standby Current: 100

A (Max)

Hardware Data Protection

Low V

Program Inhibit Below 3.2V

Self-timed program/erase operations with end-
of-cycle detection
DATA Polling
Toggle Bit

CMOS and TTL Interface

Available in two versions
V29C51000T (Top Boot Block)
V29C51000B (Bottom Boot Block)

Packages:
32-pin Plastic DIP
32-pin TSOP-I
32-pin PLCC

Description

The V29C51000T/V29C51000B is a high speed

65,536 x 8 bit CMOS flash memory. Programming
or erasing the device is done with a single 5 Volt
power supply. The device has separate chip enable
CE, program enable WE, and output enable OE
controls to eliminate bus contention.

The V29C51000T/V29C51000B offers a combi-

nation of features: Boot Block with Sector Erase
Mode. The end of program/erase cycle is detected
by DATA Polling of I/O

or by the Toggle Bit I/O

The V29C51000T/V29C51000B features a

sector erase operation which allows each sector to
be erased and reprogrammed without affecting
data stored in other sectors. The device also
supports full chip erase.

Boot block architecture enables the device to

boot from either the top (V29C51000T) or bottom
(V29C51000B) sector. All inputs and outputs are
CMOS and TTL compatible.

The V29C51000T/V29C51000B is ideal for

applications that require updatable code and data
storage.

Device Usage Chart

Operating

Temperature

Range

Package Outline

Access Time (ns)

Temperature

Mark

C to 70

Blank

MOSEL VITELIC

V29C51000T/V29C51000B

V29C51000T/V29C51000B Rev. 0.5 October 2000

OPERATING VOLTAGE

51: 5V

DEVICE

SPEED

51000-01

000

BOOT BLOCK LOCATION

T: TOP

B: BOTTOM

45: 45ns
70: 70ns
90: 90ns

BLANK (0

C TO 70

P = PDIP

T = TSOP-I

J = PLCC

TEMP.

PKG.

Pin Configurations

N/C

A15

A12

I/O0

I/O1
I/O2

GND

13
14

15
16

32-Pin PDIP

Top View

A14

A13

A11

A10

I/O3

I/O4

I/O5

I/O6

I/O7

51001-02

Pin Names

Address Inputs

I/O

Data Input/Output

Chip Enable

Output Enable

Program Enable

10% Power Supply

GND

Ground

NC No

Connect

I/O

51001-03

I/O

GND

I/O

32 Pin PLCC

Top View

15 16 17 18 19 20

32 31 30

A11

A9
A8

A13
A14

VCC

N/C
N/C

A15
A12

A7
A6
A5
A4

1
2
3
4
5
6

8
9
10
11
12
13
14
15
16

29
28
27
26
25

24
23
22
21
20

32-Pin TSOP I

Standard Pinout

Top View

OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1

I/O0

19
18
17

51001-04

MOSEL VITELIC

V29C51000T/V29C51000B

V29C51000T/V29C51000B Rev. 0.5 October 2000

Functional Block Diagram

Capacitance

(1,2)

NOTE:

Capacitance is sampled and not 100% tested.

= 25

C, V

= 5V

10%, f = 1 MHz.

Latch Up Characteristics

(1)

NOTE:

Includes all pins except V

. Test conditions: V

= 5V, one pin at a time.

AC Test Load

Symbol

Parameter

Test mSetup

Typ.

Max.

Units

Input Capacitance

= 0

OUT

Output Capacitance

OUT

= 0

IN2

Control Pin Capacitance

= 0

Parameter Min.

Max.

Unit

Input Voltage with Respect to GND on A

, OE

-1

+13

Input Voltage with Respect to GND on I/O, address or control pins

-1

+ 1

Current

-100

+100

Address buffer & latches

51001-05

I/O Buffer & Data Latches

I/O

Y-Decoder

65,536 Bit

Memory Cell Array

X-Decoder

Control Logic

51001-06

IN3064 or Equivalent

IN3064

or Equivalent

2.7 k

6.2 k

+5.0 V

IN3064 or Equivalent

= 100 pF

Device Under

Test

MOSEL VITELIC

V29C51000T/V29C51000B

V29C51000T/V29C51000B Rev. 0.5 October 2000

Absolute Maximum Ratings

(1)

NOTE:

Stress greater than those listed unders "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

No more than one output maybe shorted at a time and not exceeding one second long.

DC Electrical Characteristics

(over the commercial operating range)

Symbol

Parameter

Commercial

Unit

Input Voltage (input or I/O pins)

-2 to +7

Input Voltage (A

pin, OE)

-2 to +13

Power Supply Voltage

-0.5 to +5.5

STG

Storage Temerpature (Plastic)

-65 to +125

OPR

Operating Temperature

0 to +70

OUT

Short Circuit Current

(2)

200 (Max.)

Parameter
Name

Parameter

Test Conditions

Min.

Max.

Unit

Input LOW Voltage

= V

Min.

0.8

Input HIGH Voltage

= V

Max.

Input Leakage Current

= GND to V

, V

= V

Max.

Output Leakage Current

OUT

= GND to V

, V

= V

Max.

Output LOW Voltage

= V

Min., I

= 2.1mA

0.4

Output HIGH Voltage

= V

Min, I

= -400

2.4

CC1

Read Current

CE = OE = V

, WE = V

, all I/Os open,

Address input = V

, at f = 1/t

Min.,

= V

Max.

CC2

Program Current

CE = WE = VIL, OE = V

, V

= V

Max.

TTL Standby Current

CE = OE = WE = V

, V

= V

Max.

SB1

CMOS Standby Current

CE = OE = WE = V

0.3V, V

= V

Max.

100

Device ID Voltage for A

CE = OE = V

, WE = V

11.5

12.5

Device ID Current for A

CE = OE = V

, WE = V

, A9 = V

Max.

MOSEL VITELIC

V29C51000T/V29C51000B

V29C51000T/V29C51000B Rev. 0.5 October 2000

AC Electrical Characteristics

(over all temperature ranges)

Read Cycle

Program (Erase/Program) Cycle

Parameter

Name

Parameter

-45

-70

-90

Unit

Min.

Max.

Min.

Max.

Min.

Max.

Read Cycle Time

Address Access Time

ACS

Chip Enable Access Time

Output Enable Access Time

CLZ

CE Low to Output Active

OLZ

OE Low to Output Active

Output Enable or Chip Disable to Output in
High Z

Output Hold from Address Change

Parameter

Name

Parameter

-45

-70

-90

Unit

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.

Program Cycle Time

Address Setup Time

Address Hold Time

CE Setup Time

CE Hold Time

OES

OE Setup Time

OEH

OE High Hold Time

WE Pulse Width

WPH

WE Pulse Width High

Data Setup Time

Data Hold Time

WHWH1

Programming Cycle

WHWH2

Sector Erase Cycle

WHWH3

Chip Erase Cycle

500

MOSEL VITELIC

V29C51000T/V29C51000B

V29C51000T/V29C51000B Rev. 0.5 October 2000

Waveforms of Read Cycle

Waveforms of WE Controlled-Program Cycle

NOTES:
1.

I/O

: The output is the complement of the data written to the device.

PA: The address of the memory location to be programmed.

PD: The data at the byte address to be programmed.

CLZ

OLZ

ADDRESS

I/O

VALID DATA OUT

HIGH-Z

51000-07

HIGH-Z

5555H

WHWH1

WPH

OES

OUT

I/O

(1)

(3)

A0H

51000-08

ADDRESS

I/O

3rd bus cycle

(2)

MOSEL VITELIC

V29C51000T/V29C51000B

V29C51000T/V29C51000B Rev. 0.5 October 2000

Waveforms of CE Controlled-Program Cycle

Waveforms of Erase Cycle

(1)

NOTES:
1.

PA: The address of the memory location to be programmed.

PD: The data at the byte address to be programmed.

SA: The sector address for Sector Erase. Address = don't care for Chip Erase.

WHWH1

WPH

OES

OUT

I/O7

(2)

A0H

51000-09

ADDRESS

5555H

(1)

I/O

WPH

ADDRESS

I/O

5555H

2AAAH

AAH

55H

80H

AAH

55H

30H

10H for

Chip Erase

51000-10

V29C51000T/V29C51000B Rev. 0.5 October 2000

MOSEL VITELIC

V29C51000T/V29C51000B

Functional Description

The V29C51000T/V29C51000B consists of 256

equally-sized sectors of 512 bytes each. The 8 KB
lockable Boot Block is intended for storage of the
system BIOS boot code. The boot code is the first
piece of code executed each time the system is
powered on or rebooted.

The V29C51000 is available in two versions: the

V29C51000T with the Boot Block address starting
from E000H to FFFFH, and the V29C51000B with
the Boot Block address starting from 0000H to
FFFFH.

Read Cycle

A read cycle is performed by holding both CE

and OE signals LOW. Data Out becomes valid only
when these conditions are met. During a read cycle
WE must be HIGH prior to CE and OE going LOW.
WE must remain HIGH during the read operation
for the read to complete (see Table 1).

Output Disable

Returning OE or CE HIGH, whichever occurs first

will terminate the read operation and place the l/O
pins in the HIGH-Z state.

Standby

The device will enter standby mode when the CE

signal is HIGH. The l/O pins are placed in the
HIGH-Z, independent of the OE signal.

Command Sequence

T h e V 2 9 C 5 1 0 0 0 T / V 2 9 C 5 1 0 0 0 B d o e s n o t

provide the "reset" feature to return the chip to its
normal state when an incomplete command
sequence or an interruption has happened. In this
case, normal operation (Read Mode) can be
restored by issuing a "non-existent" command
sequence, for example Address: 5555H, Data FFH.

Byte Program Cycle

The V29C51000T/V29C51000B is programmed

on a byte-by-byte basis. The byte program
operation is initiated by using a specific four-bus-
cycle sequence: two unlock program cycles, a
program setup command and program data
program cycles (see Table 2).

During the byte program cycle, addresses are

latched on the falling edge of either CE or WE,
whichever is last. Data is latched on the rising edge
of CE or WE, whichever is first. The byte program
cycle can be CE controlled or WE controlled.

Sector Erase Cycle

The V29C51000T/V29C51000B features a

sector erase operation which allows each sector to
be erased and reprogrammed without affecting
data stored in other sectors. Sector erase operation
is initiated by using a specific six-bus-cycle
sequence: Two unlock program cycles, a setup
command, two additional unlock program cycles,
and the sector erase command (see Table 2). A
sector must be first erased before it can be
reprogrammed. While in the internal erase mode,

8KB Boot Block

512

8KB Boot Block

V29C51000T

V29C51000B

FFFFH

E000H

0000H

1FFFH

51000-13

0000H

8KB Boot Block = 16 Sectors

Table 1. Operation Modes Decoding

NOTES:
1.

X = Don't Care, V

= HIGH, V

= LOW.

PD: The data at the byte address to be programmed.

Decoding Mode

I/O

Read

READ

Program

Standby

HIGH-Z

Autoselect Device ID

CODE

Autoselect Manufacture ID

CODE

Output Disable

HIGH-Z

MOSEL VITELIC

V29C51000T/V29C51000B

V29C51000T/V29C51000B Rev. 0.5 October 2000

the device ignores any program attempt into the
device. The internal erase completion can be
determined via DATA polling or toggle bit.

The V29C51000T/V29C51000B is shipped with

pre-erased sectors (all bits = 1).

Chip Erase Cycle

The V29C51000T/V29C51000B features a chip-

erase operation. The chip erase operation is
i n i t i a t e d b y u s i n g a s p e c i f i c s i x - b u s - c y c l e
sequence: two unlock program cycles, a setup
command, two additional unlock program cycles,
and the chip erase command (see Table 2).

T h e c h i p e r a s e o p e r a t i o n i s p e r f o r m e d

sequentially, one sector at a time. When the
automated on chip erase algorithm is requested
with the chip erase command sequence, the device
automatically programs and verifies the entire
memory array for an all zero pattern prior to erasure

The automatic erase begins on the rising edge of

the last WE or CE pulse in the command sequence
and terminates when the data on DQ7 is "1".

Program Cycle Status Detection

There are two methods for determining the state

o f t h e V 2 9 C 5 1 0 0 0 T / V 2 9 C 5 1 0 0 0 B d u r i n g a
program (erase/program) cycle: DATA Polling
(I/O

) and Toggle Bit (I/O

DATA Polling (I/O

)

The V29C51000T/V29C51000B features DATA

polling to indicate the end of a program cycle.
When the device is in the program cycle, any

attempt to read the device will received the
complement of the loaded data on I/O

. Once the

program cycle is completed, I/O

will show true

data, and the device is then ready for the next
cycle.

Toggle Bit (I/O

)

The V29C51000T/V29C51000B also features

another method for determining the end of a
program cycle. When the device is in the program
cycle, any attempt to read the device will result in
l/O

toggling between 1 and 0. Once the program is

completed, the toggling will stop. The device is then
ready for the next operation. Examining the toggle
bit may begin at any time during a program cycle.

Boot Block Protection

T h e V 2 9 C 5 1 0 0 0 T / V 2 9 C 5 1 0 0 0 B f e a t u r e s

hardware Boot Block Protection. This feature will
prevent erasing/programming of data in the Boot
Block once the feature is enabled (see Table 3).
The device is shipped with the Boot Block
unprotected.

Autoselect

The V29C51000T/V29C51000B features an

Autoselect mode to identify the Boot Block
(protected/unprotected), the Device (Top/Bottom),
and the manufacturer ID.

To get to the Autoselect mode, a high voltage

) must be applied to the A

pin. Once the A

signal is returned to LOW or HIGH, the device will
return to the previous mode.

Table 2. Command Codes

NOTES:
1.

Top Boot Sector

Bottom Boot Sector

PA: The address of the memory location to be programmed.

PD: The data at the byte address to be programmed.

Command
Sequence

First Bus
Program Cycle

Second Bus
Program Cycle

Third Bus
Program Cycle

Fourth Bus
Program Cycle

Fifth Bus
Program Cycle

Six Bus
Program Cycle

Address

Data

Address

Data

Address

Data

Address

Data

Address

Data

Address

Data

Read

XXXXH

F0H

Read

5555H

AAH

2AAAH

55H

5555H

F0H

Autoselect

5555H

AAH

2AAAH

55H

5555H

90H

00H

40H

01H

00H

(1)

A0H

(2)

Byte
Program

5555H

AAH

2AAAH

55H

5555H

A0H

PD(4)

Chip Erase

5555H

AAH

2AAAH

55H

5555H

80H

5555H

AAH

2AAAH

55H

5555H

10H

Sector Erase

5555H

AAH

2AAAH

55H

5555H

80H

5555H

AAH

2AAAH

55H

PA(3)

30H

V29C51000T/V29C51000B Rev. 0.5 October 2000

MOSEL VITELIC

V29C51000T/V29C51000B

Boot Block Detection

In Autoselect mode, performing a read at

address 3CXX2H or address 0CXX2H will indicate
if the Top Boot Block sector or the Bottom Boot
Block sector is locked out. If the data is 01H, the
Top/Bottom Boot Block is protected. If the data is
00H, the Top/Bottom Boot Block is unprotected.
(see Table 3.)

Device ID

In Autoselect mode, performing a read at

address XXXXH will determine whether the device
is a Top Boot Block device or a Bottom Boot Block
device. If the data is 00H, the device is a Top Boot
Block. If the data is A0H, the device is a Bottom
Boot Block device (see Table 3).

In addition, the device ID can also be read via the

command register when the device is erased or
programmed in a system without applying high
voltage to the A

pin. When A

is HIGH, the device

ID is presented at the outputs.

Manufacturer ID

In Autoselect mode, performing a read at

address. XXXX0H will determine the manufacturer
ID. 40H is the manufacturer code for Mosel Vitelic
Flash.

In addition the manufacturer ID can also be read

via the command register when the device is
erased or programmed in a system without
applying high voltage to the A

pin. when A

LOW, the manufacturer ID is presented at the
outputs.

Hardware Data Protection

Sense Protection: the program operation is

inhibited when VCC is less than 2.5V.

Noise Protection: a CE or WE pulse of less than

5ns will not initiate a program cycle.

Program Inhibit Protection: holding any one of

OE LOW, CE HIGH or WE HIGH inhibits a program
cycle.

Table 3. Autoselect Decoding

NOTE:
1.

X = Don't Care, V

= HIGH, V

= LOW.

Decoding Mode

Boot Block

Address

Data I/O

I/O

Boot Block Protection

Top

01H: protected

Bottom

00H: unprotected

Device ID

Top

01H

Bottom

00H

Manufacture ID

A0H

MOSEL VITELIC

WORLDWIDE OFFICES

V29C51000T/V29C51000B

MOSEL VITELIC

3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461

The information in this document is subject to change without
notice.

MOSEL VITELIC makes no commitment to update or keep cur-
rent the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.

MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applica-
tions. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liabil-
ity for consequential or incidental arising from any use of its prod-
ucts. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.

10/00
Printed in U.S.A.

U.S. SALES OFFICES

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FAX: 408-433-0952

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: V29C51000B-90P