MOSEL VITELIC

V436416S04V(C)TG-10PC
3.3 VOLT 16M x 64 HIGH PERFORMANCE
PC100 UNBUFFERED SDRAM MODULE

PRELIMINARY

V436416S04V(C)TG-10PC Rev. 1.2 June 2000

Features

168 Pin Unbuffered 16,777,216 x 64 bit
Oganization SDRAM Modules

Utilizes High Performance 8M x 8 SDRAM in
TSOPII-54 Packages

Fully PC Board Layout Compatible to INTEL'S
Rev 1.0 Module Specification

Single +3.3V (

0.3V) Power Supply

Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)

Auto Refresh (CBR) and Self Refresh

All Inputs, Outputs are LVTTL Compatible

4096 Refresh Cycles every 64 ms

Serial Present Detect (SPD)

Description

The V436416S04V(C)TG-10PC memory module

is organized 16,777,216 x 64 bits in a 168 pin dual
in line memory module (DIMM). The 16M x 64 un-
buffered DIMM uses 16 Mosel-Vitelic 8M x 8
SDRAM. The x64 modules are ideal for use in high
performance computer systems where increased
memory density and fast access times are required.

SDRAM Performance

Module Frequency vs AC Parameter

Key Component Timing Parameters

-8PC

Units

Clock Frequency (max.)

125

MHz

Clock Access Time CAS
Latency = 3

Latency = 2

Frequency

(CAS Latency)

RCD

Unit

V436416S04V(C)TG-10PC

100 MHz (PC)

CLK

V436416S04V(C)TG-10PC-01

V436416S04V(C)TG-10PC Rev. 1.2 June 2000

MOSEL VITELIC

V436416S04V(C)TG-10PC

Pin Configurations (Front Side/Back Side)

Notes:

* These pins are not used in this module.

Pin

Front

Pin

Front

Pin

Front

Pin

Back

Pin

Back

Pin

Back

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

VSS

I/O1
I/O2
I/O3
I/O4

VCC

I/O5
I/O6
I/O7
I/O8
I/O9

VSS

I/O10
I/O11
I/O12
I/O13
I/O14

VCC

I/O15
I/O16

CBO*

CB1*

VSS

NC
NC

VCC

DQM0

29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56

DQM1

CS0

VSS

A0
A2
A4
A6
A8

A10(AP)

BA1

VCC
VCC

CLK0

VSS

CS2

DQM2
DQM3

VCC

NC
NC

CB2*
CB3*

VSS

I/O17
I/O18

57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84

I/O19
I/O20

VCC

I/O21

NC
DU

CKE1

VSS

I/O22
I/O23
I/O24

VSS

I/O25
I/O26
I/O27
I/O28

VCC

I/O29
I/O30
I/O31
I/O32

VSS

CLK2

SDA

SCL

VCC

85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

100
101
102
103
104
105
106
107
108
109
110
111
112

VSS

I/O33
I/O34
I/O35
I/O36

VCC

I/O37
I/O38
I/O39
I/O40
I/O41

VSS

I/O42
I/O43
I/O44
I/O45
I/O46

VCC

I/O47
I/O48

CB4*
CB5*

VSS

NC
NC

VCC
CAS

DQM4

113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140

DQM5

CS1

RAS
VSS

A1
A3
A5
A7
A9

BA0

A11

VCC

CLK1

VSS

CKE0

CS3

DQM6
DQM7

VCC

NC
NC

CB6*
CB7*

VSS

I/O49
I/O50

141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168

I/O51
I/O52

VCC

I/O53

NC
DU
NC

VSS

I/O54
I/O55
I/O56

VSS

I/O57
I/O58
I/O59
I/O60

VCC

I/O61
I/O62
I/O63
I/O64

VSS

CLK3

SA0
SA1
SA2

VCC

Pin Names

A0A11

Address Inputs

I/O1I/O64

Data Inputs/Outputs

RAS

Row Address Strobe

CAS

Column Address Strobe

Read/Write Input

BA0, BA1

Bank Selects

CKE0, CKE1

Clock Enable

CS0CS3

Chip Select

CLK0CLK3

Clock Input

DQM0DQM7

Data Mask

VCC

Power (+3.3 Volts)

VSS

Ground

SCL

Clock for Presence Detect

SDA

Serial Data OUT for Presence
Detect

SA0A2

Serial Data IN for Presence
Detect

CB0CB7

Check Bits (x72 Organization)

No Connection

Don't Use

MOSEL VITELIC

V436416S04V(C)TG-10PC

V436416S04V(C)TG-10PC Rev. 1.2 June 2000

Module Part Number Information

Block Diagram

SDRAM

3.3V

V436416S04V(C)TG-10PC-02

MOSEL-VITELIC

MANUFACTURED

168 PIN UNBUFFERED

DIMM X 8 COMPONENT

REFRESH RATE 4K

DEPTH

4 BANKS

TSOP

WIDTH

LVTTL

GOLD

10PC

-10PC PC100 2-2-2

COMPONENT REVISION
LEVEL
BLANK = B REV.
C = C REV.

DQM0

I/O1I/O8

CS0

CS1

CS3

DQM4

I/O33I/O40

DQM1

I/O9I/O16

DQM5

I/O41I/O48

DQM2

I/O17I/O24

CS2

DQM6

I/O49I/O56

DQM3

I/O25I/O32

DQM7

I/O57I/O64

V436416S04V(C)TG-10PC-03

D0-D15

D0-D7

A11-A0, BA0, BA1

10K

RAS, CAS, WE

CKE0

CKE1

D0-D7

C0-C31

D9-D15

SA0
SA1
SA2

SCL

SA0
SA1
SA2

SCL

SDA

PROM SPD (256 WORD X 8 BIT)

47K

CLOCK WIRING

16M X 64

CLK0

4 SDRAM +3.3pF

CLK1

4 SDRAM +3.3pF

CLK2

4 SDRAM +3.3pF

CLK3

4 SDRAM +3.3pF

DQM
I/O1I/O8

DQM
I/O1I/O8 D8

DQM
I/O1I/O8 D9

DQM
I/O1I/O8 D10

DQM
I/O1I/O8 D11

DQM
I/O1I/O8

DQM
I/O1I/O8 D12

DQM
I/O1I/O8 D13

DQM
I/O1I/O8 D14

DQM
I/O1I/O8 D15

V436416S04V(C)TG-10PC Rev. 1.2 June 2000

MOSEL VITELIC

V436416S04V(C)TG-10PC

Serial Presence Detect Information

A serial presence detect storage device -

PROM - is assembled onto the module. Informa-

tion about the module configuration, speed, etc. is

written into the E

PROM device during module pro-

duction using a serial presence detect protocol (I

synchronous 2-wire bus)

SPD-Table:

Byte

Number

Function Described

SPD Entry Value

Hex Value

100 MHz

-10PC

Number of SPD bytes

128

Total bytes in Serial PD

256

Memory Type

SDRAM

Number of Row Addresses (without BS bits)

Number of Column Addresses (for x8 SDRAM)

Number of DIMM Banks

Module Data Width

Module Data Width (continued)

Module Interface Levels

LVTTL

SDRAM Cycle Time at CL=3

10.0 ns

SDRAM Access Time from Clock at CL=3

6.0 ns

Dimm Config (Error Det/Corr.)

none

Refresh Rate/Type

Self-Refresh, 15.6

SDRAM width, Primary

Error Checking SDRAM Data Width

n/a / x8

Minimum Clock Delay from Back to Back
Random Column Address

ccd

= 1 CLK

Burst Length Supported

1, 2, 4, 8 & full Page

Number of SDRAM Banks

Supported CAS Latencies

CL = 2 & 3

CS Latencies

CS Latency = 0

WE Latencies

WL = 0

SDRAM DIMM Module Attributes

Non Buffered/Non Reg.

SDRAM Device Attributes: General

Vcc tol

10%

Minimum Clock Cycle Time at CAS Latency = 2

10.0 ns

Maximum Data Access Time from Clock for CL = 2

6.0 ns

Minimum Clock Cycle Time at CL = 1

Not Supported

Maximum Data Access Time from Clock at CL = 1

Not Supported

Minimum Row Precharge Time t

20 ns

Minimum Row Active to Row Active Delay t

RRD

16 ns

Minimum RAS to CAS Delay t

RCD

20 ns

MOSEL VITELIC

V436416S04V(C)TG-10PC

DC Characteristics

= 0

C to 70

C; V

= 0 V; V

, V

DDQ

= 3.3V

0.3V

Minimum RAS Pulse Width t

RAS

45 ns

Module Bank Density (Per Bank)

64 MByte

SDRAM Input Setup Time

2 ns

SDRAM Input Hold Time

1 ns

SDRAM Data Input Setup Time

2 ns

SDRAM Data Input Hold Time

1 ns

36-61

Superset Information (May be used in Future)

SPD Revision

Revision 1.2

Checksum for Bytes 0 - 62

64-125

Manufacturers's Information (Optional)
(FFh if not used)

126

Max. Frequency Specification

100 MHz

127

100 MHz Support Details

128+

Unused Storage Location

Symbol

Parameter

Limit Values

Unit

Min.

Max.

Input High Voltage

2.0

+0.3

Input Low Voltage

0.5

0.8

Output High Voltage (I

OUT

= 2.0 mA)

2.4

Output Low Voltage (I

OUT

= 2.0 mA)

0.4

I(L)

Input Leakage Current, any input
(0 V < V

< 3.6 V, all other inputs = 0V)

O(L)

Output leakage current
(DQ is disabled, 0V < V

OUT

< V

)

SPD-Table: (Continued)

Byte

Number

Function Described

SPD Entry Value

Hex Value

100 MHz

-10PC

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