MOSEL VITELIC
1
V436532Z04V
256MB 144-PIN UNBUFFERED SDRAM
SODIMM, 32M X 64 3.3VOLT
PRELIMINARY
V436532Z04V Rev.1.2 November 2001
Features
s
JEDEC-standard 144 pin, Small-Outline, Dual in
line Memory Module (SODIMM)
s
Serial Presence Detect with E
2
PROM
s
Nonbuffered
s
Fully Synchronous, All Signals Registered on
Positive Edge of System Clock
s
Single +3.3V ( 0.3V) Power Supply
s
All Device Pins are LVTTL Compatible
s
4096 Refresh Cycles every 64 ms
s
Self-Refresh Mode
s
Internal Pipelined Operation; Column Address
can be changed every System Clock
s
Programmable Burst Lengths: 1, 2, 4, 8
s
Auto Precharge and Piecharge all Banks by A10
s
Data Mask Function by DQM
s
Mode Register Set Programming
s
Programmable (CAS Latency: 2, 3 Clocks)
s
SOC component package
Description
The V436532Z04V memory module is organized
33,554,432x 64 bits in a 144 pin SODIMM. The 32M
x 64 memory module uses 16 Mosel-Vitelic 16M x 8
SDRAM. The x64 modules are ideal for use in high
performance computer systems where increased
memory density and fast access times are required.
Part Number
Speed
Grade
Configuration
V436532Z04VASG-75
-75, CL=3
(133 MHz)
32M x 64
V436532Z04VASG-75PC
-75PC, CL=2,3
(133 MHz)
32M x 64
V436532Z04VASG-10PC
-10PC, CL=2
(100 MHz)
32M x 64
1
Pin 2 on Backside
Pin 144 on Backside
59
61
143
32M x 8
32M x 8
32M x 8
32M x 8
2
V436532Z04V Rev. 1.2 November 2001
MOSEL VITELIC
V436532Z04V
Pin Configurations (Front Side/Back Side)
Note:
1. RAS, CAS, WE CASx, CSx are active low signals.
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VSS
VSS
DQ0
DQ32
DQ1
DQ33
DQ2
DQ34
DQ3
DQ35
VDD
VDD
DQ4
DQ36
DQ5
DQ37
DQ6
DQ38
DQ7
DQ39
VSS
VSS
DQMB0
DQMB4
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
DQMB1
DQMB5
VDD
VDD
A0
A3
A1
A4
A2
A5
VSS
VSS
DQ8
DQ40
DQ9
DQ41
DQ10
DQ42
DQ11
DQ43
VDD
VDD
DQ12
DQ44
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
DQ13
DQ45
DQ14
DQ46
DQ15
DQ47
VSS
VSS
NC
NC
NC
NC
CLK0
CKE0
VDD
VDD
RAS
CAS
WE
CKE1
CS0
NC
CS1
A12
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
NC
CLK1
VSS
VSS
NC
NC
NC
NC
VDD
VDD
DQ16
DQ48
DQ17
DQ49
DQ18
DQ50
DQ19
DQ51
VSS
VSS
DQ20
DQ52
DQ21
DQ53
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
DQ22
DQ54
DQ23
DQ55
VDD
VDD
A6
A7
A8
BA0
VSS
VSS
A9
BA1
A10
A11
VDD
VDD
DQMB2
DQMB6
DQMB3
DQMB7
VSS
VSS
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
DQ24
DQ56
DQ25
DQ57
DQ26
DQ58
DQ27
DQ59
VDD
VDD
DQ28
DQ60
DQ29
DQ61
DQ30
DQ62
DQ31
DQ63
VSS
VSS
SDA
SCL
VDD
VDD
Pin Names
A0A11, BA0, BA1
Address, Bank Select
DQ0DQ63
Data Inputs/Outputs
RAS
Row Address Strobes
CAS
Column Address Strobes
WE
Write Enable
CS0, CS1
Chip Select
DQMB0DQMB7
Output Enable
CKE0, CKE1
Clock Enable
CLK0, CLK1
Clock
SDA
Serial Input/Output
SCL
Serial Clock
VDD
Power Supply
VSS
Ground
NC
No Connect (Open)
MOSEL VITELIC
V436532Z04V
3
V436532Z04V Rev. 1.2 November 2001
Part Number Information
V
4
3
65
32
Z 0
4
V
A
S
G - XX
SDRAM
3.3V
WIDTH
DEPTH
144 PIN SODIMM
X8 COMPONENT
REFRESH
RATE 4K
4 BANKS
LVTTL
COMPONENT
REV LEVEL
COMPONENT
PACKAGE, S=SOC
LEAD FINISH
G = GOLD
SPEED
75PC = PC133 CL2,3
MOSEL VITELIC
MANUFACTURED
75
= PC133 CL3
10PC = PC100 CL2
Block Diagram
DQM0
I/O1I/O8
CS0
10
10
10
10
CS1
CS3
CS
DQM4
I/O33I/O40
DQM1
I/O9I/O16
DQM5
I/O41I/O48
DQM2
I/O17I/O24
CS2
10
10
10
10
DQM6
I/O49I/O56
DQM3
I/O25I/O32
DQM7
I/O57I/O64
D0-D15
D0-D15
D0-D15
D0-D7
A11-A0, BA0, BA1
V
DD
V
CC
10K
RAS, CAS, WE
CKE0
CKE1
D0-D7
C0-C31
D9-D15
V
SS
SA0
SA1
SA2
SCL
SA0
SA1
SA2
SCL
SDA
WP
E
2
PROM SPD (256 WORD X 8 BIT)
47K
CLOCK WIRING
32M X 64
CLK0
4 SDRAM +3.3pF
CLK1
4 SDRAM +3.3pF
CLK2
4 SDRAM +3.3pF
CLK3
4 SDRAM +3.3pF
DQM
I/O1I/O8
D0
DQM
I/O1I/O8
D1
DQM
I/O1I/O8
D2
DQM
I/O1I/O8
D3
CS
CS
CS
CS
DQM
I/O1I/O8 D8
DQM
I/O1I/O8 D9
DQM
I/O1I/O8 D10
DQM
I/O1I/O8 D11
CS
CS
CS
CS
DQM
I/O1I/O8
D4
DQM
I/O1I/O8
D5
DQM
I/O1I/O8
D6
DQM
I/O1I/O8
D7
CS
CS
CS
DQM
I/O1I/O8 D12
DQM
I/O1I/O8 D13
DQM
I/O1I/O8 D14
DQM
I/O1I/O8 D15
CS
CS
CS
CS
8
8
CS0
CS0
CS1
CS1
4
V436532Z04V Rev. 1.2 November 2001
MOSEL VITELIC
V436532Z04V
Block Diagram
Serial Presence Detect Information
A serial presence detect storage device - E
2
PROM -
is assembled onto the module. Information about the
module configuration, speed, etc. is written into the
E
2
PROM device during module production using a se-
rial presence detect protocol (I
2
C synchronous 2-wire
bus)
SPD-Table for modules:
Byte Num-
ber
Function Described
SPD Entry Value
Hex Value
-75PC
-75
-10PC
0
Number of SPD bytes
128
80
80
80
1
Total bytes in Serial PD
256
08
08
08
2
Memory Type
SDRAM
04
04
04
3
Number of Row Addresses (without BS bits)
12
0C
0C
0C
4
Number of Column Addresses ( x8 SDRAM)
10
0A
0A
0A
5
Number of DIMM Banks
2
02
02
02
6
Module Data Width
64
40
40
40
7
Module Data Width (continued)
0
00
00
00
8
Module Interface Levels
LVTTL
01
01
01
9
SDRAM Cycle Time at CL=3
7.5 ns/10.0 ns
75
75
A0
10
SDRAM Access Time from Clock at CL=3
5.4 ns/6.0ns
54
54
60
11
Dimm Config (Error Det/Corr.)
none
00
00
00
12
Refresh Rate/Type
Self-Refresh,15.6
s
80
80
80
13
SDRAM width, Primary
x8
08
08
08
14
Error Checking SDRAM Data Width
n/a / x8
00
00
00
15
Minimum Clock Delay from Back to Back Ran-
dom Column Address
t
ccd
= 1 CLK
01
01
01
16
Burst Length Supported
1, 2, 4 & 8
0F
0F
0F
17
Number of SDRAM Banks
4
04
04
04
18
Supported CAS Latencies
CL = 2 / 3
06
06
06
19
CS Latencies
CS Latency = 0
01
01
01
20
WE Latencies
WL = 0
01
01
01
21
SDRAM DIMM Module Attributes
Non Buffered/Non Reg.
00
00
00
22
SDRAM Device Attributes: General
Vcc tol 10%
0E
0E
0E
23
Minimum Clock Cycle Time at CAS Latency = 2
7.5 ns/10.0 ns
75
A0
A0
24
Maximum Data Access Time from Clock for CL
= 2
5.4ns/6.0ns
54
60
60
25
Minimum Clock Cycle Time at CL = 1
Not Supported
00
00
00
26
Maximum Data Access Time from Clock at CL =
1
Not Supported
00
00
00
27
Minimum Row Precharge Time
15 ns / 20 ns
0F
14
14
MOSEL VITELIC
V436532Z04V
5
V436532Z04V Rev. 1.2 November 2001
28
Minimum Row Active to Row Active Delay t
RRD
14 ns/15 ns
0E
0F
0F
29
Minimum RAS to CAS Delay t
RCD
15 ns/20 ns
0F
14
14
30
Minimum RAS Pulse Width t
RAS
42 ns/45 ns
2A
2D
2D
31
Module Bank Density (Per Bank)
128Mbyte
20
20
20
32
SDRAM Input Setup Time
1.5 ns
15
15
15
33
SDRAM Input Hold Time
0.8 ns
08
08
08
34
SDRAM Data Input Setup Time
1.5 ns
15
15
15
35
SDRAM Data Input Hold Time
0.8 ns
08
08
08
62-61
Superset Information (May be used in Future)
00
00
00
62
SPD Revision
Revision 2 / 1.2
02
02
12
63
Checksum for Bytes 0 - 62
DB
20
67
64
Manufacturer's JEDEC ID Code
Mosel Vitelic
40
40
40
65-71
Manufacturer's JEDEC ID Code (cont.)
00
00
00
72
Manufacturing Location
1 = US, 2 = Taiwan
73-90
Module Part Number (ASCII)
V436532Z04V
91-92
PCB Identification Code
Current PCB Revision
93
Assembly Manufacturing Date (Year)
Binary Coded year (BCD)
94
Assembly Manufacturing Date (Week)
Binary Coded week (BCD)
95-98
Assembly Serial Number
byte 95 = LSB, byte 98 =
MSB
99-125
Reserved
00
00
00
126
Intel Specification for Frequency
64
64
64
127
Supported Frequency
128+
Unused Storage Location
00
00
00
SPD-Table for modules: (Continued)
Byte Num-
ber
Function Described
SPD Entry Value
Hex Value
-75PC
-75
-10PC
6
V436532Z04V Rev. 1.2 November 2001
MOSEL VITELIC
V436532Z04V
DC Characteristics
T
A
= 0
C to 70
C; V
SS
= 0 V; V
DD
, V
DDQ
= 3.3V
0.3V
Capacitance
T
A
= 0
C to 70
C; V
DD
= 3.3V
0.3V, f = 1 MHz
Absolute Maximum Ratings
Symbol
Parameter
Limit Values
Unit
Min.
Max.
V
IH
Input High Voltage
2.0
V
CC
+0.3
V
V
IL
Input Low Voltage
0.5
0.8
V
V
OH
Output High Voltage (I
OUT
= 4.0 mA)
2.4
--
V
V
OL
Output Low Voltage (I
OUT
= 4.0 mA)
--
0.4
V
I
I(L)
Input Leakage Current, any input
(0 V < V
IN
< 3.6 V, all other inputs = 0V)
10
10
A
I
O(L)
Output leakage current
(DQ is disabled, 0V < V
OUT
< V
CC
)
10
10
A
Symbol
Parameter
Limit Values (Max.)
Unit
C
I1
Input Capacitance (A0 to A11, RAS, CAS, WE)
40
pF
C
I2
Input Capacitance (CS0, CSI)
25
pF
C
ICL
Input Capacitance (CLK0-CLK1)
28
pF
C
I3
Input Capacitance (CKE0, CKEI)
20
pF
C
I4
Input Capacitance (DQMB0-DQMB7)
10
pF
C
SC
Input Capacitance (SCL, SA0-2)
8
pF
C
IO
Input/Output Capacitance
18
pF
Parameter
Max.
Units
Voltage on VDD Supply Relative to V
SS
-1 to 4.6
V
Voltage on Input Relative to V
SS
-1 to 4.6
V
Operating Temperature
0 to +70
C
Storage Temperature
-55 to 125
C
Power Dissipation
12
W
MOSEL VITELIC
V436532Z04V
7
V436532Z04V Rev. 1.2 November 2001
Standby and Refresh Currents
1
T
A
= 0
C to 70
C, V
CC
= 3.3V
0.3V
Sym-
bol
Parameter
Test Conditions
75PC/75
10PC
Unit
Note
I
CC
1
Operating Current
Burst length = 4, CL = 3
t
RC
> = t
RC
(min),
t
CK
> = t
CK
(min), IO = 0 mA
2 Bank Interleave Operation
1360
1200
mA
1,2
I
CC
2P
Precharged Standby Current in
Power Down Mode
CKE< = V
IL
(max), t
CK
> = t
CK
(min)
24
24
mA
I
CC
2N
Precharged Standby Current in
Non-Power Down Mode
CKE> = V
IH
(min), t
CK
> = t
CK
(min), In-
put changed once in 3 cycles
360
280
mA
CS = High
I
CC
3P
Active Standby Current in Power
Down Mode
CKE< = V
IL
(max), t
CK
> = t
CK
(min)
160
160
mA
I
CC
3N
Active Standby Current in Non-Pow-
er Down Mode
CKE> = V
IH
(min), t
CK
> = t
CK
(min), In-
put changed one time
440
360
mA
CS = High
I
CC
4
Burst Operating Current
Burst length = Full Page,
t
RC
= Infinite, CL = 3,
t
CK
> = t
CK
(min), IO = 0 mA
2 Banks Activated
880
720
mA
1, 2
I
CC
5
Auto Refresh Current
t
RC
>= t
RC
(min)
4000
3360
mA
1,2
I
CC
6
Self Refresh Current
CKE = <0.2 V
Standard
23
24
mA
1,2
L-Version
12.8
12.8
8
V436532Z04V Rev. 1.2 November 2001
MOSEL VITELIC
V436532Z04V
AC Characteristics
3,4
T
A
= 0 to 70
C; V
SS
= 0V; V
CC
= 3.3V
0.3V, t
T
= 1 ns
#
Symbol Parameter
Limit Values
Unit
Note
-75PC
-75
-10PC
Min.
Max.
Min.
Max.
Min.
Max.
Clock and Clock Enable
1
t
CK
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
7.5
7.5
7.5
10
10
10
ns
ns
2
f
CK
System frequency
CAS Latency = 3
CAS Latency = 2
133
133
133
100
100
100
MHz
MHz
3
t
AC
Clock Access Time
CAS Latency = 3
CAS Latency = 2
5.4
6
5.4
6
6
6
ns
ns
4,5
4
t
CH
Clock High Pulse Width
2.5
2.5
3
ns
6
5
t
CL
Clock Low Pulse Width
2.5
2.5
3
ns
6
6
t
CS
Input Setup time
1.5
1.5
2
ns
7
7
t
CH
Input Hold Time
0.8
0.8
1
ns
7
8
t
CKSP
CKE Setup Time (Power down mode)
2
2
2
ns
8
9
t
CKSR
CKE Setup Time (Self Refresh Exit)
8
8
8
ns
9
10
t
T
Transition time (rise and fall)
1
1
1
ns
Common Parameters
11
t
RCD
RAS to CAS delay
15
20
20
ns
12
t
RC
Cycle Time
70
120k
70
120k
70
120k
ns
13
t
RAS
Active Command Period
42
45
45
ns
14
t
RP
Precharge Time
15
20
20
ns
15
t
RRD
Bank to Bank Delay Time
14
15
20
ns
16
t
CCD
CAS to CAS delay time
(same bank)
1
1
1
CLK
Refresh Cycle
17
t
SREX
Self Refresh Exit Time
10
10
10
ns
9
18
t
REF
Refresh Period (4096cycles)
64
64
64
ms
8
Read Cycle
19
t
OH
Data Out Hold Time
3
3
3
ns
4
20
t
LZ
Data Out to Low Impedance Time
0
0
0
ns
21
t
HZ
Data Out to High Impedance Time
3
7.5
3
7.5
3
8
ns
10
22
t
DQZ
DQM Data Out Disable Latency
2
2
2
CLK
Write Cycle
23
t
DPL
Data input to Precharge (write recovery)
1
1
1
CLK
24
t
DAL
Data In to Active/refresh
5
5
5
CLK
11
25
t
DQW
DQM Write Mask Latency
0
0
0
CLK
MOSEL VITELIC
V436532Z04V
9
V436532Z04V Rev. 1.2 November 2001
Notes:
1.
The specified values are valid when addresses are changed no more than once during t
CK
(min.) and when No
Operation commands are registered on every rising clock edge during t
RC
(min). Values are shown per module
bank.
2.
The specified values are valid when data inputs (DQ's) are stable during t
RC
(min.).
3.
All AC characteristics are shown for device level.
An initial pause of 100
s is required after power-up, then a Precharge All Banks command must be given followed
by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin.
4.
AC timing tests have V
IL
= 0.4V and V
IH
= 2.4V with the timing referenced to the 1.4V crossover point. The transition
time is measured between V
IH
and V
IL
. All AC measurements assume t
T
= 1 ns with the AC output load circuit
shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with
a input signal of 1V / ns edge rate between 0.8V and 2.0V.
5.
If clock rising time is longer than 1 ns, a time (t
T
/2 -0.5) ns has to be added to this parameter.
6.
Rated at 1.5V
7.
If t
T
is longer than 1 ns, a time (t
T
-1) ns has to be added to this parameter.
8.
Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be
given to "wake-up" the device.
9.
Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to t
RC
is satisfied once the Self Refresh Exit command
is registered.
10.
Referenced to the time which the output achieves the open circuit condition, not to output voltage levels.
11.
t
DAL
is equivalent to t
DPL
+ t
RP
.
1.4V
1.4V
tSETUP
tHOLD
tAC
tAC
tLZ
tOH
tHZ
CLOCK
INPUT
OUTPUT
50 pF
I/O
Z=50 Ohm
+ 1.4 V
50 Ohm
2.4V
0.4V
t
T
tCL
tCH
I/O
Measurement conditions for
tac and toh
50 pF
10
V436532Z04V Rev. 1.2 November 2001
MOSEL VITELIC
V436532Z04V
Package Diagram
144 Pin SODIMM
144 Pin SODIMM
2.661
1.25
0.039
0.140
0.787
1
Pin 2 on Backside
3.3V
Pin 144 on Backside
59
61
143
NOTE:
1. All dimensions in inches.
Tolerances
0.005 unless otherwise specified.
0.117
SOC component package
1.00
MOSEL VITELIC
V436532Z04V
11
V436532Z04V Rev. 1.2 November 2001
Module Label Information
Label Information
C
L
= 3 or 2 (CLK)
t
RCD
= 3 or 2 (CLK)
t
RP
= 3 or 2 (CLK)
t
AC
= 5.4 ns
XXX
U
UNBUFFERED DIMM
PC133
54
JEDEC SPD Revision 2
2
V436616R24XXX-XX 128MB CLX
PC133U-XXX-542-A
0130-K682165
Assembly in Taiwan
A
Gerber file Intel
PC100 x 16 Based
-
-
-
MOSEL VITELIC
Part Number
Module Density
DIMM manufacture date code
CAS Latency
2 = CL2
3 = CL3
Criteria of PC100 or PC133
(refer to MVI datasheet)
V436664S24VATG-10PC
512MB CLX
8
V436532Z04VXXX-XXXX 256MB CLX
xxxx-xxxxxxx
8 Based
MOSEL VITELIC
WORLDWIDE OFFICES
V436532Z04V
Copyright , MOSEL VITELIC Inc.
Printed in U.S.A.
MOSEL VITELIC
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461
The information in this document is subject to change without
notice.
MOSEL VITELIC makes no commitment to update or keep cur-
rent the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applica-
tions. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liabil-
ity for consequential or incidental arising from any use of its prod-
ucts. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
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