MOSEL VITELIC
1
V43658R04V
3.3 VOLT 8M x 64 UNBUFFERED SDRAM
MODULE
PRELIMINARY
V43658R04V Rev. 1.0 March 2002
Features
168 Pin Unbuffered 8,388,608 x 64 bit
Oganization SDRAM DIMM
Utilizes High Performance 128 Mbit, 8M x 16
SDRAM in TSOPII-54 Packages
Fully PC Board Layout Compatible to INTEL'S
Rev 1.0 Module Specification
Single +3.3V ( 0.3V) Power Supply
Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All Inputs, Outputs are LVTTL Compatible
4096 Refresh Cycles every 64 ms
Serial Present Detect (SPD)
SDRAM Performance
Description
The V43658R04V memory module is organized
8,388,608 x 64 bits in a 168 pin dual in line memory
module (DIMM). The 8M x 64 memory module uses
4 Mosel-Vitelic 8M x 16 SDRAM. The x64 modules
are ideal for use in high performance computer
systems where increased memory density and fast
access times are required.
Part Number
Speed
Grade
Configuration
V43658R04VXTG-75
-75, CL=3
(133 MHz)
8M x 64
V43658R04VXTG-75PC
-75PC, CL=2,3
(133 MHz)
8M x 64
V43658R04VXTG-10PC
-10PC, CL=2,3
(100 MHz)
8M x 64
2
V43658R04V Rev. 1.0 March 2002
MOSEL VITELIC
V43658R04V
Pin Configurations (Front Side/Back Side)
Notes:
* These pins are not used in this module.
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VSS
I/O1
I/O2
I/O3
I/O4
VCC
I/O5
I/O6
I/O7
I/O8
I/O9
VSS
I/O10
I/O11
I/O12
I/O13
I/O14
VCC
I/O15
I/O16
CBO*
CB1*
VSS
NC
NC
VCC
WE
DQM0
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
DQM1
CS0
DU
VSS
A0
A2
A4
A6
A8
A10(AP)
BA1
VCC
VCC
CLK0
VSS
DU
CS2
DQM2
DQM3
DU
VCC
NC
NC
CB2*
CB3*
VSS
I/O17
I/O18
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
I/O19
I/O20
VCC
I/O21
NC
DU
CKE1
VSS
I/O22
I/O23
I/O24
VSS
I/O25
I/O26
I/O27
I/O28
VCC
I/O29
I/O30
I/O31
I/O32
VSS
CLK2
NC
WP
SDA
SCL
VCC
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
VSS
I/O33
I/O34
I/O35
I/O36
VCC
I/O37
I/O38
I/O39
I/O40
I/O41
VSS
I/O42
I/O43
I/O44
I/O45
I/O46
VCC
I/O47
I/O48
CB4*
CB5*
VSS
NC
NC
VCC
CAS
DQM4
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
DQM5
CS1
RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VCC
CLK1
NC
VSS
CKE0
CS3
DQM6
DQM7
DU
VCC
NC
NC
CB6*
CB7*
VSS
I/O49
I/O50
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
I/O51
I/O52
VCC
I/O53
NC
DU
NC
VSS
I/O54
I/O55
I/O56
VSS
I/O57
I/O58
I/O59
I/O60
VCC
I/O61
I/O62
I/O63
I/O64
VSS
CLK3
NC
SA0
SA1
SA2
VCC
Pin Names
A0A11
Address Inputs
I/O1I/O64
Data Inputs/Outputs
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Read/Write Input
BA0, BA1
Bank Selects
CKE0, CKE1
Clock Enable
CS0CS3
Chip Select
CLK0CLK3
Clock Input
DQM0DQM7
Data Mask
VCC
Power (+3.3 Volts)
VSS
Ground
SCL
Clock for Presence Detect
SDA
Serial Data OUT for Presence
Detect
SA0A2
Serial Data IN for Presence
Detect
CB0CB7
Check Bits (x72 Organization)
NC
No Connection
DU
Don't Use
MOSEL VITELIC
V43658R04V
3
V43658R04V Rev.1.0 March 2002
Part Number Information
Block Diagram
V 4 3 65 8 R 0 4 V X T G - XX
SDRAM
3.3V
WIDTH
DEPTH
168-pins unbuffered DIMM
X16 COMPONENT
REFRESH
RATE 4K
4 BANKS
LVTTL
COMPONENT
REV LEVEL
COMPONENT
PACKAGE, T=TSOP
LEAD FINISH
G = GOLD
SPEED
75PC = PC133 CL2,3
MOSEL VITELIC
MANUFACTURED
75 = PC133 CL3
10PC = PC100 CL2
DQM0
I/O1I/O8
CS0
CS2
WE
WE
WE: SDRAM D0D3
CKE: SDRAM D0D3
RAS: SDRAM D0D3
A(11:0): SDRAM D0D3
BA0, BA1: SDRAM D0D3
CKE0
RAS
CAS
WE
A(11:0)
BA0, BA1
CAS: SDRAM D0D3
C0C7
Two 0.1
F capacitors
per each SDRAM
D0D3
D0D3
V
CC
V
SS
SCL0
SA2
SA1
SA0
CLK0/2
SDA
WP
D0/D2
D1/D3
E
2
PROM SPD (256 WORD X 8 BITS)
47K
10
LDQM
I/O1I/O8
UDQM
I/O9I/O16
CS
D0
10
DQM1
I/O9I/O16
10
DQM4
I/O33I/O40
WE
LDQM
I/O1I/O8
UDQM
I/O9I/O16
CS
D2
10
DQM5
I/O41I/O48
10
DQM2
I/O17I/O24
WE
LDQM
I/O1I/O8
UDQM
I/O9I/O16
CS
D1
10
DQM3
I/O25I/O32
10
DQM6
I/O49I/O56
WE
LDQM
I/O1I/O8
UDQM
I/O9I/O16
CS
D3
10
DQM7
I/O57I/O64
10
CLK1/3
10pF
10
15pF
4
V43658R04V Rev. 1.0 March 2002
MOSEL VITELIC
V43658R04V
Serial Presence Detect Information
A serial presence detect storage device -
E
2
PROM - is assembled onto the module. Informa-
tion about the module configuration, speed, etc. is
written into the E
2
PROM device during module pro-
duction using a serial presence detect protocol (I
2
C
synchronous 2-wire bus)
SPD Table
Byte Num-
ber
Function Described
SPD Entry Value
Hex Value
-75PC
-75
-10PC
0
Number of SPD bytes
128
80
80
80
1
Total bytes in Serial PD
256
08
08
08
2
Memory Type
SDRAM
04
04
04
3
Number of Row Addresses (without BS bits)
12
0C
0C
0C
4
Number of Column Addresses (for x16
SDRAM)
9
09
09
09
5
Number of DIMM Banks
1
01
01
01
6
Module Data Width
64
40
40
40
7
Module Data Width (continued)
0
00
00
00
8
Module Interface Levels
LVTTL
01
01
01
9
SDRAM Cycle Time at CL=3
7.5 ns/10.0 ns
75
75
A0
10
SDRAM Access Time from Clock at CL=3
5.4 ns/6.0 ns
54
54
60
11
Dimm Config (Error Det/Corr.)
none
00
00
00
12
Refresh Rate/Type
Self-Refresh, 15.6
s
80
80
80
13
SDRAM width, Primary
x16
10
10
10
14
Error Checking SDRAM Data Width
n/a / x8
00
00
00
15
Minimum Clock Delay from Back to Back Ran-
dom Column Address
t
ccd
= 1 CLK
01
01
01
16
Burst Length Supported
1, 2, 4, 8
0F
0F
0F
17
Number of SDRAM Banks
4
04
04
04
18
Supported CAS Latencies
CL = 3, 2
06
06
06
19
CS Latencies
CS Latency = 0
01
01
01
20
WE Latencies
WL = 0
01
01
01
21
SDRAM DIMM Module Attributes
Non Buffered/Non Reg.
00
00
00
22
SDRAM Device Attributes: General
Vcc tol 10%
0E
0E
0E
23
Minimum Clock Cycle Time at CAS Latency =
2
7.5 ns/10.0 ns
75
A0
A0
24
Maximum Data Access Time from Clock for
CL = 2
5.4 ns/6.0 ns
54
60
60
25
Minimum Clock Cycle Time at CL = 1
Not Supported
00
00
00
26
Maximum Data Access Time from Clock at CL
= 1
Not Supported
00
00
00
27
Minimum Row Precharge Time
15 ns/20 ns
0F
14
14
MOSEL VITELIC
V43658R04V
5
V43658R04V Rev.1.0 March 2002
DC Characteristics
T
A
= 0
C to 70
C; V
SS
= 0 V; V
DD
, V
DDQ
= 3.3V
0.3V
28
Minimum Row Active to Row Active Delay
t
RRD
14 ns/15 ns/16 ns
0E
0F
10
29
Minimum RAS to CAS Delay t
RCD
15 ns/20 ns
0F
14
14
30
Minimum RAS Pulse Width t
RAS
42 ns/45 ns
2A
2D
2D
31
Module Bank Density (Per Bank)
64 MByte
10
10
10
32
SDRAM Input Setup Time
1.5 ns/2.0 ns
15
15
20
33
SDRAM Input Hold Time
0.8 ns/1.0 ns
08
08
10
34
SDRAM Data Input Setup Time
1.5 ns/2.0 ns
15
15
20
35
SDRAM Data Input Hold Time
0.8 ns/1.0 ns
08
08
10
62-61
Superset Information (May be used in Future)
00
00
00
62
SPD Revision
Revision 2/1.2
02
02
12
63
Checksum for Bytes 0 - 62
D1
16
84
64
Manufacturer's JEDEC ID Code
Mosel Vitelic
40
40
40
65-71
Manufacturer's JEDEC ID Code (cont.)
00
00
00
72
Manufacturing Location
73-90
Module Part Number (ASCII)
V43658R04V
91-92
PCB Identification Code
93
Assembly Manufacturing Date (Year)
94
Assembly Manufacturing Date (Week)
95-98
Assembly Serial Number
99-125
Reserved
00
00
00
126
Intel Specification for Frequency
64
64
64
127
Supported frequency
128+
Unused Storage Location
00
00
00
Symbol
Parameter
Limit Values
Unit
Min.
Max.
V
IH
Input High Voltage
2.0
V
CC
+0.3
V
V
IL
Input Low Voltage
0.5
0.8
V
V
OH
Output High Voltage (I
OUT
= 2.0 mA)
2.4
--
V
V
OL
Output Low Voltage (I
OUT
= 2.0 mA)
--
0.4
V
SPD (Continued)Table
Byte Num-
ber
Function Described
SPD Entry Value
Hex Value
-75PC
-75
-10PC
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