MOSEL VITELIC
1
V53C806H
HIGH PERFORMANCE
1M x 8 BIT FAST PAGE MODE
CMOS DYNAMIC RAM
PRELIMINARY
V53C806H Rev. 1.6 April 1998
HIGH PERFORMANCE
40
45
50
60
Max. RAS Access Time, (t
RAC
)
40 ns
45 ns
50 ns
60 ns
Max. Column Address Access Time, (t
CAA
)
20 ns
22 ns
24 ns
30 ns
Min. Fast Page Mode Cycle Time, (t
PC
)
23 ns
25 ns
28 ns
40 ns
Min. Read/Write Cycle Time, (t
RC
)
75 ns
80 ns
90 ns
120 ns
Features
s
1M x 8-bit organization
s
Fast Page Mode for a sustained data rate of
43 MHz
s
RAS access time: 40, 45, 50, 60 ns
s
Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh capability
s
Refresh Interval: 1024 cycle/16 ms
s
Available in 28-pin 400 mil SOJ package
s
Single +5V
10% Power Supply
s
TTL Interface
Description
The V53C806H is a ultra high speed 1,048,576 x
8 bit CMOS dynamic random access memory. The
V53C806H offers a combination of features: Fast
Page Mode for high data bandwidth, and Low
CMOS standby current.
All inputs and outputs are TTL compatible. Input
and output capacitances are significantly lowered to
allow increased system performance. Fast Page
Mode operation allows random access of up to
1024 x 8 bits within a row with cycle times as fast as
23 ns. Because of static circuitry, the CAS clock is
not in the critical timing path. The flow-through col-
umn address latches allow address pipelining while
relaxing many critical system timing requirements.
The V53C806H is ideally suited for graphics, dig-
ital signal processing and high-performance com-
puting systems.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
K
40
45
50
60
Std.
0
C to 70
C
Blank
2
V53C806H Rev. 1.6 April 1998
MOSEL VITELIC
V53C806H
FAMILY
DEVICE
PKG
( t
RAC
)
SPEED
PWR.
V
5
3
C
40 (40 ns)
45 (45 ns)
50 (50 ns)
60 (60 ns)
TEMP.
BLANK (0
C to 70
C)
BLANK (NORMAL)
K (SOJ)
8
0
6
H
808H-01
Description
Pkg.
Pin Count
SOJ
K
28
28-Pin SOJ
PIN CONFIGURATION
Top View
Pin Names
VCC
IO1
IO2
IO3
IO4
WE
NC
NC
A0
A1
A2
A3
1
2
3
4
5
6
8
9
10
11
12
13
28
27
806H-02
26
25
24
23
21
20
19
18
17
VSS
IO8
IO7
IO6
IO5
CAS
A9
A8
A7
A6
A5
A4
16
RAS
VCC
7
14
22
OE
VSS
15
A
0
A
9
Address Inputs
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
OE
Output Enable
I/O
1
I/O
8
Data Input, Output
V
CC
+5V Supply
V
SS
0V Supply
NC
No Connect
Absolute Maximum Ratings*
Ambient Temperature
Under Bias..................................10
C to +80
C
Storage Temperature (plastic)......55
C to +125
C
Voltage Relative to V
SS
................. 1.0 V to +7.0 V
Data Output Current ..................................... 50 mA
Power Dissipation.......................................... 1.4 W
*Note:
Operation above Absolute Maximum Ratings can
adversely affect device reliability.
Capacitance*
T
A
= 25
C, V
CC
= 5 V
10%, f = 1 MHz
* Note:
Capacitance is sampled and not 100% tested
Symbol
Parameter Typ.
Max.
Unit
C
IN1
Address Input
3
4
pF
C
IN2
RAS, CAS, WE, OE
4
5
pF
C
OUT
Data Input/Output
5
7
pF
3
V53C806H Rev. 1.6 April 1998
MOSEL VITELIC
V53C806H
Block Diagram
A 0
A 1
A8
A9
SENSE AMPLIFIERS
REFRESH
COUNTER
VCC
VSS
10
I/O1
ADDRESS BUFFERS
AND PREDECODERS
X 0 -X
ROW
DECODERS
1024
MEMORY
ARRAY
1024 x 1024 x 8
COLUMN DECODERS
DATA I/O BUS
Y0 -Y9
1024 x 8
I/O
BUFFER
I/O2
I/O3
I/O4
OE CLOCK
GENERATOR
WE CLOCK
GENERATOR
CAS CLOCK
1M x 8
GENERATOR
RAS CLOCK
GENERATOR
OE
806H-03
WE
CAS
RAS
9
I/O5
I/O6
I/O7
I/O8
4
V53C806H Rev. 1.6 April 1998
MOSEL VITELIC
V53C806H
DC and Operating Characteristics
T
A
= 0
C to 70
C, V
CC
= 5 V
10%, V
SS
= 0 V, unless otherwise specified.
Symbol
Parameter
Access
Time
V53C806H
Unit
Test Conditions
Notes
Min.
Typ.
Max.
I
LI
Input Leakage Current
(any input pin)
10
10
m
A
V
SS
V
IN
V
CC
I
LO
Output Leakage Current
(for High-Z State)
10
10
m
A
V
SS
V
OUT
V
CC
RAS, CAS at V
IH
I
CC1
V
CC
Supply Current,
Operating
40
220
mA
t
RC
= t
RC
(min.)
1, 2
45
210
50
200
60
190
I
CC2
V
CC
Supply Current,
TTL Standby
4
mA
RAS, CAS at V
IH
other inputs
V
SS
I
CC3
V
CC
Supply Current,
RAS-Only Refresh
40
220
mA
t
RC
= t
RC
(min.)
2
45
210
50
200
60
190
I
CC4
V
CC
Supply Current,
Fast Page Mode
Operation
40
110
mA
Minimum cycle
1, 2
45
100
50
90
60
80
I
CC5
V
CC
Supply Current,
Standby, Output Enabled
2.0
mA
RAS = V
IH
, CAS = V
IL
other inputs
V
SS
1
I
CC6
V
CC
Supply Current,
CMOS Standby
2.0
mA
RAS
V
CC
0.2 V,
CAS
V
CC
0.2 V,
All other inputs
V
SS
V
CC
Supply Voltage
4.5
5.0
5.5
V
V
IL
Input Low Voltage
1
0.8
V
3
V
IH
Input High Voltage
2.4
V
CC
+ 1
V
3
V
OL
Output Low Voltage
0.4
V
I
OL
= 4.2 mA
V
OH
Output High Voltage
2.4
V
I
OH
= 5 mA
5
V53C806H Rev. 1.6 April 1998
MOSEL VITELIC
V53C806H
AC Characteristics
T
A
= 0
C to 70
C, V
CC
= 5 V
10%, V
SS
= 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V
#
Symbol
Parameter
40
45
50
60
Unit
Notes
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
1
t
RAS
RAS Pulse Width
40
75K
45
75K
50
75K
60
75K
ns
2
t
RC
Read or Write Cycle Time
75
80
90
110
ns
3
t
RP
RAS Precharge Time
25
25
30
40
ns
4
t
CSH
CAS Hold Time
40
45
50
60
ns
5
t
CAS
CAS Pulse Width
12
13
14
15
ns
6
t
RCD
RAS to CAS Delay
17
28
18
32
19
36
20
43
ns
7
t
RCS
Read Command Setup Time
0
0
0
0
ns
4
8
t
ASR
Row Address Setup Time
0
0
0
0
ns
9
t
RAH
Row Address Hold Time
7
8
9
10
ns
10
t
ASC
Column Address Setup Time
0
0
0
0
ns
11
t
CAH
Column Address Hold Time
5
6
7
10
ns
12
t
RSH (R)
RAS Hold Time (Read Cycle)
12
13
14
15
ns
13
t
CRP
CAS to RAS Precharge Time
5
5
5
5
ns
14
t
RCH
Read Command Hold Time
Referenced to CAS
0
0
0
0
ns
5
15
t
RRH
Read Command Hold Time
Referenced to RAS
0
0
0
0
ns
5
16
t
ROH
RAS Hold Time Referenced to OE
8
9
10
10
ns
17
t
OAC
Access Time from OE
12
13
14
17
ns
18
t
CAC
Access Time from CAS
12
13
14
17
ns
6, 7
19
t
RAC
Access Time from RAS
40
45
50
60
ns
6, 8, 9
20
t
CAA
Access Time from Column Address
20
22
24
30
ns
6, 7, 10
21
t
LZ
CAS to Low-Z Output
0
0
0
0
ns
16
22
t
HZ
Output buffer turn-off delay time
0
6
0
7
0
8
0
10
ns
16
23
t
AR
Column Address Hold Time
from RAS
30
35
40
45
ns
24
t
RAD
RAS to Column Address
12
20
13
23
14
26
15
30
ns
11
Delay Time
25
t
RSH (W)
RAS or CAS Hold Time in Write
Cycle
12
13
14
15
ns
26
t
CWL
Write Command to CAS Lead Time
12
13
14
15
ns
27
t
WCS
Write Command Setup Time
0
0
0
0
ns
12, 13
28
t
WCH
Write Command Hold Time
5
6
7
10
ns
29
t
WP
Write Pulse Width
5
6
7
10
ns
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