1
V53C8256L Rev. 1.1 August 1996
MOSEL VITELIC
V53C8256L
HIGH PERFORMANCE
60
Max.
RAS
Access Time, (t
RAC
)
60 ns
Max. Column Address Access Time, (t
CAA
)
30 ns
Min. Fast Page Mode Cycle Time, (t
PC
)
40 ns
Min. Read/Write Cycle Time, (t
RC
)
120 ns
PRELIMINARY
V53C8256L
ULTRA-HIGH PERFORMANCE,
3.3 VOLT 256K X 8 BIT FAST PAGE MODE
CMOS DYNAMIC RAM
Features
s
256K x 8-bit organization
s
Fast Page Mode for a sustained data rate
of 25 MHz
s
RAS
access time: 60 ns
s
Read-Modify-Write,
RAS
-Only Refresh,
CAS
-Before-
RAS
Refresh capability
s
Refresh Interval--512 cycles/8 ms
s
Available in 24 pin 300 mil Plastic DIP,
26/24 pin 300 mil SOJ, and 28-pin TSOP-I
packages
s
Single +3.3 V
0.3 V power supply
s
TTL Interface
Description
The V53C8256L is a high speed 262,144 x 8 bit
CMOS dynamic random access memory. The
V53C8256L offers a combination of features: Fast
Page Mode for high data bandwidth, fast usable
speed, CMOS standby current.
All inputs and outputs are TTL compatible. Input
and output capacitances are significantly lowered to
allow increased system performance. Fast Page
Mode operation allows random access of up to 512
(x8) bits within a row with cycle times as short as
40ns. Because of static circuitry, the
CAS
clock is
not in the critical timing path. The flow-through
column address latches allow address pipelining
while relaxing many critical system timing
requirements for fast usable speed. These features
make the V53C8256L ideally suited for graphics,
digital signal processing and high performance
computing systems.
Device Usage Chart
Operating
Package Outline
Access Time (ns)
Power
Temperature
Temperature
Range
K
T
60
Std.
Mark
0
C to 70
C
Blank
-40
C to 85
C
I
-55
C to 125
C
E
2
V53C8256L
V53C8256L Rev. 1.1 August 1996
MOSEL VITELIC
Description
Pkg.
Pin Count
Plastic DIP
P
26
SOJ
K
26/24
TSOP-I
T
28
26/24 Lead SOJ
PIN CONFIGURATION
Top View
24 Lead Plastic DIP
PIN CONFIGURATION
Top View
V
5
3
C
2
5
6
L
8
FAMILY
DEVICE
PKG
( t
RAC
)
SPEED
PWR.
60 (60 ns)
TEMP.
BLANK (0
C to 70
C)
I (-40
C TO 85
C)
E (-55
C TO 125
C)
BLANK (NORMAL)
L (LOW POWER)
P (PLASTIC DIP)
K (SOJ)
T (TSOP-I)
8256L 01
V
SS
I/O
1
I/O
2
I/O
3
I/O
4
WE
RAS
A
0
A
1
A
2
A
3
V
CC
8256L 03
1
2
3
4
5
6
7
8
9
10
11
12
14
13
24
23
22
21
20
19
18
17
16
15
300 mil
V
SS
I/O
8
I/O
7
I/O
6
I/O
5
CAS
OE
A
8
A
7
A
6
A
5
A
4
WE
RAS
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
8256L 02
17
16
15
300 mil
CAS
OE
14
V
SS
I/O
1
I/O
2
I/O
3
I/O
4
A
0
A
1
A
2
A
3
V
CC
V
SS
I/O
8
I/O
7
I/O
6
I/O
5
A
8
A
7
A
6
A
5
A
4
28 Lead TSOP-I
PIN CONFIGURATION
Top View
CAS
I/O5
I/O6
I/O7
I/O8
VSS
VSS
NC
I/O1
I/O2
I/O3
I/O4
NC
WE
OE
A8
A7
A6
A5
A4
NC
VCC
NC
A3
A2
A1
A0
RAS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
8256L 04
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Names
A
0
A
8
Address Inputs
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
OE
Output Enable
I/O
1
I/O
8
Data Input, Output
V
CC
+5V Supply
V
SS
0V Supply
NC
No Connect
3
V53C8256L Rev. 1.1 August 1996
MOSEL VITELIC
V53C8256L
Absolute Maximum Ratings*
Ambient Temperature
Under Bias ............................. 10
C to +80
C
Storage Temperature (plastic) .... 55
C to +125
C
Voltage Relative to V
SS ....................
1.0 V to +4.6 V
Data Output Current .................................... 50 mA
Power Dissipation ......................................... 1.0 W
*Note: Operation above Absolute Maximum Ratings can
adversely affect device reliability.
Capacitance*
T
A
= 25
C, V
CC
= 3.3 V
0.3V, f = 1 MHz
Symbol
Parameter
Typ. Max.
Unit
C
IN1
Address Input
3
4
pF
C
IN2
RAS
,
CAS
,
WE
,
OE
4
5
pF
C
OUT
Data Input/Output
5
7
pF
* Note: Capacitance is sampled and not 100% tested
Block Diagram
A0
A1
A
7
A8
SENSE AMPLIFIERS
REFRESH
COUNTER
VCC
VSS
9
I/O 1
ADDRESS B
UFFERS
AND PREDECODERS
X 0 -X
RO
W
DECODERS
512
MEMORY
ARRAY
COLUMN DECODERS
DATA I/O BUS
Y0 -Y8
512 x 8
I/O
BUFFER
8256L 05
I/O2
I/O3
I/O4
OE CLOCK
GENERATOR
WE CLOCK
GENERATOR
CAS CLOCK
GENERATOR
256K x 8
RAS CLOCK
GENERATOR
OE
WE
CAS
RAS
8
I/O 5
I/O6
I/O7
I/O8
4
V53C8256L
V53C8256L Rev. 1.1 August 1996
MOSEL VITELIC
DC and Operating Characteristics (1-2)
T
A
= 0
C to 70
C, V
CC
= 3.3 V
0.3 V, V
SS
= 0 V, unless otherwise specified.
V53C8256L
Time
Min.
Typ.
Max. Unit
Test Conditions
Notes
I
LI
Input Leakage Current
10
10
A
V
SS
V
IN
V
CC
(any input pin)
I
LO
Output Leakage Current
10
10
A
V
SS
V
OUT
V
CC
(for High-Z State)
RAS
,
CAS
at V
IH
I
CC1
V
CC
Supply Current,
60
120
mA
t
RC
= t
RC
(min.)
1, 2
Operating
I
CC2
V
CC
Supply Current,
2
mA
other inputs
V
SS
TTL Standby
I
CC3
V
CC
Supply Current,
60
120
mA
t
RC
= t
RC
(min.)
2
RAS
-Only Refresh
I
CC4
V
CC
Supply Current,
60
110
mA
Minimum Cycle
1, 2
Fast Page Mode
Operation
I
CC5
V
CC
Supply Current,
2.0
mA
RAS
=V
IH
,
CAS
=V
IL
1
Standby, Output Enabled
other inputs
V
SS
I
CC6
V
CC
Supply Current,
2.0
mA
RAS
V
CC
0.2 V,
CMOS Standby
CAS
V
CC
0.2 V,
All other inputs
V
SS
V
IL
Input Low Voltage
1
0.8
V
3
V
IH
Input High Voltage
2.0
V
CC
+1
V
3
V
OL
Output Low Voltage
0.4
V
I
OL
= 2.0 mA
V
OH
Output High Voltage
2.4
V
I
OH
= 2.0 mA
Access
Symbol
Parameter
5
V53C8256L Rev. 1.1 August 1996
MOSEL VITELIC
V53C8256L
AC Characteristics
T
A
= 0
C to 70
C, V
CC
= 3.3 V
0.3 V, V
SS
= 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V
60
#
Symbol
Symbol
Parameter
Min.
Max.
Unit
Notes
1
t
RL1RH1
t
RAS
RAS
Pulse Width
60
75K
ns
2
t
RL2RL2
t
RC
Read or Write Cycle Time
120
ns
3
t
RH2RL2
t
RP
RAS
Precharge Time
50
ns
4
t
RL1CH1
t
CSH
CAS
Hold Time
60
ns
5
t
CL1CH1
t
CAS
CAS
Pulse Width
15
ns
6
t
RL1CL1
t
RCD
RAS
to
CAS
Delay
20
45
ns
7
t
WH2CL2
t
RCS
Read Command Setup Time
0
ns
4
8
t
AVRL2
t
ASR
Row Address Setup Time
0
ns
9
t
RL1AX
t
RAH
Row Address Hold Time
10
ns
10
t
AVCL2
t
ASC
Column Address Setup Time
0
ns
11
t
CL1AX
t
CAH
Column Address Hold Time
10
ns
12
t
CL1RH1(R)
t
RSH (R)
RAS
Hold Time (Read Cycle)
15
ns
13
t
CH2RL2
t
CRP
CAS
to
RAS
Precharge Time
5
ns
14
t
CH2WX
t
RCH
Read Command Hold Time Referenced to
CAS
0
ns
5
15
t
RH2WX
t
RRH
Read Command Hold Time Referenced to
RAS
0
ns
5
16
t
OEL1RH2
t
ROH
RAS
Hold Time Referenced to
OE
10
ns
17
t
GL1QV
t
OAC
Access Time from
OE
15
ns
18
t
CL1QV
t
CAC
Access Time from
CAS
15
ns
6, 7
19
t
RL1QV
t
RAC
Access Time from
RAS
60
ns
6, 8, 9
20
t
AVQV
t
CAA
Access Time from Column Address
30
ns
6, 7, 10
21
t
CL1QX
t
LZ
OE
or
CAS
to Low-Z Output
0
ns
16
22
t
CH2QZ
t
HZ
OE
or
CAS
to High-Z Output
0
10
ns
16
23
t
RL1AX
t
AR
Column Address Hold Time from
RAS
50
ns
24
t
RL1AV
t
RAD
RAS
to Column Address Delay Time
15
30
ns
11
25
t
CL1RH1(W)
t
RSH (W)
RAS
or
CAS
Hold Time in Write Cycle
15
ns
26
t
WL1CH1
t
CWL
Write Command to
CAS
Lead Time
15
ns
27
t
WL1CL2
t
WCS
Write Command Setup Time
0
ns
12, 13
28
t
CL1WH1
t
WCH
Write Command Hold Time
10
ns
29
t
WL1WH1
t
WP
Write Pulse Width
10
ns
30
t
RL1WH1
t
WCR
Write Command Hold Time from
RAS
50
ns
31
t
WL1RH1
t
RWL
Write Command to
RAS
Lead Time
15
ns
JEDEC
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