MOSEL VITELIC
1
V54C2128164VAT
128Mbit SDRAM
2.5 VOLT, TSOP II 8M X 16
V54C2128164VAT Rev. 1.0 April 2003
PRELIMINARY
6
7PC
7
8PC
System Frequency (f
CK
)
166 MHz
143 MHz
143 MHz
125 MHz
Clock Cycle Time (t
CK3
)
6 ns
7 ns
7 ns
8 ns
Clock Access Time (t
AC3
) CAS Latency = 3
5.4 ns
5.4 ns
5.4 ns
6 ns
Clock Access Time (t
AC2
) CAS Latency = 2
5.4 ns
5.4 ns
6 ns
6 ns
Features
4 banks x 2Mbit x 16 organization
High speed data transfer rates up to 166 MHz
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
Single Pulsed RAS Interface
Data Mask for Read/Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 3
Programmable Wrap Sequence: Sequential or
Interleave
Programmable Burst Length:
1, 2, 4, 8 for Sequential Type
1, 2, 4, 8 for Interleave Type
Multiple Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
Random Column Address every CLK (1-N Rule)
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 4096 cycles/64 ms
Available in 54 Pin TSOPII
LVTTL Interface
Single +2.5 V
0.2 V Power Supply
Description
The V54C2128164VAT is a four bank Synchro-
nous DRAM organized as 4 banks x 2Mbit x 16.The
V54C2128164VAT achieves high speed data trans-
fer rates up to 166 MHz by employing a chip archi-
tecture that prefetches multiple bits and then
synchronizes the output data to a system clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
T/S
6
7PC
7
8PC
Std.
L
-40
C to 70C
Blank
4
V54C2128164VAT Rev.1.0 April 2003
MOSEL VITELIC
V54C2128164VAT
Signal Pin Description
Pin
Type
Signal
Polarity
Function
CLK
Input
Pulse
Positive
Edge
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the
clock.
CKE
Input
Level
Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby
initiates either the Power Down mode or the Self Refresh mode.
CS
Input
Pulse
Active Low CS enables the command decoder when low and disables the command decoder when
high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
RAS, CAS
WE
Input
Pulse
Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
command to be executed by the SDRAM.
A0 - A11
Input
Level
--
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-An defines the column address (CA0-CAn)
when sampled at the rising clock edge.CAn depends from the SDRAM organization:
8M x 16 SDRAM CA0CA8.
In addition to the column address, A10(=AP) is used to invoke autoprecharge operation
at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1
to control which bank(s) to precharge. If A10 is high, all four banks will BA0 and BA1 are
used to define which bank to precharge.
BA0,
BA1
Input
Level
--
Selects which bank is to be active.
DQx
Input
Output
Level
--
Data Input/Output pins operate in the same manner as on conventional DRAMs.
LDQM
UDQM
Input
Pulse
Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sam-
pled high. In Read mode, DQM has a latency of two clock cycles and controls the output
buffers like an output enable. In Write mode, DQM has a latency of zero and operates as
a word mask by allowing input data to be written if it is low but blocks the write operation
if DQM is high.
VCC, VSS Supply
Power and ground for the input buffers and the core logic.
VCCQ
VSSQ
Supply
--
--
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
5
V54C2128164VAT Rev. 1.0 April 2003
MOSEL VITELIC
V54C2128164VAT
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the
positive edge of the clock. The following list shows the thruth table for the operation commands.
Notes:
1. V = Valid , x = Don't Care, L = Low Level, H = High Level
2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands
are provided.
3. These are state of bank designated by BS0, BS1 signals.
4. Power Down Mode can not entry in the burst cycle.
Operation
Device
State
CKE
n-1
CKE
n
CS
RAS
CAS
WE
DQM
A0-9,
A11
A10
BS0
BS1
Row Activate
Idle
3
H
X
L
L
H
H
X
V
V
V
Read
Active
3
H
X
L
H
L
H
X
V
L
V
Read w/Autoprecharge
Active
3
H
X
L
H
L
H
X
V
H
V
Write Active
3
H
X
L
H
L
L
X
V
L
V
Write with Autoprecharge
Active
3
H
X
L
H
L
L
X
V
H
V
Row Precharge
Any
H
X
L
L
H
L
X
X
L
V
Precharge All
Any
H
X
L
L
H
L
X
X
H
X
Mode Register Set
Idle
H
X
L
L
L
L
X
V
V
V
No Operation
Any
H
X
L
H
H
H
X
X
X
X
Device Deselect
Any
H
X
H
X
X
X
X
X
X
X
Auto Refresh
Idle
H
H
L
L
L
H
X
X
X
X
Self Refresh Entry
Idle
H
L
L
L
L
H
X
X
X
X
Self Refresh Exit
Idle
(Self Refr.)
L
H
H
X
X
X
X
X
X
X
L
H
H
X
Power Down Entry
Idle
Active
4
H
L
H
X
X
X
X
X
X
X
L
H
H
X
Power Down Exit
Any
(Power
Down)
L
H
H
X
X
X
X
X
X
X
L
H
H
L
Data Write/Output Enable
Active
H
X
X
X
X
X
L
X
X
X
Data Write/Output Disable
Active
H
X
X
X
X
X
H
X
X
X
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