MOSEL VITELIC

V54C31732G2V
HIGH PERFORMANCE 166/143 MHz
3.3 VOLT ENHANCED GRAPHICS
512K X 32 SDRAM 2 BANKS X 256Kbit X 32

V54C31732G2V Rev. 1.0 August 1999

PRELIMINARY

V54C31732G2V

-6

-7

-8

-10

Unit

Clock Frequency (t

)

166

143

125

100

MHz

Latency

clocks

Cycle Time (t

)

Access Time (t

)

5.4

Features

JEDEC Standard 3.3V Power Supply

Specially screened for graphics applications

Single Pulsed RAS Interface

Programmable CAS Latency: 2, 3

All Inputs are sampled at the positive going edge
of clock

Programmable Wrap Sequence: Sequential or
Interleave

Programmable Burst Length: 1, 2, 4, 8 and Full
Page for Sequential and 1, 2, 4, 8 for Interleave

DQM 0-3 for Byte Masking

Auto & Self Refresh

2K Refresh Cycles/32 ms

Special Mode Registers

One Color Register

Burst Read with Single Write Operation

Block Write (8 Columns)

Description

The V54C31732G2V is a 33,554,432 bits syn-

chronous high data rate DRAM organized as 2 x
262,144 words by 32 bits. The device is designed to
comply with JEDEC standards set for synchronous
DRAM products, both electrically and mechanically.
Synchronous design allows precise cycle control
with the system clock. The CAS latency, burst
length and burst sequence must be programmed
into device prior to access operation. In addition, it
features block write and masked block write func-
tions by making a programmable mode register and
special mode register, the system can select modes
to maximize its performance.

V54C31732G2V Rev. 1.0 August 1999

MOSEL VITELIC

V54C31732G2V

100 Pin TQFP

PIN CONFIGURATION

Top View

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

100

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

VSSQ

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

VDD

VSSQ

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VDD
A

VDDQ

VSSQ

VDDQ

VSSQ

VDDQ

VDD

VSSQ

VDDQ

DQM

CAS

RAS

VDDQ

VSSQ

VDDQ

VSSQ

VDDQ

VDD

VSSQ

VDDQ

DQM

DQM1

CLK

CKE

DSF

100 pin TQFP

20 x 14 mm

0.65 mm pitch

(Marking side)

V54C31732G2V-01

MOSEL VITELIC

V54C31732G2V

V54C31732G2V Rev. 1.0 August 1999

Block Diagram

V54C31732G2V-02

CLK

CKE

RAS

CAS

DSF

DQMi

CLK

Address

-A

, BA

Column Address

Buffer

Row Address

Buffer

Refresh
Counter

Latency 8

Burst Length

Output

Buff

Input

Buff

Prog

r
amming

Column Decoder

Sense Amplifier

Timing

Column Address

Counter

Row

Decoder

MUX

Write

Control

Logic

Block

Write

Control

Logic

Memory Array

Bank 0

256k x 32

Memory Array

Bank 1

256k x 32

Row

Decoder

Color

DQMi

-DQ

Column Addresses

-A

, BA

Row Addresses

Column Decoder

Sense Amplifier

V54C31732G2V Rev. 1.0 August 1999

MOSEL VITELIC

V54C31732G2V

Signal Pin Description

Pin

Name

Input Function

CLK

Clock Input

System clock input. Active on the positive rising edge to sample all inptus

CKE

Clock Enable

Activates the CLK signal when high and deactivates the CLK when low.
CKE low initiates the power down mode, suspend mode, or the self
refresh mode

Chip Select

Disables or enables device operation by masking or enabling all inputs
except CLK, CKE and DQMi

RAS

Row Address Strobe

Latches row addresses on the positive edge of CLK with RAS low.
Enables row access & precharge

CAS

Column Address Strobe

Latches column addresses on the positive edge of CLK with CAS low.
Enables column access

Write Enable

Enables write operation

-A

Address

During a bank activate command, A

-A

defines the row address. During

a read or write command, A

-A

defines the column address. In addition

to the column address A

is used to invoke auto precharge BA define the

bank to be precharged. A

is low, auto precharge is disabled during a

precharge cycle, If A

is high, both bank will be precharged ,if A

is low,

the BA is used to decide which bank to precharge

Bank Select

Selects which bank to activate. BA low select bank A and high selects
bank B

-DQ

Data Input/Output

Data inputs/output are multiplexed on the same pins

DQMi

Data Input/Output Mask

Makes data output Hi-Z. Blocks data input when DQM is active

VDD/VSS

Power Supply/Ground

Power Supply. +3.3V

�

0.3V/ground

VDDQ/VSSQ

Data Output Power/Ground

Provides isolated power/ground to DQs for improved noise immunity

DSF

Define Special Function

Enables block write and special mode register set

No Connection

V54C31732G2V Rev. 1.0 August 1999

MOSEL VITELIC

V54C31732G2V

Address Input for Mode Set (Mode Register Operation)

Power On and Initialization

The default power on state of the mode register is

supplier specific and may be undefined. The
following power on and initialization sequence
guarantees the device is preconditioned to each
users specific needs. Like a conventional DRAM,
the Synchronous DRAM must be powered up and
initialized in a predefined manner. During power on,
all VCC and VCCQ pins must be built up
simultaneously to the specified voltage when the
input signals are held in the "NOP" state. The power
on voltage must not exceed VCC+0.3V on any of
the input pins or VCC supplies. The CLK signal
must be started at the same time. After power on,
an initial pause of 200

�

s is required followed by a

precharge of both banks using the precharge
command. To prevent data contention on the DQ
bus during power on, it is required that the DQM and
CKE pins be held high during the initial pause
period. Once all banks have been precharged, the

Mode Register Set Command must be issued to
initialize the Mode Register. A minimum of eight
Auto Refresh cycles (CBR) are also required.These
may be done before or after programming the Mode
Register. Failure to follow these steps may lead to
unpredictable start-up modes.

Programming the Mode Register

The Mode register designates the operation

mode at the read or write cycle. This register is di-
vided into 4 fields. A Burst Length Field to set the
length of the burst, an Addressing Selection bit to
program the column access sequence in a burst cy-
cle (interleaved or sequential), a CAS

Latency

Field

to set the access time at clock cycle and a Opera-
tion mode field to differentiate between normal op-
eration (Burst read and burst Write) and a special
Burst Read and Single Write mode. The mode set
operation must be done before any activate com-
mand after the initial power up. Any content of the

Address Bus (Ax)

Burst Length

CAS Latency

Mode Register

CAS Latency

Latency

Reserve

Burst Length

Length

Sequential

Interleave

Reserve

Full Page

Reserve

Burst

Type

Type

Sequential

Interleave

Test Mode

Mode

Mode Reg

Set

Test

Mode

Write Burst Length

Write Burst Length

Length

Burst

Single Bit

Special Mode Set SMRS

Functions

Unchanged

Load Color Register

Электронный компонент: V54C31732G2V-8