MOSEL VITELIC
1
V58C2256(804/404/164)S
HIGH PERFORMANCE
2.5 VOLT 256 Mbit DDR SDRAM
4 BANKS X 8Mbit X 8 (804)
4 BANKS X 4Mbit X 16 (164)
4 BANKS X 16Mbit X 4 (404)
PRELIMINARY
V58C2256(804/404/164)S Rev.1.4 October 2002
6
7
75
8
DDR333B
DDR266A
DDR266B
DDR200
Clock Cycle Time (t
CK2
)
7.5 ns
7.5ns
10 ns
10 ns
Clock Cycle Time (t
CK2.5
)
6 ns
7ns
7.5 ns
8 ns
System Frequency (f
CK max
)
166 MHz
143 MHz
133 MHz
125 MHz
Features
High speed data transfer rates with system
frequency up to 166 MHz
Data Mask for Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 2.5
Programmable Wrap Sequence: Sequential
or Interleave
Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
Automatic and Controlled Precharge Command
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 8192 cycles/64 ms
Available in 66-pin 400 mil TSOP or 60 Ball SOC
BGA
SSTL-2 Compatible I/Os
Double Data Rate (DDR)
Bidirectional Data Strobe (DQS) for input and
output data, active on both edges
On-Chip DLL aligns DQ and DQs transitions with
CK transitions
Differential clock inputs CK and CK
Power Supply 2.5V 0.2V
QFC options for FET control. x4 parts.
*Note: DDR 333B Supports PC2700 module with 2.5-3-3 timing
DDR 266A Supports PC2100 module with 2-2-2 timing
DDR 266B Supports PC2100 module with 2.5-3-3 timing
DDR 200 Supports PC1600 module with 2-2-2 timing
Description
The V58C2256(804/404/164)S is a four bank
DDR DRAM organized as 4 banks x 8Mbit x 8 (804),
4 banks x 4Mbit x 16 (164), or 4 banks x 16Mbit x 4
(404). The V58C2256(804/404/164)S achieves high
speed data transfer rates by employing a chip archi-
tecture that prefetches multiple bits and then syn-
chronizes the output data to a system clock.
All of the control, address, circuits are synchro-
nized with the positive edge of an externally sup-
plied clock. I/O transactions are ocurring on both
edges of DQS.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at a higher rate than is possible with standard
DRAMs. A sequential and gapless data rate is pos-
sible depending on burst length, CAS latency and
speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
Package Outline
CK Cycle Time (ns)
Power
Temperature
Mark
JEDEC 66 TSOP II
60 SOC BGA
-6
-7
-75
-8
Std.
L
0C to 70C
Blank
MOSEL VITELIC
V58C2256(804/404/164)S
4
V58C2256(804/404/164)S Rev. 1.4 October 2002
Block Diagram
Row decoder
Memory array
Bank 0
8192 x 1024
x 8
C
o
l
u
m
n
de
c
o
de
r
S
e
n
s
e a
m
pl
i
f
i
e
r
&
I(
O
)
bu
s
Row decoder
Memory array
Bank 1
C
o
l
u
m
n
dec
ode
r
S
ens
e am
pl
i
f
i
e
r
&
I(
O
)
bu
s
Row decoder
Memory array
Bank 2
C
o
l
u
m
n
dec
oder
S
e
n
s
e a
m
pl
i
f
i
e
r
&
I(
O
)
bu
s
Row decoder
Memory array
Bank 3
C
o
l
u
m
n
dec
oder
S
e
ns
e
am
p
l
i
f
i
e
r
&
I
(
O
)
bu
s
Input buffer
Output buffer
DQ
0
-DQ
3
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
A0 - A12, BA0, BA1
A0 - A9, A11, AP, BA0, BA1
Control logic & timing generator
CK
CK
E
CS
RA
S
CA
S
WE
DM
Row Addresses
Column Addresses
DLL
Strobe
Gen.
Data Strobe
CK, CK
CK
DQS
QF
C
8192 x 1024
x 8
8192 x 1024
x 8
8192 x 1024
x 8
64M x 4
V 58 C 2 256(80/40/16) 4 S X T XX
DDR SDRAM
CMOS
2.5V
256Mb, 8K Refresh
4 Banks
COMPONENT
REV LEVEL A=0.14u
COMPONENT
PACKAGE, T = TSOP S=SOC BGA
SSTL
SPEED
MOSEL VITELIC
MANUFACTURED
6 (133MHz@CL2.5))
75(133MHz@CL2.5)
x8, x4, x16
8 (125MHz@CL2.5)
7 (143MHz@CL2.5))
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