MOSEL VITELIC
1
V62C1804096
512K X 8, CMOS STATIC RAM
PRELIMINARY
V62C1804096 Rev. 1.0 October 2001
Features
s
High-speed: 85, 100 ns
s
Ultra low standby current of 2A (max.)
s
Fully static operation
s
All inputs and outputs directly compatible
s
Three state outputs
s
Ultra low data retention current (V
CC
= 1.0V)
s
Operating voltage: 1.8V2.3V
s
Packages
36-Ball CSP BGA (8mm x 10mm)
Description
The V62C1804096 is a very low power CMOS
static RAM organized as 524,288 words by 8 bits.
Easy memory expansion is provided by an active
LOW CE1, and active HIGH CE2, an active LOW
OE, and three static I/O's. This device has an
a u to m a ti c p o w e r -d o w n m o d e f e a tu r e w h e n
deselected.
Device Usage Chart
Operating
Temperature
Range
Package
Outline
Access Time (ns)
Power
Temperature
Mark
B
85
100
L
LL
0C to 70 C
Blank
40C to +85C
I
Functional Block Diagram
Row Decoder
Sense Amp
1024
x
4096
Column Decoder
Input Buffer
Control
Circuit
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
I/O1
I/O
8
OE
WE
CE1
CE2
A
17
A
18
2
V62C1804096 Rev. 1.0 October 2001
MOSEL VITELIC
V62C1804096
Pin Descriptions
A
0
A
18
Address Inputs
These 19 address inputs select one of the 512K x 8
bit segments in the RAM.
CE
1
, CE
2
Chip Enable Inputs
CE
1
is active LOW and CE
2
is active HIGH. Both
chip enables must be active to read from or write to
the device. If either chip enable is not active, the
device is deselected and is in a standby power
mode. The I/O pins will be in the high-impedance
state when deselected.
OE
Output Enable Input
The Output Enable input is active LOW. With chip
enabled, when OE is LOW and WE HIGH, data of
the selected memory location will be available on
the I/O pins. When OE is HIGH, the I/O pins will be
in the high impedance state.
WE
Write Enable Input
The write enable input is active LOW and controls
read and write operations. With the chip enabled,
when WE is HIGH and OE is LOW, output data will
be present at the I/O pins; when WE is LOW and
OE is HIGH, the data present on the I/O pins will be
written into the selected memory locations.
I/O
1
I/O
8
Data Input and Data Output Ports
These 8 bidirectional ports are used to read data
from and write data into the RAM.
V
CC
Power Supply
GND
Ground
Pin Configurations (Top View)
36 BGA
A
1
2
3
4
5
6
1
Note: NC means no connect.
NB means no ball.
2
TOP VIEW
TOP VIEW
3
4
5
6
B
C
D
E
F
G
H
A
A0
I/O5
I/O6
B
C
D
E
F
G
H
VSS
VCC
I/O7
I/O8
A9
A1
A2
NB
NB
NB
NB
OE
A10
CE2
WE
NC
NB
NB
A18
CE1
A11
A3
A4
A5
NB
NB
A17
A16
A12
A6
A7
NB
NB
NB
NB
A15
A13
A8
I/O1
I/O2
VCC
VSS
I/O3
I/O4
A14
MOSEL VITELIC
V62C1804096
3
V62C1804096 Rev. 1.0 October 2001
Part Number Information
Absolute Maximum Ratings
(1)
NOTE:
1.
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Symbol
Parameter
Commercial
Industrial
Units
V
CC
Supply Voltage
-0.5 to + V
CC
+ 0.5
-0.5 to + V
CC
+ 0.5
V
V
N
Input Voltage
-0.5 to + V
CC
+ 0.5
-0.5 to + V
CC
+ 0.5
V
V
DQ
Input/Output Voltage Applied
V
CC
+ 0.3
V
CC
+ 0.3
V
T
BIAS
Temperature Under Bias
-10 to +125
-65 to +135
C
T
STG
Storage Temperature
-55 to +125
-65 to +150
C
SRAM
FAMILY
C = CMOS PROCESS
62 = STANDARD
18 = 1.8V2.3V
OPERATING
VOLTAGE
4096K
ORGANIZATION
PKG
SPEED
62
C
8
18
4096
MOSEL-VITELIC
MANUFACTURED
V
8 = 8-bit
85 ns
100 ns
TEMP.
BLANK = 0
C to 70
C
I = -40
C to +85
C
L = LOW POWER
LL = LOW LOW POWER
T = TSOP STANDARD
B = BGA
DENSITY
PWR.
1
1
80
80
Capacitance*
T
A
= 25C, f = 1.0MHz
NOTE:
1.
This parameter is guaranteed and not tested.
Truth Table
NOTE:
X = Don't Care, L = LOW, H = HIGH
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Output Capacitance
V
I/O
= 0V
8
pF
Mode
CE
1
CE
2
OE
WE
I/O
Operation
Standby
H
X
X
X
High Z
Standby
X
L
X
X
High Z
Output Disable
L
H
H
H
High Z
Read
L
H
L
H
D
OUT
Write
L
H
X
L
D
IN
4
V62C1804096 Rev. 1.0 October 2001
MOSEL VITELIC
V62C1804096
DC Electrical Characteristics
(over all temperature ranges, V
CC
= 1.8V2.3V)
NOTES:
1.
These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2.
V
IL
(Min.) = -3.0V for pulse width < t
RC
/2.
3.
Maximum value.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
V
IL
Input LOW Voltage
(1,2)
-0.3
--
0.4
V
V
IH
Input HIGH Voltage
(1)
1.6
--
V
CC
+0.3
V
I
IL
Input Leakage Current
V
CC
= Max, V
IN
= 0V to V
CC
--
--
1
A
I
OL
Output Leakage Current
V
CC
= Max, CE
1
= V
IH
, V
OUT
= 0V to V
CC
--
--
1
A
V
OL
Output LOW Voltage
V
CC
= Min, I
OL
= 2mA
--
--
0.4
V
V
OH
Output HIGH Voltage
V
CC
= Min, I
OH
= -0.5mA
V
CC
0.4
--
--
V
Symbol
Parameter
Comm.
(3)
Ind.
(3)
Units
I
CC1
Average Operating Current, CE
1
= V
IL
, CE
2
= V
CC
0.2, Output Open,
V
CC
= Max.
f = fmax
25
30
mA
f = 1 MHz
2
3
I
SB
TTL Standby Current
CE
1
>=V
IH
, CE
2
<= V
IL
, V
CC
= Max., f = 0
L
0.4
0.5
mA
LL
0.3
0.3
I
SB1
CMOS Standby Current, CE
1
S V
CC
0.2V, CE
2
0.2V,
V
IN
>= V
CC
0.2V or V
IN
<=0.2V, V
CC
= Max., f = 0
L
5
7
A
LL
2
3
AC Test Conditions
AC Test Loads and Waveforms
Input Pulse Levels
0 to 1.6V
Input Rise and Fall Times
5 ns
Timing Reference Levels
0.9V
Output Load
see below
* Includes scope and jig capacitance
C
L
= 30pF + 1TTL Load
C
L
*
TTL
MOSEL VITELIC
V62C1804096
5
V62C1804096 Rev. 1.0 October 2001
Data Retention Characteristics
NOTES:
1.
t
RC
= Read Cycle Time
2.
T
A
= +25
C.
Low V
CC
Data Retention Waveform (1) (CE
1
Controlled)
Key to Switching Waveforms
Symbol
Parameter
Power
Min.
Typ.
(2)
Max.
Units
V
DR
V
CC
for Data Retention
CE
1
V
CC
0.2V, CE
2
< 0.2V, V
IN
V
CC
0.2V,
or V
IN
0.2V
1.0
--
2.3
V
I
CCDR
Data Retention Current
CE
1
V
DR
0.2V, CE
2
< 0.2V, V
IN
V
CC
0.2V,
or V
IN
0.2V, V
DR
= 1.0V
Com'l
L
--
1
3
A
LL
--
0.5
1.5
Ind.
L
--
--
5
LL
--
--
2
t
CDR
Chip Deselect to Data Retention Time
0
--
--
ns
t
R
Operation Recovery Time (see Retention Waveform)
t
RC
(1)
--
--
ns
V
CC
Data Retention Mode
CE
1
V
CC
0.2V
CE
1
1.6V
1.6V
1.8V
t
CDR
t
R
V
DR
1V
1.8V
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
WILL BE
STEADY
MAY CHANGE
FROM H TO L
WILL BE
CHANGING
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
CHANGING
FROM L TO H
DON'T CARE:
ANY CHANGE
PERMITTED
CHANGING:
STATE
UNKNOWN
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
"OFF" STATE
6
V62C1804096 Rev. 1.0 October 2001
MOSEL VITELIC
V62C1804096
AC Electrical Characteristics
(over all temperature ranges)
Read Cycle
Write Cycle
Parameter
Name
Parameter
85
100
Unit
Min.
Max.
Min.
Max.
t
RC
Read Cycle Time
85
--
100
--
ns
t
AA
Address Access Time
--
85
--
100
ns
t
ACS1
Chip Enable Access Time
--
85
--
100
ns
t
ACS2
Chip Enable Access Time
--
85
--
100
ns
t
OE
Output Enable to Output Valid
--
85
--
40
ns
t
CLZ1
Chip Enable to Output in Low Z
10
--
15
--
ns
t
CLZ2
Chip Enable to Output in Low Z
10
--
15
--
ns
t
OLZ
Output Enable to Output in Low Z
5
--
10
--
ns
t
CHZ
Chip Disable to Output in High Z
--
30
--
35
ns
t
OHZ
Output Disable to Output in High Z
--
30
--
35
ns
t
OH
Output Hold from Address Change
10
--
10
--
ns
Parameter
Name
Parameter
85
100
Unit
Min.
Max.
Min.
Max.
t
WC
Write Cycle Time
85
--
70
--
ns
t
CW
Chip Enable to End of Write
70
--
60
--
ns
t
AS
Address Setup Time
0
--
0
--
ns
t
AW
Address Valid to End of Write
70
--
60
--
ns
t
WP
Write Pulse Width
60
--
50
--
ns
t
WR
Write Recovery Time
5
--
5
--
ns
t
WHZ
Write to Output High-Z
--
25
--
30
ns
t
DW
Data Setup to End of Write
40
--
45
--
ns
t
DH
Data Hold from End of Write
0
--
0
--
ns
MOSEL VITELIC
V62C1804096
7
V62C1804096 Rev. 1.0 October 2001
Switching Waveforms (Read Cycle)
Read Cycle 1
(1, 2)
Read Cycle 2
(1, 2, 4)
Read Cycle 3
(1, 3, 4)
NOTES:
1.
WE = V
IH
.
2.
CE
1
= V
IL
and CE
2
= V
IH
.
3.
Address valid prior to or coincident with CE
1
transition LOW and/or CE
2
transition HIGH.
4.
OE = V
IL
.
5.
Transition is measured 500mV from steady state with C
L
= 5pF. This parameter is guaranteed and not 100% tested.
ADDRESS
OE
I/O
t
RC
t
AA
t
OE
t
OLZ
t
OH
t
OHZ
(5)
ADDRESS
I/O
t
RC
t
AA
t
OH
t
OH
I/O
ADDRESS
CE
1
CE
2
t
ACS1
t
ACS2
t
CLZ1
(5)
t
CLZ2
(5)
t
CHZ
(5)
8
V62C1804096 Rev. 1.0 October 2001
MOSEL VITELIC
V62C1804096
Switching Waveforms (Write Cycle)
Write Cycle 1 (WE Controlled)
(4)
Write Cycle 2 (CE Controlled)
(4)
NOTES:
1.
The internal write time of the memory is defined by the overlap of CE
1
and CE
2
active and WE low. All signals must be active to
initiate and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to
the second transition edge of the signal that terminates the write.
2.
t
WR
is measured from the earlier of CE
1
or WE going high, or CE
2
going LOW at the end of the write cycle.
3.
During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
4.
OE = V
IL
or V
IH
. However it is recommended to keep OE at V
IH
during write cycle to avoid bus contention.
5.
If CE
1
is LOW and CE
2
is HIGH during this period, I/O pins are in the output state. Then the data input signals of opposite phase
to the outputs must not be applied to them.
6.
t
CW
is measured from CE
1
going low or CE
2
going HIGH to the end of write.
ADDRESS
OUTPUT
INPUT
CE
1
CE
2
WE
t
WC
t
CW
(6)
t
CW
(6)
t
DW
t
DH
t
AW
t
WR
(2)
t
WHZ
t
WP
(1)
t
AS
ADDRESS
OUTPUT
High-Z
INPUT
CE
1
CE
2
WE
t
WC
t
DW
t
DH
t
AW
t
CW
(6)
t
CW
(6)
t
WR
(2)
t
AS
(4)
(5)
MOSEL VITELIC
V62C1804096
9
V62C1804096 Rev. 1.0 October 2001
Package Diagrams
36 Ball--8x10 BGA
E1
E
6
5
4
D
A
B
C
D
E
BOTTOM VIEW
SIDE VIEW
aaa
F
G
H
D1
b
SOLDER BALL
3
2
1
e
A
C
A1
SYMBOL
A
A1
b
c
D
D1
E
E1
e
aaa
UNIT.MM
1.05+0.15
0.25
0.05
0.35
.0.05
0.30(TYP)
10.00
0.10
5.25
8.00
0.10
3.75
0.75TYP
0.10
MOSEL VITELIC
WORLDWIDE OFFICES
V62C1804096
MOSEL VITELIC
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461
Copyright , MOSEL VITELIC Inc.
Printed in U.S.A.
The information in this document is subject to change without
notice.
MOSEL VITELIC makes no commitment to update or keep cur-
rent the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applica-
tions. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liabil-
ity for consequential or incidental arising from any use of its prod-
ucts. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
U.S. SALES OFFICES
U.S.A.
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0952
TAIWAN
7F, NO. 102
MIN-CHUAN E. ROAD, SEC. 3
TAIPEI
PHONE: 886-2-2545-1213
FAX: 886-2-2545-1209
NO 19 LI HSIN ROAD
SCIENCE BASED IND. PARK
HSIN CHU, TAIWAN, R.O.C.
PHONE: 886-3-579-5888
FAX: 886-3-566-5888
SINGAPORE
10 ANSON ROAD #23-13
INTERNATIONAL PLAZA
SINGAPORE 079903
PHONE: 65-3231801
FAX: 65-3237013
JAPAN
ONZE 1852 BUILDING 6F
2-14-6 SHINTOMI, CHUO-KU
TOKYO 104-0041
PHONE: 03-3537-1400
FAX: 03-3537-1402
UK & IRELAND
SUITE 50, GROVEWOOD
BUSINESS CENTRE
STRATHCLYDE BUSINESS
PARK
BELLSHILL, LANARKSHIRE,
SCOTLAND, ML4 3NQ
PHONE: 44-1698-748515
FAX: 44-1698-748516
GERMANY
(CONTINENTAL
EUROPE & ISRAEL)
BENZSTRASSE 32
71083 HERRENBERG
GERMANY
PHONE: +49 7032 2796-0
FAX: +49 7032 2796 22
NORTHWESTERN
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0952
SOUTHWESTERN
302 N. EL CAMINO REAL #200
SAN CLEMENTE, CA 92672
PHONE: 949-361-7873
FAX: 949-361-7807
CENTRAL,
NORTHEASTERN &
SOUTHEASTERN
604 FIELDWOOD CIRCLE
RICHARDSON, TX 75081
PHONE: 214-352-3775
FAX: 214-904-9029
PDF 
ZIP