MOSEL VITELIC
1
V827432U24S
2.5 VOLT 32M x 72 HIGH PERFORMANCE
LOW PROFILE (1U) REGISTERED ECC
DDR SDRAM MODULE
PRELIMINARY
V827432U24S Rev. 1.0 December 2002
Features
184 Pin Registered 33,554,432 x 72 bit
Organization DDR SDRAM Modules
Utilizes High Performance 32M x 8 DDR
SDRAM in TSOPII-66 Packages
Single +2.5V ( 0.2V) Power Supply
Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All Inputs, Outputs are SSTL-2 Compatible
8192 Refresh Cycles every 64 ms
Serial Presence Detect (SPD)
1.2 inches (1U) Low Profile Registered DIMM
Description
The V827432U24S memory module is organized
33,554,432 x 72 bits in a 184 pin memory module.
The 32M x 72 memory module uses 9 Mosel-Vitelic
32M x 8 DDR SDRAM. The x72 low profile modules
are ideal for use in high performance computer
systems where increased memory density, fast
access times and small form factors are required.
Component
Used
-6
-7
-75
-8
Units
t
CK
Clock Frequency
(max.)
166
(PC333)
143
(PC266A)
133
(PC266B)
125
(PC200)
MHz
t
AC
Clock Access
Time CAS Latency
= 2.5
6
7
7.5
8
ns
Module Speed
A1
PC1600 (100MHz @ CL2)
B0
PC2100B (133MHz @ CL2.5)
B1
PC2100A (133MHz @ CL2)
C0
PC2700 (166MHz @ CL2.5)
Register
PLL
2
MOSEL VITELIC
V827432U24S
V827432U24S Rev. 1.0 December 2002
Part Number Information
V 8 2 74 32 U 2 4 S X T G - XX
DDRSDRAM
2.5V
WIDTH
DEPTH
184 PIN Registered
DIMM X8 COMPONENT
REFRESH
RATE 8K
4 BANKS
STTL
COMPONENT
REV LEVEL
COMPONENT
PACKAGE, T = TSOP
LEAD FINISH
G = GOLD
SPEED
A1 (100MHz@CL2)
MOSEL VITELIC
MANUFACTURED
B0 (133MHz@CL2.5)
B1 (133MHz@CL2)
C0 (166MHz@CL2.5)
MOSEL VITELIC
V827432U24S
3
V827432U24S Rev. 1.0 December 2002
Block Diagram
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DM
I/O 7
I/O 6
I/O 1
I/O 0
D0
DM0/DQS9
I/O 5
I/O 4
I/O 3
I/O 2
DQ12
DQ13
DQ14
DQ8
DQ9
DQ10
DQ11
DM
I/O 7
I/O 6
I/O 1
I/O 0
D1
I/O 5
I/O 4
I/O 3
DM1/DQS10
DQ20
DQ21
DQ22
DQ23
DQ16
DQ17
DQ18
DQ19
DM
I/O 7
I/O 6
I/O 1
I/O 0
D2
I/O 5
I/O 4
I/O 3
I/O 2
DM2/DQS11
DQ28
DQ29
DQ30
DQ31
DQ24
DQ25
DQ26
DQ27
DM
I/O 7
I/O 6
I/O 1
I/O 0
D3
I/O 5
I/O 4
I/O 3
I/O 2
DM3/DQS12
DQ36
DQ37
DQ38
DQ39
DQ32
DQ33
DQ34
DQ35
DM
I/O 7
I/O 6
I/O 1
I/O 0
D4
DM4/DQS13
I/O 5
I/O 4
I/O 3
I/O 2
DQ44
DQ45
DQ46
DQ47
DQ40
DQ41
DQ42
DQ43
DM
I/O 7
I/O 6
I/O 1
I/O 0
D5
I/O 5
I/O 4
I/O 3
I/O 2
DM5/DQS14
DQ52
DQ53
DQ54
DQ55
DQ48
DQ49
DQ50
DQ51
DM
I/O 7
I/O 6
I/O 1
I/O 0
D6
I/O 5
I/O 4
I/O 3
I/O 2
DQ60
DQ61
DQ62
DQ63
DQ56
DQ57
DQ58
DQ59
DM
I/O 7
I/O 6
I/O 1
I/O 0
D7
I/O 5
I/O 4
I/O 3
I/O 2
DM7/DQS16
RCS0
CS
CS
CS
CS
CS
CS
CS
CS
DQS0
DQS
DQS4
DQS1
DQS5
DQS
DQS2
DQS
DQS3
DQS
DM6/DQS15
DQS6
DQS7
DQ15
I/O 2
CB4
CB5
CB6
CB7
CB0
CB1
CB2
CB3
DM
I/O 7
I/O 6
I/O 1
I/O 0
D8
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS8
DM8/DQS17
DQS
DQS
DQS
DQS
DQS
PCK
RAS
CAS
CKE0
BA0-BAN
A0-A13
R
E
G
I
S
T
E
R
CS0
PCK
R E S E T
RCS0
RBA0 - RBAn
RA0 - RA12
RRAS
RCAS
RCKE0
RWE
BA0 -BAn : SDRAMs DQ0 - D8
A0 -An : SDRAMs D0 - D8
RAS : SDRAMs D0 - D8
CAS : SDRAMs D0 - D8
CKE : SDRAMs D0 - D8
WE: SDRAMs D0 - D8
WE
PLL*
CK0,CK0
* Wire per Clock Loading table/wiring Diagrams
A0
Serial PD
A1
A2
SA0
SA1
SA2
SCL
SDA
W P
V
SS
D0 - D8
D0 - D8
V
DD
/V
DDQ
D0 - D8
D0 - D8
VREF
Strap: see Note 4
V
DDSPD
SPD
4
MOSEL VITELIC
V827432U24S
V827432U24S Rev. 1.0 December 2002
Pin Configurations (Front Side/Back Side)
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
NC
VSS
DQ8
DQ9
DQS1
VDDQ
CK1
CK1
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VDDQ
DQ19
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
Vss
A1
CB0*
CB1*
VDD
DQS8*
A0
CB2*
VSS
CB3*
BA1
Key
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
VDDQ
WE
DQ41
CAS
VSS
DQS5
DQ42
DQ43
VDD
NC
DQ48
DQ49
VSS
CK2
CK2
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
VSS
DQ4
DQ5
VDDQ
DM0
DQ6
DQ7
VSS
NC
NC
A13*
VDDQ
DQ12
DQ13
DM1
VDD
DQ14
DQ15
CKE1
VDDQ
BA2*
DQ20
A12
VSS
DQ21
A11
DM2
VDD
DQ22
A8
DQ23
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
VSS
A6
DQ28
DQ29
VDDQ
DM3
A3
DQ30
VSS
DQ31
CB4*
CB5*
VDDQ
CK0*
CK0*
VSS
DM8*
A10
CB6*
VDDQ
CB7*
key
VSS
DQ36
DQ37
VDD
DM4
DQ38
DQ39
VSS
DQ44
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
RAS
DQ45
VDDQ
CS0
CS1
DM5
VSS
DQ46
DQ47
NC
VDDQ
DQ52
DQ53
NC
VDD
DM6
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
DM7
DQ62
DQ63
VDDQ
SA0
SA1
SA2
VDDSPD
Notes:
* These pins are not used in this module.
Pin Names
Pin Pin
Description
CK1, CK1, CK2, CK2 Differential
Clock
Inputs
CS0
Chip Select Input
CKE0
Clock Enable Input
RAS, CAS, WE Commend
Sets
Inputs
A0 ~ A12
Address
BA0, BA1
Bank Address
DQ0~DQ63 Data
Inputs/Outputs
DQS0~DQS7 Data
Strobe
Inputs/Outputs
DM0~DM7 Data-in
Mask
Key
Key
VDD Power
Supply
VDDQ DQs
Power
Supply
VSS Ground
VREF Reference
Power
Supply
VDDSPD
Power Supply for SPD
SA0~SA2 E
2
PROM Address Inputs
SCL E
2
PROM Clock
SDA E
2
PROM Data I/O
VDDID VDD
Identification
Flag
DU
Do not Use
NC No
Connection
Pin Pin
Description
MOSEL VITELIC
V827432U24S
5
V827432U24S Rev. 1.0 December 2002
Serial Presence Detect Information
Bin Sort:
A1 (PC1600 @ CL2)
B0 (PC2100B @ CL2.5)
B1 (PC2100A @ CL2)
C0 (PC2700 @ CL2.5)
Byte #
Function described
Function Supported
Hex value
A1 B0
B1
C0
A1
B0
B1
C0
0
Defines # of Bytes written into serial memory at module manufactur-
er
128bytes 80h
1
Total # of Bytes of SPD memory device
256bytes
08h
2
Fundamental memory type
SDRAM DDR
07h
3
# of row address on this assembly
13
0Dh
4
# of column address on this assembly
10
0Ah
5
# of module Rows on this assembly
1 Bank
01h
6
Data width of this assembly
72 bits
48h
7
.........Data width of this assembly
-
00h
8
VDDQ and interface standard of this assembly
SSTL 2.5V
04h
9
DDR SDRAM cycle time at CAS Latency =2.5
8ns
7.5ns
7ns
6ns
80h
75h
70h
60h
10
DDR SDRAM Access time from clock at CL=2.5
0.8ns 0.75ns 0.75ns 0.70ns 80h
75h
75h
70h
11
DIMM configuration type(Non-parity, Parity, ECC)
Non-parity, ECC
02h
12
Refresh rate & type
7.8us & Self refresh
82h
13
Primary DDR SDRAM width
x8
08h
14
Error checking DDR SDRAM data width
x8
08h
15
Minimum clock delay for back-to-back random column
address
t
CCD
=1CLK 01h
16
DDR SDRAM device attributes : Burst lengths supported
2,4,8
0Eh
17
DDR SDRAM device attributes : # of banks on each DDR SDRAM
4 banks
04h
18
DDR SDRAM device attributes : CAS Latency supported
2,2.5
0Ch
19
DDR SDRAM device attributes : CS Latency
0CLK
01h
20
DDR SDRAM device attributes : WE Latency
1CLK
02h
21
DDR SDRAM module attributes
Registered address&
control inputs and On-card
DLL
26h
22
DDR SDRAM device attributes : General
+/-0.2V voltage tolerance
00h
23
DDR SDRAM cycle time at CL =2
10ns
10ns
7.5ns
7.5ns
A0h
A0h
75h
75h
24
DDR SDRAM Access time from clock at CL =2
0.8ns 0.75ns 0.75ns 0.70ns 80h
75h
75h
70h
25
DDR SDRAM cycle time at CL =1.5
-
-
-
-
00h
26
DDR SDRAM Access time from clock at CL =1.5
-
-
-
-
00h
27
Minimum row precharge time (=t
RP
)
20ns 20ns 15ns 18ns 50h 50h 3Ch
48h
6
MOSEL VITELIC
V827432U24S
V827432U24S Rev. 1.0 December 2002
28
Minimum row activate to row active delay(=t
RRD
)
15ns 15ns 15ns 12ns
3Ch 3Ch 3Ch
30h
29
Minimum RAS to CAS delay(=t
RCD
)
20ns 20ns 15ns 18ns
50h 50h 3Ch
48h
30
Minimum active to precharge time(=t
RAS
)
50ns 45ns 45ns 42ns
32h 2Dh 2Dh
2Ah
31
Module ROW density
256MB
40h
32
Command and address signal input setup time
1.1ns
0.9ns
0.9ns 0.75ns
B0h
90h
90h
75h
33
Command and address signal input hold time
1.1ns
0.9ns
0.9ns 0.75ns
B0h
90h
90h
75h
34
Data signal input setup time
0.6ns
0.5ns
0.5ns 0.45ns
60h
50h
50h
45h
35
Data signal input hold time
0.6ns
0.5ns
0.5ns 0.45ns
60h
50h
50h
45h
36-40
Superset information (may be used in future)
00h
41
SDRAM device minimum active to active/auto-refresh time
(=t
RC
)
70ns 65ns 65ns
60ns
46h 41h 41h
3Ch
42
SDRAM device minimum active to autorefresh to active/auto-refresh
time (=t
RFC
)
80ns 75ns 75ns
72ns
50h 4Bh 4Bh
48h
43
SDRAM device maximum device cycle time (=t
CK MAX
)
12ns 12ns 12ns
12ns
30h 30h 30h
30h
44
SDRAM device maximum skew between DQS and DQ signals
(=t
DQSQ
)
0.6ns 0.5ns 0.5ns
0.45ns
3Ch 32h 32h
2Dh
45
SDRAM device maximum read datahold skew factor (=t
QHS
)
1ns 0.75ns
0.75ns 0.60ns
A0h 75h 75h
60h
46-61
Superset information (may be used in future)
-
00h
62
SPD data revision code
Initial release
00h
63
Checksum for Bytes 0 ~ 62
-
FFh
3Ah
E2h
63h
64
Manufacturer JEDEC ID code
Mosel Vitelic
40h
65 -71
....... Manufacturer JEDEC ID code
00h
72
Manufacturing location
01h
73-90
Module part number (ASCII)
V827432U24S
91
Manufacturer revison code (For PCB)
0
00
92
Manufacturer revison code (For component)
0
00
93
Manufacturing date (Week)
-
-
94
Manufacturing date (Year)
-
-
95~98 Assembly serial #
-
-
99~127 Manufacturer specific data (may be used in future)
Undefined
00h
128~25
5
Open for customer use
Undefined
00h
Byte #
Function described
Function Supported
Hex value
A1 B0
B1
C0
A1
B0
B1
C0
Serial Presence Detect Information (cont.)
MOSEL VITELIC
V827432U24S
7
V827432U24S Rev. 1.0 December 2002
DC Operating Conditions
(T
A
= 0 to 70C, Voltage referenced to V
SS
= 0V)
Notes: 1. V
DDQ
must not exceed the level of V
DD
.
2. V
IL
(min) is acceptable -1.5V AC pulse width with <= 5ns of duration.
3. The value of V
REF
is approximately equal to 0.5V
DDQ
.
AC Operating Conditions
(T
A
= 0 to 70 C, Voltage referenced to V
SS
= 0V)
Notes: 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of VIX is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the DC level of the
same.
Parameter
Symbol
Min
Typ.
Max
Unit
Note
Power Supply Voltage
V
DD
2.3
2.5
2.7
V
Power Supply Voltage
V
DDQ
2.3
2.5
2.7
V
1
Input High Voltage
V
IH
V
REF
+ 0.15
-
V
DDQ
+ 0.3
V
Input Low Voltage
V
IL
-0.3
-
V
REF
- 0.15
V
2
I/O Termination Voltage
V
TT
V
REF
- 0.04
V
REF
V
REF
+ 0.04
V
Reference Voltage
V
REF
1.15
1.25
1.35
V
3
Input Leakage Current
I
I
-2
-
2
A
Output Leakage Current
IO
z
-5
-
5
A
Output High Current (V
OUT
= 1.95V)
IO
H
-16.8
-
-
mA
Output Low Current (V
OUT
= 0.35V)
IO
L
16.8
-
-
mA
Parameter Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
V
IH(AC)
V
REF
+ 0.31
V
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
V
IL(AC)
V
REF
- 0.31
V
Input Differential Voltage, CK and CK inputs
V
ID(AC)
0.7
V
DDQ
+ 0.6
V
1
Input Crossing Point Voltage, CK and CK inputs
V
IX(AC)
0.5*V
DDQ-0.2
0.5*V
DDQ+0.2
V
2
8
MOSEL VITELIC
V827432U24S
V827432U24S Rev. 1.0 December 2002
AC Operating Test Conditions
(T
A
= 0 to 70C, Voltage referenced to V
SS
= 0V)
Input/Output Capacitance
(V
DD
= 2.5V, V
DDQ
= 2.5V, T
A
= 25C, f = 1MHz)
Parameter Value
Unit
Reference Voltage
V
DDQ
x 0.5
V
Termination Voltage
V
DDQ
x 0.5
V
AC Input High Level Voltage (V
IH
, min)
V
REF
+ 0.31
V
AC Input Low Level Voltage (V
IL
, max)
V
REF
- 0.31
V
Input Timing Measurement Reference Level Voltage
V
REF
V
Output Timing Measurement Reference Level Voltage
V
TT
V
Input Signal maximum peak swing
1.5
V
Input minimum Signal Slew Rate
1
V/ns
Termination Resistor (R
T
) 50
Ohm
Series Resistor (R
S
)
25 Ohm
Output Load Capacitance for Access Time Measurement (C
L
) 30
pF
Parameter
Symbol Min
Max
Unit
Input capacitance (A
0
~ A
11
, BA
0
~ BA
1
, RAS, CAS, WE) CIN
1
60 75
pF
Input capacitance (CKE
0
) CIN
2
40
48
pF
Input capacitance (CS
0
) CIN
3
40
48
pF
Input capacitance (CLK
1
, CLK
2
) CIN
4
30
32
pF
Data & DQS input/output capacitance (DQ
0
~DQ
63
) C
OUT
10
12
pF
Input capacitance (DM0~DM8)
CIN
5
10
12
pF
Output Load Circuit (SSTL_2)
Output
Z0=50
C
LOAD
=30pF
V
REF
=0.5*V
DDQ
R
T
=50
V
tt
=0.5*V
DDQ
MOSEL VITELIC
V827432U24S
9
V827432U24S Rev. 1.0 December 2002
DDR SDRAM I
DD
SPEC TABLE
* Module I
DD
was calculated on the basis of component I
DD
and can be differently measured according to DQ loading cap.
Detailed test conditions for DDR SDRAM IDD1 & IDD
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25' C
2. Worst Case : Vdd = 2.7V, T= 10' C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Symbol
A1
PC1600@CL=2
B0
PC2100B@CL=2.5
B1
PC2100A@CL=2
C0
PC2700A@CL=2.5
Unit
IDD0
810
900
900
990
mA
IDD1
900
1080
1080
1260
mA
IDD2P
135
180
180
225
mA
IDD2F
315
342
342
405
mA
IDD2Q
306
333
333
396
mA
IDD3P
135
180
180
225
mA
IDD3N
540
630
630
720
mA
IDD4R
1350
1710
1710
2070
mA
IDD4W
1170
1530
1530
1890
mA
IDD5
1620
1710
1710
1800
mA
IDD6
Normal
27
27
27
27
mA
Low power
17
17
17
17
mA
IDD7
2250
2700
2700
3150
mA
10
MOSEL VITELIC
V827432U24S
V827432U24S Rev. 1.0 December 2002
AC Characteristics
(AC operating conditions unless otherwise noted)
Parameter Symbol
(PC333) (PC266A)
(PC266B)
(PC200)
Unit Note
Min Max Min Max Min Max Min Max
Row Cycle Time
t
RC
60
- 65
- 65 - 70 - ns
Auto Refresh Row Cycle Time
t
RFC
72
- 75 - 75 - 80 -
ns
Row Active Time
t
RAS
42 120K 45 120K 45 120K 50 120K
ns
Row Address to Column Address Delay
t
RCD
18
- 15
- 20 - 20 - ns
Row Active to Row Active Delay
t
RRD
12
-
15
-
15
-
15
-
ns
Column Address to Column Address Delay
t
CCD
1 - 1 - 1 - 1 -
CLK
Row Precharge Time
t
RP
18
- 15
- 20 - 20 - ns
Write Recovery Time
t
WR
12
- 15 - 15 - 15 -
ns
Last Data-In to Read Command
t
DRL
1 - 1 - 1 - 1 -
CLK
Auto Precharge Write Recovery + Precharge
Time
t
DAL
35 - 35 - 35 - 35 -
ns
System Clock Cycle
Time
CAS Latency = 2.5
t
CK
6 12 7 12
7.5
12 8 12
ns
CAS Latency = 2
7.5
12
7.5
12
10
12
10
12
ns
Clock High Level Width
t
CH
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55
CLK
Clock Low Level Width
t
CL
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55
CLK
Data-Out edge to Clock edge Skew
t
AC
-0.75 0.75 -0.75 0.75 -0.75 0.75 -0.8 0.8 ns
DQS-Out edge to Clock edge Skew
t
DQSCK
-0.75 0.75 -0.75 0.75 -0.75 0.75 -0.8 0.8 ns
DQS-Out edge to Data-Out edge Skew
t
DQSQ
- 0.45 - 0.5 -
0.5
- 0.6
ns
Data-Out hold time from DQS
t
QH
t
HPmin
-0.75ns
- t
HPmin
-0.75ns
- t
HPmin
-0.75ns
- t
HPmin
-0.75ns
- ns 1
Clock Half Period
t
HP
t
CH/L
min
- t
CH/L
min
- t
CH/L
min
- t
CH/L
min
- ns 1
Input Setup Time (fast slew rate)
t
IS
0.75 - 0.9 - 0.9 - 1.1 - ns
2,3,5,6
Input Hold Time (fast slew rate)
t
IH
0.75
- 0.9 - 0.9 - 1.1 - ns
2,3,5,6
Input Setup Time (slow slew rate)
t
IS
0.8 - 1.0 - 1.0 - 1.1 -
ns
2,4,5,6
Input Hold Time (slow slew rate)
t
IH
0.8
- 1.0 - 1.0 - 1.1 - ns
2,4,5,6
Input Pulse Width
t
IPW
0.4 0.6 2.2 - 2.2 - - - ns 6
Write DQS High Level Width
t
DQSH
0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6
CLK
Write DQS Low Level Width
t
DQSL
0.75 1.25 0.4 0.6 0.4 0.6 0.4 0.6
CLK
CLK to First Rising edge of DQS-In
t
DQSS
0.45
- 0.75 1.25 0.75 1.25 0.75 1.25
CLK
Data-In Setup Time to DQS-In (DQ & DM)
t
DS
0.45 - 0.5 - 0.5 - 0.6 - ns 7
Data-in Hold Time to DQS-In (DQ & DM)
t
DH
1.75 - 0.5 - 0.5 - 0.6 - ns 7
DQ & DM Input Pulse Width
t
DIPW
0.9 1.1 1.75 - 1.75 - 2 - ns
Read DQS Preamble Time
t
RPRE
0.4 0.6 0.9 1.1 0.9 1.1 0.9 1.1
CLK
Read DQS Postamble Time
t
RPST
0
- 0.4 0.6 0.4 0.6 0.4 0.6
CLK
MOSEL VITELIC
V827432U24S
11
V827432U24S Rev. 1.0 December 2002
AC Characteristics (cont.)
Notes: 1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, CS, RAS, CAS, WE.
3. For command/address input slew rate >=1.0V/ns
4. For command/address input slew rate >=0.5V/ns and <1.0V/ns
5. CK, CK slew rates are >=1.0V/ns
6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed
by design or tester correlation.
7. Data latched at both rising and falling edges of Data Strobes(DQS) : DQ, DM
8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
Absolute Maximum Ratings
Note: Operation at above absolute maximum rating can adversely affect device reliability
Write DQS Preamble Setup Time
t
WPRES
0.25 - 0 - 0 - 0 -
CLK
Write DQS Preamble Hold Time
t
WPREH
0.4 0.6 0.25 - 0.25 - 0.25 - CLK
Write DQS Postamble Time
t
WPST
2
- 0.4 0.6 0.4 0.6 0.4 0.6
CLK
Mode Register Set Delay
t
MRD
10 - 2 - 2 - 2 -
CLK
Power Down Exit Time
t
PDEX
75 - 10 - 10 - 10 -
ns
Exit Self Refresh to Non-Read Command
t
XSNR
200 - 75 - 75 - 80 -
ns
Exit Self Refresh to Read Command
t
XSRD
200 - 200 - 200 - 200 -
CLK
8
Average Periodic Refresh Interval
t
REFI
- 7.8
- 7.8
- 7.8
- 7.8
us
Parameter Symbol
Rating
Unit
Ambient Temperature
T
A
0
~
70
C
Storage Temperature
T
STG
-55 ~ 125
C
Voltage on Any Pin relative to V
SS
V
IN
, V
OUT
-0.5 ~ 3.6
V
Voltage on V
DD
relative to V
SS
V
DD
-0.5 ~ 3.6
V
Voltage on V
DDQ
relative to V
SS
V
DDQ
-0.5 ~ 3.6
V
Output Short Circuit Current
I
OS
50 mA
Power Dissipation
P
D
11
W
Soldering Temperature Time
T
SOLDER
260 10
C Sec
Parameter Symbol
(PC333) (PC266A)
(PC266B)
(PC200)
Unit Note
Min Max Min Max Min Max Min Max
12
MOSEL VITELIC
V827432U24S
V827432U24S Rev. 1.0 December 2002
Module Dimensions (Low Profile)
All dimensions are typical unless otherwise stated.
Millimeters
Inches
133.35
5.25
1.2
30.48
Register
2.63
.104 max.
1.27
.050
PLL
MOSEL VITELIC
V827432U24S
13
V827432U24S Rev. 1.0 December 2002
Label Information
C
L
= 2.5 (CLK)
t
RCD
= 3 (CLK)
t
RP
= 3 (CLK)
2533
R
Registered DIMM
PC2700
0
SPD Revision
V827432U24SXXX-XX 256MB CLXX
PC2700R-2533-0-XX
XXXX-XXXXXXX
Assembly in Taiwan
X
-
-
MOSEL VITELIC
Part Number
Module Density
DIMM manufacture date code
Criteria of PC2700
CAS Latency
X
-
Gerber file used for this design
"A" : Reference design for raw card A is used for this assembly
"B" : Reference design for raw card B is used for this assembly
"C" : Reference design for raw card C is used for this assembly
"E" : Reference design for raw card C is used for this assembly
"F" : Reference design for raw card C is used for this assembly
"H" : Reference design for raw card C is used for this assembly
"K" : Reference design for raw card C is used for this assembly
"L" : Reference design for raw card C is used for this assembly
"M" : Reference design for raw card C is used for this assembly
"Z" : None of the reference design were used for this assembly
Revision number of the reference design used
"1" : 1st Revision
"2" : 2nd Revision
"3" : 3nd Revision
blank : not applicable
C
L
= 2.5 (CLK)
t
RCD
= 3 (CLK)
t
RP
= 3 (CLK)
2533
R
Registered DIMM
PC2100
08
SPD Revision
0
V827432U24SXXX-XX 256MB CLXX
PC2100R-2533-080-X
XXXX-XXXXXXX
Assembly in Taiwan
X
Gerber file
-
-
-
MOSEL VITELIC
Part Number
Module Density
DIMM manufacture date code
Criteria of PC2100 or PC1600
CAS Latency
14
MOSEL VITELIC
V827432U24S
V827432U24S Rev. 1.0 December 2002
WORLDWIDE OFFICES
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own quality assurance testing appropriate to such applications.
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