MOTOROLA CMOS LOGIC DATA
7
MC14001B
B-Suffix Series CMOS Gates
The B Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure (Complemen-
tary MOS). Their primary use is where low power dissipation and/or high
noise immunity is desired.
Supply Voltage Range = 3.0 Vdc to 18 Vdc
All Outputs Buffered
Capable of Driving Two Lowpower TTL Loads or One Lowpower
Schottky TTL Load Over the Rated Temperature Range.
Double Diode Protection on All Inputs Except: Triple Diode Protection
on MC14011B and MC14081B
PinforPin Replacements for Corresponding CD4000 Series B Suffix
Devices (Exceptions: MC14068B and MC14078B)
L SUFFIX
CERAMIC
CASE 632
ORDERING INFORMATION
MC14XXXBCP
Plastic
MC14XXXBCL
Ceramic
MC14XXXBD
SOIC
TA = 55
to 125
C for all packages.
P SUFFIX
PLASTIC
CASE 646
D SUFFIX
SOIC
CASE 751A
MAXIMUM RATINGS*
(Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage
0.5 to + 18.0
V
Vin, Vout
Input or Output Voltage (DC or Transient)
0.5 to VDD + 0.5
V
lin, lout
Input or Output Current (DC or Transient),
per Pin
10
mA
PD
Power Dissipation, per Package
500
mW
Tstg
Storage Temperature
65 to + 150
_
C
TL
Lead Temperature (8Second Soldering)
260
_
C
* Maximum Ratings are those values beyond which damage to the device may occur.
Temperature Derating:
Plastic "P and D/DW" Packages: 7.0 mW/
_
C From 65
_
C To 125
_
C
Ceramic "L" Packages: 12 mW/
_
C From 100
_
C To 125
_
C
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS
(Vin or Vout)
VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 3
1/94
MC14001B
Quad 2-Input NOR Gate
MC14002B
Dual 4-Input NOR Gate
MC14011B
Quad 2-Input NAND Gate
MC14012B
Dual 4-Input NAND Gate
MC14023B
Triple 3-Input NAND Gate
MC14025B
Triple 3-Input NOR Gate
MC14068B
8-Input NAND Gate
MC14071B
Quad 2-Input OR Gate
MC14072B
Dual 4-Input OR Gate
MC14073B
Triple 3-Input AND Gate
MC14075B
Triple 3-Input OR Gate
MC14078B
8-Input NOR Gate
MC14081B
Quad 2-Input AND Gate
MC14082B
Dual 4-Input AND Gate
MOTOROLA CMOS LOGIC DATA
MC14001B
8
LOGIC DIAGRAMS
1
2
5
6
8
9
12
13
3
4
10
11
1
2
5
6
8
9
12
13
3
4
10
11
1
2
5
6
8
9
12
13
3
4
10
11
1
2
5
6
8
9
12
13
3
4
10
11
2 INPUT
1
2
9
3 INPUT
8
3
4
6
5
11
12
10
13
1
2
9
8
3
4
6
5
11
12
10
13
1
2
9
8
3
4
6
5
11
12
10
13
1
2
9
8
3
4
6
5
11
12
10
13
3
4
1
5
2
4 INPUT
10
11
13
12
9
1
13
1
13
1
13
13
13
3
4
5
2
10
11
12
9
3
4
5
2
10
11
12
9
3
4
5
2
10
11
12
9
5
9
10
4
3
2
11
12
8 INPUT
5
9
10
4
3
2
11
12
NC = 6, 8
NC = 6, 8
NC = 6, 8
NC = 6, 8
NC = 6, 8
NC = 6, 8
VDD = PIN 14
VSS = PIN 7
FOR ALL DEVICES
NOR
MC14001B
Quad 2Input NOR Gate
MC14025B
Triple 3Input NOR Gate
MC14002B
Dual 4Input NOR Gate
MC14078B
8Input NOR Gate
MC14068B
8Input NAND Gate
MC14012B
Dual 4Input NAND Gate
MC14023B
Triple 3Input NAND Gate
NAND
MC14011B
Quad 2Input NAND Gate
OR
MC14071B
Quad 2Input OR Gate
AND
MC14081B
Quad 2Input AND Gate
MC14075B
Triple 3Input OR Gate
MC14073B
Triple 3Input AND Gate
MC14072B
Dual 4Input OR Gate
MC14082B
Dual 4Input AND Gate
MOTOROLA CMOS LOGIC DATA
9
MC14001B
PIN ASSIGNMENTS
11
12
13
14
8
9
10
5
4
3
2
1
7
6
OUTC
OUTD
IN 1D
IN 2D
VDD
IN 1C
IN 2C
OUTB
OUTA
IN 2A
IN 1A
VSS
IN 2B
IN 1B
11
12
13
14
8
9
10
5
4
3
2
1
7
6
IN 2B
IN 3B
IN 4B
OUTB
VDD
NC
IN 1B
IN 3A
IN 2A
IN 1A
OUTA
VSS
NC
IN 4A
11
12
13
14
8
9
10
5
4
3
2
1
7
6
OUTC
OUTD
IN 1D
IN 2D
VDD
IN 1C
IN 2C
OUTB
OUTA
IN 2A
IN 1A
VSS
IN 2B
IN 1B
11
12
13
14
8
9
10
5
4
3
2
1
7
6
IN 2B
IN 3B
IN 4B
OUTB
VDD
NC
IN 1B
IN 3A
IN 2A
IN 1A
OUTA
VSS
NC
IN 4A
11
12
13
14
8
9
10
5
4
3
2
1
7
6
OUTC
IN 1C
IN 2C
IN 3C
VDD
IN 3A
OUTA
IN 2B
IN 1B
IN 2A
IN 1A
VSS
OUTB
IN 3B
11
12
13
14
8
9
10
5
4
3
2
1
7
6
OUTC
IN 1C
IN 2C
IN 3C
VDD
IN 3A
OUTA
IN 2B
IN 1B
IN 2A
IN 1A
VSS
OUTB
IN 3B
11
12
13
14
8
9
10
5
4
3
2
1
7
6
IN 6
IN 7
IN 8
OUT
VDD
NC
IN 5
IN 3
IN 2
IN 1
NC
VSS
NC
IN 4
11
12
13
14
8
9
10
5
4
3
2
1
7
6
OUTC
OUTD
IN 1D
IN 2D
VDD
IN 1C
IN 2C
OUTB
OUTA
IN 2A
IN 1A
VSS
IN 2B
IN 1B
11
12
13
14
8
9
10
5
4
3
2
1
7
6
IN 2B
IN 3B
IN 4B
OUTB
VDD
NC
IN 1B
IN 3A
IN 2A
IN 1A
OUTA
VSS
NC
IN 4A
11
12
13
14
8
9
10
5
4
3
2
1
7
6
OUTC
IN 1C
IN 2C
IN 3C
VDD
IN 3A
OUTA
IN 2B
IN 1B
IN 2A
IN 1A
VSS
OUTB
IN 3B
11
12
13
14
8
9
10
5
4
3
2
1
7
6
IN 6
IN 7
IN 8
OUT
VDD
NC
IN 5
IN 3
IN 2
IN 1
NC
VSS
NC
IN 4
11
12
13
14
8
9
10
5
4
3
2
1
7
6
OUTC
IN 1C
IN 2C
IN 3C
VDD
IN 3A
OUTA
IN 2B
IN 1B
IN 2A
IN 1A
VSS
OUTB
IN 3B
11
12
13
14
8
9
10
5
4
3
2
1
7
6
OUTC
OUTD
IN 1D
IN 2D
VDD
IN 1C
IN 2C
OUTB
OUTA
IN 2A
IN 1A
VSS
IN 2B
IN 1B
11
12
13
14
8
9
10
5
4
3
2
1
7
6
IN 2B
IN 3B
IN 4B
OUTB
VDD
NC
IN 1B
IN 3A
IN 2A
IN 1A
OUTA
VSS
NC
IN 4A
NC = NO CONNECTION
MC14012B
Dual 4Input NAND Gate
MC14023B
Triple 3Input NAND Gate
MC14001B
Quad 2Input NOR Gate
MC14002B
Dual 4Input NOR Gate
MC14011B
Quad 2Input NAND Gate
MC14078B
8Input NOR Gate
MC14082B
Dual 4Input AND Gate
MC14081B
Quad 2Input AND Gate
MC14025B
Triple 3Input NOR Gate
MC14068B
8Input NAND Gate
MC14071B
Quad 2Input OR Gate
MC14072B
Dual 4Input OR Gate
MC14073B
Triple 3Input AND Gate
MC14075B
Triple 3Input OR Gate
MOTOROLA CMOS LOGIC DATA
MC14001B
10
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to VSS)
Characteristic
Symbol
VDD
Vdc
55
_
C
25
_
C
125
_
C
Unit
Characteristic
Symbol
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
Output Voltage
"0" Level
Vin = VDD or 0
VOL
5.0
10
15
--
--
--
0.05
0.05
0.05
--
--
--
0
0
0
0.05
0.05
0.05
--
--
--
0.05
0.05
0.05
Vdc
"1" Level
Vin = 0 or VDD
VOH
5.0
10
15
4.95
9.95
14.95
--
--
--
4.95
9.95
14.95
5.0
10
15
--
--
--
4.95
9.95
14.95
--
--
--
Vdc
Input Voltage
"0" Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
--
--
--
1.5
3.0
4.0
--
--
--
2.25
4.50
6.75
1.5
3.0
4.0
--
--
--
1.5
3.0
4.0
Vdc
"1" Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH
5.0
10
15
3.5
7.0
11
--
--
--
3.5
7.0
11
2.75
5.50
8.25
--
--
--
3.5
7.0
11
--
--
--
Vdc
Output Drive Current
(VOH = 2.5 Vdc)
Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
IOH
5.0
5.0
10
15
3.0
0.64
1.6
4.2
--
--
--
--
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
--
--
--
--
1.7
0.36
0.9
2.4
--
--
--
--
mAdc
(VOL = 0.4 Vdc)
Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
IOL
5.0
10
15
0.64
1.6
4.2
--
--
--
0.51
1.3
3.4
0.88
2.25
8.8
--
--
--
0.36
0.9
2.4
--
--
--
mAdc
Input Current
Iin
15
--
0.1
--
0.00001
0.1
--
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
--
--
--
--
5.0
7.5
--
--
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
--
--
--
0.25
0.5
1.0
--
--
--
0.0005
0.0010
0.0015
0.25
0.5
1.0
--
--
--
7.5
15
30
Adc
Total Supply Current**
(Dynamic plus Quiescent,
Per Gate, CL = 50 pF)
IT
5.0
10
15
IT = (0.3
A/kHz) f + IDD/N
IT = (0.6
A/kHz) f + IDD/N
IT = (0.9
A/kHz) f + IDD/N
Adc
#Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
** The formulas given are for the typical characteristics only at 25
_
C.
To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL 50) Vfk
where: IT is in
A (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per
package.
MOTOROLA CMOS LOGIC DATA
11
MC14001B
BSERIES GATE SWITCHING TIMES
SWITCHING CHARACTERISTICS*
(CL = 50 pF, TA = 25
_
C)
Characteristic
Symbol
VDD
Vdc
Min
Typ #
Max
Unit
Output Rise Time, All BSeries Gates
tTLH = (1.35 ns/pF) CL + 33 ns
tTLH = (0.60 ns/pF) CL + 20 ns
tTLH = (0.40 ns/PF) CL + 20 ns
tTLH
5.0
10
15
--
--
--
100
50
40
200
100
80
ns
Output Fall Time, All BSeries Gates
tTHL = (1.35 ns/pF) CL + 33 ns
tTHL = (0.60 ns/pF) CL + 20 ns
tTHL = (0.40 ns/pF) CL + 20 ns
tTHL
5.0
10
15
--
--
--
100
50
40
200
100
80
ns
Propagation Delay Time
MC14001B, MC14011B only
tPLH, tPHL = (0.90 ns/pF) CL + 80 ns
tPLH, tPHL = (0.36 ns/pF) CL + 32 ns
tPLH, tPHL = (0.26 ns/pF) CL + 27 ns
All Other 2, 3, and 4 Input Gates
tPLH, tPHL = (0.90 ns/pF) CL + 115 ns
tPLH, tPHL = (0.36 ns/pF) CL + 47 ns
tPLH, tPHL = (0.26 ns/pF) CL + 37 ns
8Input Gates (MC14068B, MC14078B)
tPLH, tPHL = (0.90 ns/pF) CL + 155 ns
tPLH, tPHL = (0.36 ns/pF) CL + 62 ns
tPLH, tPHL = (0.26 ns/pF) CL + 47 ns
tPLH, tPHL
5.0
10
15
5.0
10
15
5.0
10
15
--
--
--
--
--
--
--
--
--
125
50
40
160
65
50
200
80
60
250
100
80
300
130
100
350
150
110
ns
* The formulas given are for the typical characteristics only at 25
_
C.
#Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
VDD
14
CL
VSS
7
PULSE
GENERATOR
INPUT
OUTPUT
90%
50%
10%
10%
50%
90%
20 ns
20 ns
tPHL
tPLH
tTLH
tTHL
VOL
VOH
0 V
VDD
INPUT
OUTPUT
INVERTING
* All unused inputs of AND, NAND gates must be connected to VDD.
All unused inputs of OR, NOR gates must be connected to VSS.
90%
50%
10%
VOL
VOH
OUTPUT
NONINVERTING
tTHL
tTLH
tPLH
tPHL
*
Figure 1. Switching Time Test Circuit and Waveforms
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