Document Outline
- Introduction
- 33702 Simplified Application Diagram
- 33702 Simplified Block Diagram
- Pin Function Description
- Maximum Ratings
- Static Electrical Characteristics
- Dynamic Electrical Characteristics
- Electrical Performance Curves
- System/Application Information
- Introduction
- Functional Descriptions
- 33702 Power Sequencing
- I2C Bus Operation
- Application Information
- Package Dimensions
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
33702 Simplified Application Diagram
This document contains information on a product under development.
Motorola reserves the right to change or discontinue this product without notice.
Motorola, Inc. 2003
Order this document from Analog Marketing: MC33702/D
Rev 0, 05/2003
33702
Preliminary Information
ORDERING INFORMATION
Device
Temperature
Range (T
A
)
Package
PC33702DWB/R2
-40 to 85C
32 SOICW
3.0 A Switch-Mode Power Supply
with Linear Regulator
The 33702 provides the means to efficiently supply the Power QUICCTM I,
II, and other families of Motorola microprocessors and DSPs. The 33702
incorporates a high-performance switching regulator, providing the direct
supply for the microprocessor's core, and a low dropout (LDO) linear regulator
control circuit providing the microprocessor I/O and bus voltage.
The switching regulator is a high-efficiency synchronous buck regulator with
integrated 50 m
N-channel power MOSFETs to provide protection features
and to allow space-efficient, compact design.
The 33702 incorporates many advanced features; e.g., precisely
maintained up/down power sequencing, ensuring the proper operation and
protection of the CPU and power system.
Features
Operating Voltage: 2.8 V to 6.0 V
High-Accuracy Output Voltages
Fast Transient Response
Switcher Output Current Up to 3.0 A
Undervoltage Lockout
Power Sequencing
Programmable Watchdog Timer
Voltage Margining via I
2
CTM Bus
Overcurrent Protection
Reset with Programmable Power-ON Delay
Enable Inputs
I
2
C is a trademark of Phillips Corporation.
POWER SUPPLY
INTEGRATED CIRCUIT
O the r
Circuits
ADDR
LDRV
LDO
LFB
CS
RT
RES ET
VDDH (I/Os)
VDDL (Core)
SW
MPC85xx
PG ND
I NV
EN1
MC3 3703
2.8 V to 1 3. 5 V In put
VIN2
VBST
VBD
CLKS YN
CLKS EL
FREQ
Optional
PORESET
0.8 to 5.0 V
0.8 t o 5. 0 V
(Adjustable)
(Adjustable)
VIN1
EN2
GND
BO OT
SDA
SCL
VOUT
VBS T
S R
33702
VIN2
VIN1
VBD
VBST
VOUT
V
LDO
=
V
OUT
=
MPC8XXX
2.8 V to 6.0 V
DWB SUFFIX
CASE 1324-02
32-LEAD SOICW
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33702
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
2
Figure 1. 33702 Simplified Block Diagram
Buck
Control
Logic
+
-
+
-
Thermal
Limit
Current
Limit
Error
Amp.
PWM
Comp.
UVLO
VBST
VDDI
SW
FREQ
Power
Down
Reset
Control
POR
Timer
SysCon
SysCon
INV
EN2
0.8V
(2)
EN1
SoftSt
CLKSYN
VIN2
Buck
HS
&
LS
Driver
VBST
+
-
Vref
Vref
Power
Enable
8.0V
VBST
Boost
Control
VBD
VDDI
LDRV
Vref
LFB
CS
LDO
RT
RESET
VDDI
SDA
SCL
PGND
Reset
VIN1
VIN
BOOT
CLKSEL
VOUT
VLDO
LCMP
Vref
VDDI
Q2
Q1
(2)
(2)
(4)
ADDR
I
2
C
Interface
I
2
C
Control
I
2
C
Control
VDDI
VDDI
Internal
Supply
VDDI
Bandgap
Voltage
Reference
Power
Sequencing
Voltage Margining
W-dog Timer
VBST
Slope
Comp.
VOUT
To Reset
Control
Pow.
Seq.
Switcher
Oscillator
300kHz
VBST
Linear
Regulator
Control
I-lim
PGND
Pow. Seq.
VOUT
Q3
Q4
INV
LFB
Buck
Control
Logic
Buck
Control
Logic
+
-
+
-
+
-
+
-
Thermal
Limit
Current
Limit
Error
Amp.
PWM
Comp.
UVLO
VBST
VDDI
SW
FREQ
Power
Down
Reset
Control
POR
Timer
SysCon
SysCon
INV
EN2
0.8V
(2)
EN1
SoftSt
CLKSYN
VIN2
Buck
HS
&
LS
Driver
Buck
HS
&
LS
Driver
VBST
+
-
+
-
Vref
Vref
Power
Enable
8.0V
VBST
Boost
Control
Boost
Control
VBD
VDDI
LDRV
Vref
LFB
CS
LDO
RT
RESET
VDDI
SDA
SCL
PGND
Reset
VIN1
VIN
BOOT
CLKSEL
VOUT
VLDO
LCMP
Vref
VDDI
Q2
Q1
(2)
(2)
(4)
ADDR
I
2
C
Interface
I
2
C
Control
I
2
C
Control
VDDI
VDDI
Internal
Supply
VDDI
Bandgap
Voltage
Reference
Power
Sequencing
Voltage Margining
W-dog Timer
VBST
Slope
Comp.
Slope
Comp.
VOUT
To Reset
Control
Pow.
Seq.
Switcher
Oscillator
300kHz
VBST
Linear
Regulator
Control
I-lim
Linear
Regulator
Control
I-lim
PGND
Pow. Seq.
VOUT
Q3
Q4
INV
LFB
V
BST
V
IN1
V
IN
V
DDI
V
DDI
V
BST
V
DDI
V
DDI
I
LIM
V
BST
V
BST
V
OUT
V
LDO
V
IN2
V
OUT
V
OUT
PWR Seq.
V
DDI
Watchdog Timer
V
BD
V
DDI
V
BST
PWR Seq.
V
DDI
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33702
3
PIN FUNCTION DESCRIPTION
Pin
Pin Name
Formal Name
Definition
1
FREQ
Oscillator Frequency
This selection switcher pin can be adjusted by connecting external resistor R
F
to the
FREQ pin. The default switching frequency (FREQ pin left open or tied to V
DDI
) is set
to 300 kHz.
2
INV
Inverting Input
Buck Controller Error Amplifier inverting input.
3
V
OUT
Output Voltage
Output voltage of the buck converter. Input pin of the switching regulator power
sequence control circuit.
4, 5
V
IN2
Input Voltage 2
Buck regulator power input. Drain of the high-side power MOSFET.
6, 7
SW
Switch
Buck regulator switching node. This pin is connected to the inductor.
8, 9
24, 25
GND
Ground
Analog ground of the IC, thermal heatsinking.
10, 11
PGND
Power Ground
Buck regulator power ground.
12
V
BD
Boost Drain
Drain of the internal boost regulator power MOSFET.
13
V
BST
Boost Voltage
Internal boost regulator output voltage. The internal boost regulator provides a 20 mA
output current to supply the drive circuits for the integrated power MOSFETs and the
external N-channel power MOSFET of the linear regulator. The voltage at the V
BST
pin
is 8.0 V nominal.
14
BOOT
Bootstrap
Bootstrap capacitor input.
15
SDA
Serial Data
I
2
C bus pin. Serial data.
16
SCL
Serial Clock
I
2
C bus pin. Serial clock.
17
LCMP
Linear Compensation
Linear regulator compensation pin.
18
LFB
Linear Feedback
Linear regulator feedback pin.
19
LDO
Linear Regulator
Input pin of the linear regulator power sequence control circuit.
20
CS
Current Sense
Current sense pin of the LDO. Overcurrent protection of the linear regulator external
power MOSFET. The voltage drop over the LDO current sense resistor R
S
is sensed
between the CS and LDO pins. The LDO current limit can be adjusted by selecting the
proper value of the current sensing resistor R
S
.
21
LDRV
Linear Drive
LDO gate drive of the external pass N-channel MOSFET.
22
V
IN1
Input Voltage 1
The input supply pin for the integrated circuit. The internal circuits of the IC are supplied
through this pin.
CLKSYN
1
EN2
EN1
ADDR
GND
GND
V
DD1
V
IN1
LDRV
CS
LFB
LCMP
LDO
RT
CLKSEL
RESET
FREQ
V
IN2
SW
SW
GND
GND
PGND
PGND
V
BD
V
BST
SDA
SCL
BOOT
V
IN2
INV
V
OUT
8
9
10
11
12
13
14
15
16
3
4
5
6
7
2
32
25
24
23
22
21
20
19
18
17
30
29
28
27
26
31
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33702
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
4
23
V
DDI
Power Supply
Internal supply voltage.
26
ADDR
Address
I
2
C address selection. This pin can be either left open, tied to V
DDI
, or grounded through
a 10 k
resistor.
27
EN1
Enable 1
Enable 1 Input. The combination of the logic state of the Enable 1 and Enable 2 inputs
determine operation mode and type of power sequencing of the IC.
28
EN2
Enable 2
Enable 2 Input. The combination of the logic state of the Enable 1 and Enable 2 inputs
determine operation mode and type of power sequencing of the IC.
29
RT
Reset Timer
This pin allows programming the Power-ON Reset delay by means of an external RC
network.
30
RESET
Reset Overbar
The Reset Control circuit monitors both the switching regulator and the LDO feedback
voltages. It is an open drain output and has to be pulled up to some supply voltage (e.g.,
the output of the LDO) by an external resistor.
31
CLKSEL
Clock Selection
This pin sets the CLKSYN pin either as an oscillator output or synchronization input pin.
The CLKSEL pin is also used for the I
2
C address selection.
32
CLKSYN
Clock Synchronization
Oscillator output/synchronization input pin.
PIN FUNCTION DESCRIPTION (continued)
Pin
Pin Name
Formal Name
Definition
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33702
5
MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
Supply Voltage
V
IN1
, V
IN2
-0.3 to 7.0
V
Switching Node
SW
-1.0 to 7.0
V
Buck Regulator Bootstrap Input (BOOT - SW)
BOOT
-0.3 to 8.5
V
Boost Regulator Output
V
BST
-0.3 to 8.5
V
Boost Regulator Drain
V
BD
-0.3 to 9.5
V
RESET
Drain Voltage
RESET
-0.3 to 7.0
V
Enable Pins (EN1, EN2)
-0.3 to 7.0
V
Logic Pins (SDA, SCL, CLKSYN)
-0.3 to 7.0
V
Analog Pins (INV, V
OUT
, RESET)
-0.3 to 7.0
V
Analog Pins (LDRV
,
LFB, LDO, LCMP, CS)
-0.3 to 8.5
V
Analog Pins (CLKSEL, ADDR, RT, FREQ, V
DDI
)
-0.3 to 3.6
V
ESD Voltage
Human Body Model
(Note 1)
Machine Model
(Note 2)
V
ESD1
V
ESD2
2000
200
V
Storage Temperature
T
STG
-65 to 150
C
Power Dissipation (T
A
= 85C)
(Note 3)
P
D
TBD
W
Lead Soldering Temperature
(Note 4)
T
SOLDER
260
C
Maximum Junction Temperature
T
JMAX
125
C
Thermal Resistance, Junction to Ambient
(Note 5)
R
JA
68
C/W
Thermal Resistance, Junction to Base
(Note 6)
R
JB
18
C/W
OPERATING CONDITIONS
Supply Voltage (V
IN1
, V
IN2
)
V
IN1
, V
IN2
2.8 to 6.0
V
Operational Package Temperature (Ambient Temperature)
T
A
-40 to 85
C
Notes
1.
ESD1 testing is performed in accordance with the Human Body Model (C
ZAP
=100 pF, R
ZAP
=1500
).
2.
ESD2 testing is performed in accordance with the Machine Model (C
ZAP
=200 pF, R
ZAP
=0
).
3.
Maximum power dissipation at indicated junction temperature.
4.
Lead soldering temperature limit is for 10 seconds maximum duration. Contact Motorola Sales Office for device immersion soldering time/
temperature limits.
5.
Thermal resistance measured in accordance with EIA/JESD51-2.
6.
Theoretical thermal resistance from the die junction to the exposed pins.
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33702
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
6
STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions -40C
T
J
125
C unless otherwise noted. Input voltages V
IN1
= V
IN2
= 3.3 V using the typical
application circuit (see
Figure 20
) unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
GENERAL
Operating Voltage Range (V
IN1
, V
IN2
)
V
IN
2.8
6.0
V
Start-Up Voltage Threshold (Boost Switching)
V
ST
1.6
1.8
V
V
BST
Undervoltage Lockout
V
BST_UVLO
6.0
V
Input DC Supply Current (Normal Operation Mode, Enabled)
I
IN
60
mA
V
IN1
Pin Input Supply Current (EN1 = EN2 = 0)
I
IN1
9.0
mA
V
IN2
Pin Input Leakage Current (EN1 = EN2 = 0)
I
IN2
TBD
A
V
DDI
Internal Supply Voltage
V
DDI
3.0
3.3
V
V
DDI
Maximum Output Current
I
DDI
TBD
A
BUCK CONVERTER
Buck Converter Output Voltage Range
I
VOUT
= 30 mA to 3.0 A, V
IN1
= V
IN2
= 2.8 V to 6.0 V
V
OUT
0.8
5.0
V
Buck Converter Feedback Voltage
I
VOUT
= 30 mA to 3.0 A, V
IN1
= V
IN2
= 2.8 V to 6.0 V. No R
B
Resistor.
Includes Load Regulation Error
V
INV
0.784
0.8
0.816
V
Buck Converter Voltage Margining Step
V
MVO
1.0
%
Buck Converter Line Regulation
V
IN1
= V
IN2
= 2.8 V to 6.0 V, I
VOUT
= 3.0 A
REG
LNVO
-1.0
1.0
%
Buck Converter Load Regulation
I
VOUT
= 30 mA to 3.0 A
REG
LDVO
-1.0
1.0
%
V
OUT
Input Leakage Current
V
OUT
= 5.0 V
I
VOUTLK
TBD
A
High-Side Power MOSFET Q1 R
DS(ON)
I
D
= 1.0 A, T
A
= 25C, V
BST
= 8.0 V
R
DS(ON)
50
m
Low-Side Power MOSFET Q2 R
DS(ON)
I
D
= 1.0 A, T
A
= 25C, V
BST
= 8.0 V
R
DS(ON)
50
m
Buck Converter Peak Current Limit (High Level)
I
H_LIM
3.4
4.5
6.0
A
Buck Converter Valley Current Limit (Low Level)
I
L_LIM
1.7
2.25
3.0
A
V
OUT
Pull-Down MOSFET Q3 Current Limit
T
A
= 25C, V
BST
= 8.0 V
I
Q3_LIM
2.0
A
V
OUT
Pull-Down MOSFET Q3 R
DS(ON)
I
D
= 1.0 A, T
A
= 25C, V
BST
= 8.0 V
R
DS(ON)
1.0
Thermal Shutdown (Switcher, V
OUT
FET)
T
SD
150
170
190
C
Thermal Shutdown Hysteresis
T
SDHys
15
C
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33702
7
ERROR AMPLIFIER (BUCK CONVERTER)
Input Impedance
(Note 7)
R
IN
500
k
Output Impedance
(Note 7)
R
OUT
150
DC Open Loop Gain
(Note 7)
A
VOL
80
dB
Gain Bandwidth Product
(Note 7)
GBW
35
MHz
Slew Rate
(Note 7)
SR
200
V/
s
Output Voltage Swing High Level
V
IN1
> 3.3 V, I
OEA
= -1.0 mA
(Note 7)
V
EA_OH
2.0
V
Output Voltage Swing Low Level
I
OEA
= -1.0 mA
(Note 7)
V
EA_OL
0.4
V
Slope Compensation Ramp
(Note 7)
V
SCRamp
0.6
V
OSCILLATOR
Oscillator Low Level Output Voltage (Pin CLKSYN), CLKSEL Open
V
OSC_OL
0.4
V
Oscillator High Level Output Voltage (Pin CLKSYN), CLKSEL Open
V
OSC_OH
3.0
V
Oscillator Input Voltage Threshold (Pin CLKSYN), CLKSEL Grounded
V
OSC_IH
1.2
1.6
2.0
V
Oscillator Frequency Adjusting Reference Voltage (FREQ)
V
FREQ
1.29
V
Oscillator Frequency Adjusting Resistor Range
R
FREQ
100
200
k
BOOST REGULATOR
Boost Regulator Output Voltage
I
BST
= 20 mA, V
IN1
= V
IN2
= 2.8 V to 6.0 V
V
BST
7.5
8.0
8.5
V
Boost Regulator Start-Up Voltage
V
IN_BSU
1.6
1.8
V
Boost Regulator Peak Current Limit (Power FET Peak Current)
I
P_BD
0.75
1.0
1.5
A
Boost Regulator Power FET Valley Current Limit (Low Level)
I
L_BD
450
600
800
mA
Boost Power FET R
DS(ON)
I
BD
= 1.0 A, T
A
= 25C
R
DS(ON)
150
400
m
Boost Regulator Recommended Output Capacitor
C
BST
10
F
Boost Regulator Recommended Output Capacitor Maximum ESR
ESR
CBST
100
m
Notes
7.
Design information only. It is not production tested.
STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions -40C
T
J
125
C unless otherwise noted. Input voltages V
IN1
= V
IN2
= 3.3 V using the typical
application circuit (see
Figure 20
) unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
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33702
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
8
LINEAR REGULATOR (LDO)
LDO Output Voltage Range
V
IN1
= V
IN2
= 2.8 V to 6.0 V, I
LDO
= 10 mA to 1000 mA
V
LDO
0.8
5.0
V
LDO Feedback Voltage, LFB Pin Connected to LDO Pin
V
IN1
= V
IN2
= 2.8 V to 6.0 V, I
LDO
= 10 mA to 1000 mA. Includes Load
Regulation Error
V
LDO
0.784
0.8
0.816
V
LDO Voltage Margining Step Size
V
MLDO
1.0
%
LDO Line Regulation
V
IN1
= V
IN2
= 2.8 V to 6.0 V, I
LDO
= 1000 mA
REG
LNVLDO
-1.0
1.0
%
LDO Load Regulation
I
LDO
= 10 mA to 1000 mA
REG
LDVLDO
-1.0
1.0
%
LDO Ripple Rejection, Dropout Voltage V
DO
= 1.0 V, V
RIPPLE
= +1.0 V p-p
Sinusoidal, f = 300 kHz, I
LDO
= 500 mA
V
LDO_RR
40
dB
LDO Maximum Dropout Voltage (V
IN
- V
LDO
)
V
LDO
= 2.5 V, I
LDO
= 1000 mA
V
DO
TBD
V
LDO Current Sense Comparator Threshold Voltage (V
CS
- V
LDO
)
V
CSTH
35
45
55
mV
LDO Pin Input Current
I
LDO
1.6
2.0
2.4
mA
LDO Feedback Input Current (LFB Pin)
I
LFB
-5.0
5.0
A
LDO Drive Output Current (LDRV
Pin)
I
LDRV
2.0
3.6
5.0
mA
LDO Drive Current Limit (LDRV Pin)
I
DRLIM
3.6
mA
CS Pin Input Leakage Current
V
CS
= 5.0 V
I
CSLK
50
300
A
LDO Error Amplifier Input Impedance (LFB Pin)
R
IN
TBD
LDO Error Amplifier Output Impedance (LCMP Pin)
R
OUT
TBD
LDO Pull-Down MOSFET Q4 Current Limit
T
A
= 25C, V
BST
= 8.0 V (LDO Pin)
I
Q4_LIM
-2.0
A
LDO Pull-Down MOSFET Q4 R
DS(ON)
I
D
= 1.0 A, T
A
= 25C, V
BST
= 8.0 V
R
DS(ON)
1.0
LDO Recommended Output Capacitance
C
LDO
10
F
LDO Recommended Output Capacitor ESR
ESR
CLDO
TBD
m
Thermal Shutdown (LDO Pull-Down FET Q4)
T
SD
150
170
190
C
Thermal Shutdown Hysteresis
T
SDHys
15
C
STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions -40C
T
J
125
C unless otherwise noted. Input voltages V
IN1
= V
IN2
= 3.3 V using the typical
application circuit (see
Figure 20
) unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33702
9
CONTROL AND SUPERVISORY CIRCUITS
Enable (EN1, EN2) Input Voltage Threshold
V
TH_EN
1.2
1.6
2.0
V
Enable (EN1, EN2) Input Voltage Threshold Hysteresis
V
IHYS
0.1
V
Enable (EN1, EN2) Pull-Down Resistance
R
PU
30
60
120
k
RESET
Low-Level Output Voltage, I
OL
= 5.0 mA
V
OL
0.4
V
RESET
Leakage Current, OFF State
,
Pulled Up to 5.0 V
I
LKG-RST
10
A
RESET
Undervoltage Threshold on V
OUT
(
V
OUT
/V
OUT)
(Note 8)
V
OUTITh
-10
-7.5
-5.0
%
RESET
Overvoltage Threshold on V
OUT
(
V
OUT
/V
OUT)
(Note 8)
V
OUTITh
5.0
7.5
10
%
RESET
Undervoltage Threshold on V
LDO
(
V
LDO
/V
LDO)
(Note 8)
V
LDOITh
-10
-7.5
-5.0
%
RESET
Overvoltage Threshold on V
LDO
(
V
LDO
/V
LDO)
(Note 8)
V
LDOITh
5.0
7.5
10
%
Reset Timer Voltage Threshold
V
TH-RT
TBD
1.2
TBD
V
Reset Timer Source Current
I
S-RT
20
30
mA
Reset Timer Leakage Current
I
LKG-RT
-1.0
1.0
A
Reset Timer Saturation Voltage, Reset Timer Current = 300
A
V
SAT-RT
100
TBD
mV
Maximum Value of the Reset Timer Capacitor
C
t
47
F
CLKSEL Threshold Voltage
V
th
CLKS
1.2
1.6
2.0
V
CLKSEL Pull-Up Resistance
R
PU-CLKS
60
120
240
k
ADDR Threshold Voltage
V
th
ADDR
1.2
1.6
2.0
V
ADDR Pull-Up Resistance
R
PU-ADDR
60
120
240
k
SDA, SCL Pins I
2
C Bus (STANDARD)
Input Threshold Voltage
V
Ith
1.3
1.7
V
Input Voltage Threshold Hysteresis
V
IHYS
0.2
V
SDA, SCL Input Current, Input Voltage = 0.4 V to 6.0 V
I
I
10
A
SDA Low-Level Output Voltage, 3.0 mA Sink Current
V
OL
0.4
V
SCA, SCL Capacitance
C
I
10
pF
Notes
8.
This parameter does not include the tolerance of the external resistor divider.
STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions -40C
T
J
125
C unless otherwise noted. Input voltages V
IN1
= V
IN2
= 3.3 V using the typical
application circuit (see
Figure 20
) unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
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33702
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
10
DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions -40C
T
J
125
C unless otherwise noted. Input voltages V
IN1
= V
IN2
= 3.3 V using the typical
application circuit (see
Figure 20
) unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
BUCK CONVERTER
Duty Cycle Range (Normal Operation)
D
0
90
%
Switching Node SW Rise Time
(Note 9)
I
LOAD
= 3.0 A
t
RISE
TBD
ns
Switching Node SW Fall Time
(Note 9)
I
LOAD
= 3.0 A
t
FALL
TBD
ns
Maximum Deadtime
(Note 9)
t
D
TBD
ns
Buck Control Loop Propagation Delay
(Note 9)
V
INV
< 0.8 V to V
SW
> 90% of High Level or V
INV
> 0.8 V to V
SW
< 10% of
Low Level
t
PD
50
ns
Soft Start Duration (Power Sequencing Disabled, EN1 = 1, EN2 = 1)
t
SS
200
350
800
s
Fault Condition Timeout
t
FAULT
10
ms
Retry Timer Cycle
t
R
et
100
ms
OSCILLATOR
Oscillator Default Frequency (Switching Frequency), FREQ Pin Open
f
OSC
270
300
330
kHz
Oscillator Frequency Range
f
OSC
200
400
kHz
Oscillator Frequency Accuracy
R
F
= 100 k
f
OSC
360
400
440
kHz
Oscillator Frequency Accuracy
R
F
= 200 k
f
OSC
180
200
220
kHz
Oscillator Output Signal Duty Cycle (Square Wave, 180 Out-of-Phase with the
Internal Suitable Oscillator)
D
OSC
50
%
Synchronization Pulse Minimum Duration
t
SYNC
300
ns
BOOST REGULATOR
Boost Regulator FET Maximum ON Time
t
ON
24
s
Boost Regulator Control Loop Propagation Delay
(Note 9)
t
BST_PD
50
ns
Boost Switching Node V
BD
Rise Time
(Note 9)
I
BST
= 20 mA
t
B_RISE
15
40
ns
Boost Switching Node V
BD
Fall Time
(Note 9)
I
BST
= 20 mA
t
B_FALL
15
40
ns
Notes
9.
Design Information only. Not production tested.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33702
11
Timing Diagram
Figure 2. Definition of Time on the I
2
C Bus
DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions -40C
T
J
125
C unless otherwise noted. Input voltages V
IN1
= V
IN2
= 3.3 V using the typical
application circuit (see
Figure 20
) unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
LINEAR REGULATOR (L
DO
)
LDO Output Current Slew Rate
I
SR
TBD
mA/
s
Fault Condition Timeout
t
FAULT
1.0
ms
Retry Timer Cycle
t
R
et
100
ms
SCA, SCL PIN, I
2
C BUS (STANDARD)
SCL Clock Frequency
f
SCL
0
100
kHz
Bus Free Time Between a STOP and a START Condition
t
BUF
4.7
s
Hold Time (Repeated) START Condition (After this period, the first clock pulse
is generated.)
t
HD-STA
4.0
s
Low Period of the SCL Clock
t
LOW
4.7
s
High Period of the SCL Clock
t
HIGH
4.0
s
SDA Fall Time from V
IH_MAX
to V
IL_MIN
, Bus Capacitance 10 pF to 400 pF,
3.0 mA Sink Current
t
F
250
ns
Setup Time for a Repeated START Condition
t
SU-STA
4.7
s
Data Hold Time for I
2
C bus devices
(Note 10)
,
(Note 11)
t
HD-DAT
0
s
Data Setup Time
t
SU-DAT
250
ns
Setup Time for STOP Condition
t
SU-STO
4.0
s
Capacitive Load for Each Bus Line
C
B
400
pF
Notes
10.
Design Information only. Not production tested.
11.
The device provides an internal hold time of at least 300 ns for the SDA signal (refer to the V
IH_MIN
of the SCL signal) to bridge the undefined
region of the falling edge of SCL.
t
SU-STO
t
SU-STA
t
HD-STA
t
SU-DAT
t
HD-DAT
t
HD-STA
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33702
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
12
Electrical Performance Curves
Figure 3. Buck R
DS(ON)
(Temp)
Figure 4. F
OSC
(R
F
)
Figure 5. Buck Efficiency
Figure 6. I
LIM
(Temp)
Figure 7. Vref (Temp)
Figure 8. RT Timer (R
t
, C
t
)
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33702
13
SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33702 power supply integrated circuit provides the
means to efficiently supply the Power QUICC and other families
of Motorola microprocessors. It incorporates a high-
performance synchronous buck regulator, supplying the
microprocessor's core, and a low dropout (LDO) linear regulator
providing the microprocessor I/O and bus voltages.
This device incorporates many advanced features; e.g.,
precisely maintained up/down power sequencing, ensuring the
proper operation and protection of the CPU and power system.
At the same time, it provides high flexibility of configuration,
allowing the maximum optimization of the power supply system.
FUNCTIONAL DESCRIPTION
Switching Regulator
The switching regulator is a high-frequency (300 kHz default,
adjustable in the range from 200 kHz to 400 kHz), synchronous
buck converter driving integrated high-side and low-side
N-channel power MOSFETs. The switching regulator output
voltage is adjustable by means of an external resistor divider to
provide the required output voltage within plus/minus two
percent accuracy, and it is intended to directly power the core
of the microprocessor. The buck controller utilizes a Sensorless
PWM Current Mode Control topology to achieve excellent line
rejection, stabilize the feedback loop, and provide cycle-by-
cycle current limiting.
A typical bootstrap technique is used to provide voltage
necessary to properly enhance the high-side MOSFET gate.
When the regulator is supplied only from low-input voltage
(e.g., single +3.3 V supply rail), the bootstrap capacitor is
charged from the internal boost regulator output V
BST
through
an external diode. This arrangement allows the 33702 to
operate from very low input voltage and also comply with the
power sequencing requirements of the supplied
microcontroller.
To avoid destruction of the supplied circuits, a current limit
with retry capability was implemented in the switching regulator.
When an overcurrent condition occurs and the switch current
reaches the peak current limit value, the main (high-side) switch
is turned off until the inductor current decays to the valley value,
which is one-half of the peak current limit. If an overcurrent
condition exists for 10 ms, the buck regulator control circuit
shuts the switcher OFF and the switcher retry timer starts to
time out. When the timer expires after 100 ms, the switcher
engages the start-up sequence and runs for 10 ms, repeatedly
checking for the overcurrent condition. During the current
limited operation (e.g., in case of short circuit on the switching
regulator output), the switching regulator operation is not
synchronized to the oscillator frequency.
The output voltage V
OUT
can be adjusted by means of an
external resistor divider connected to the feedback control pin
INV. The switching regulator output voltage can be adjusted in
the range of 0.8 V to 5.0 V, but the V
OUT
output voltage is
always lower than the input voltage to the regulator. Power-up,
power-down, and fault management are coordinated with the
linear regulator.
Thermal Shutdown
To increase the overall safety of the system designed with
the 33702, an internal thermal shutdown function has been
incorporated into the switching regulator circuit. The 33702
senses the temperature of the buck regulator main switching
FET (high-side FET Q1; see
Figure 1
), the low-side
(synchronous FET Q2), and control circuit. If the temperature of
any of the monitored components exceeds the limit of safe
operation (thermal shutdown), the switching regulator will be
shut down. After the temperature falls below the value given by
the thermal shutdown hysteresis window, the switcher will retry
to operate again.
The V
OUT
pull-down FET Q3 has an independent thermal
shutdown control. When the Q3 temperature exceeds the
thermal shutdown limit, the Q3 will be turned off without
affecting the switcher operation.
Soft Start
A switching regulator soft start feature is incorporated in the
33702. The soft start is active each time the IC is enabled, V
IN
is reapplied, or after a fault retry. Other transient events do not
activate the soft start.
Boost Regulator
A boost regulator provides a high voltage necessary to
properly drive the buck regulator power MOSFETs, especially
during the low input voltage condition. The LDO regulator
external N-channel MOSFET gate is also powered from the
boost regulator. In order to properly enhance the high-side
MOSFETs when only a +3.3 V supply rail powers the integrated
circuit, the boost regulator provides an output voltage of 8.0 V
nominal value.
The 33702 boost regulator uses a simple hysteretic current
control technique, which allows fast power-up and does not
require any compensation. When the boost regulator main
power switch (low side) is turned on, the current in the inductor
starts to ramp up. After the inductor current reaches the upper
current limit (nominally set at 1.0 A), the low-side switch is
turned off and the current charges the output capacitor through
the internal rectifier. When the inductor current falls below the
valley current limit value (nominally 600 mA), the low-side
switch is turned on again, starting the next switching cycle. After
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33702
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
14
the boost regulator output capacitor reaches its regulation limit,
the low-side switch is turned off until the output voltage falls
below the regulation limit again.
Oscillator
A 300 kHz (default) oscillator sets the switching frequency of
the buck regulator. The frequency of the oscillator can be
adjusted between 200 kHz and 400 kHz by an optional external
resistor R
F
connected from the FREQ pin of the integrated
circuit to ground. See
Figure 4
for frequency resistor selection.
The CLKSYN pin can be configured either as an oscillator
output when the CLKSEL pin is left open or it can be used as a
synchronization input when the CLKSEL pin is grounded. The
oscillator output signal is a square wave logic signal with
50 percent duty cycle, 180 degrees out-of-phase with the
internal clock signal. This allows opposite phase
synchronization of two 3370x devices.
When the CLKSYN pin is used as synchronization input
(CLKSEL pin grounded), the external resistor R
F
chosen from
the chart in
Figure 4
should be used to synchronize the internal
slope compensation ramp to the external clock. Operation is
only recommended between 200 kHz and 400 kHz. The
supplied synchronization signal does not need to be 50 percent
duty cycle. Minimum pulse width is 300 ns.
Low Dropout Linear Regulator (LDO)
The adjustable low dropout linear regulator (LDO) is capable
of supplying a 1.0 A output current. It has a current limit with
retry capability. When the voltage measured across the current
sense resistor reaches the 45 mV threshold, the control circuit
limits the current for 1.0 ms and if the overcurrent condition still
exists the linear regulator is turned off. At the same time the
overcurrent condition is detected, the Retry Timer starts to time
out. When the timer expires after 100 ms, the LDO tries to
power up again for 1.0 ms, repeatedly checking for the
overcurrent condition. The current limit of the LDO can be set
by using the following formula:
I
LIM
= 45 mV/R
S
Where R
S
is the LDO current sense resistor, connected
between the CS pin and the LDO pin output (see
Figure 20
).
When no current sense resistor is used, it is still possible to
detect the overcurrent condition by tying the current sense pin
CS to the V
BST
voltage. In this case, the overcurrent condition
is sensed by saturation of the linear regulator driver buffer.
The output voltage of the LDO can be adjusted by means of
an external resistor divider connected to the feedback control
pin LFB. The linear regulator output voltage can be adjusted in
the range of 0.8 V to 5.0 V, but the LDO output voltage is always
lower than the input voltage to the regulator. Power-up, power-
down, and fault management are coordinated with the
switching regulator.
Thermal Shutdown
The LDO pull-down FET Q4 has an independent thermal
shutdown control. When the Q4 temperature exceeds the
thermal shutdown limit, the Q4 will be turned off without
affecting the LDO operation.
Voltage Margining
The 33702 includes a voltage margining feature accessed
through the I
2
C bus. Voltage margining allows for independent
adjustment of the Switcher V
OUT
voltage and the linear output
V
LDO
. Each can be adjusted up and down in 1% steps to a
range of 7%. This feature allows for worst case system
validation; i.e., determining the design margin. Margining
details are described in the section entitled
I
2
C Bus Operation
,
beginning on page 19 of this datasheet.
RESET
The
RESET
pin is an open drain output. The Reset Control
circuit supervises both output voltages--the linear regulator
output V
LDO
and the switching regulator output V
OUT
. When
either of these two regulators is out of regulation (high or low),
the
RESET
pin is pulled low. There is a 20
s delay filter
preventing erroneous resets. During power-up sequencing,
RESET
is held low until the Reset Timer times out.
Reset Timer Power-Up Delay (RT)
The Reset Timer Power-Up Delay (RT) pin is used to set the
delay between the time when the LDO and switcher outputs are
active and stable and the release of the
RESET
output. An
external resistor and capacitor are used to program the timer.
The power-up delay can be obtained by using the following
formula:
T
D
= 10 ms + R
t
C
t
Where R
t
is the Reset Timer programming resistor and C
t
is the
Reset Timer programming capacitor, both connected in parallel
from RT to ground.
Note Observe the maximum C
t
value and expect reduced
accuracy if R
t
is less than 10 k
.
Watchdog Timer
A watchdog function is available via I
2
C bus communication.
It is possible to select either window watchdog or time-out
watchdog operation, as illustrated in
Figure 9
on page 15.
Watchdog time-out starts when the watchdog function is
activated via I
2
C bus sending a Watchdog Programming
command byte, thus determining watchdog operation (window
or time-out) and period duration (refer to
Table 1
, page 15). If
the watchdog is cleared by receiving a new Watchdog
Programming command through the I
2
C bus, the watchdog
timer is reset and the new time-out period begins. If the
watchdog time expires, the
RESET
will become active (LOW)
for a time determined by the RC components of the RT timer
plus 10 ms. After a watchdog time-out, the function is no longer
active.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33702
15
Figure 9. Watchdog Operation
Table 1. Watchdog Programming Command Byte
(as a 2nd Command Byte)
When the Window Watchdog function is selected, the timer
cannot be cleared during the Closed Window time, which is
50% of the total watchdog period. When the watchdog is
cleared, the timer is reset and starts a new time-out period. If
the watchdog is not cleared during the Open Window time, the
RESET
will become active (LOW) for a time determined by the
RC components of the RT timer plus 10 ms.
EN1 and EN2 Control Pins
These two pins permit positive logic control of the Enable
function and selection of the Power Sequencing mode
concurrently.
Table 2
depicts the EN1 and EN2 function and
Power Sequencing mode selection.
Both EN1 and EN2 pins have internal pull-down resistors
and both can withstand a short circuit to the supply voltage,
6.0 V.
Table 2. Operating Mode Selection
Power Sequencing Modes
The power sequencing of the two outputs of this power
supply IC is in compliance with the Motorola Power QUICC and
other 32-bit microprocessor requirements. When the input
voltage is applied, the switcher and linear regulator outputs
follow the supply rail voltage during power-up and power-down
in the limits given by the microcontroller power sequencing
specification, illustrated in
Figures 10
through
12
. There are two
possible power sequencing modes, Standard and Inverted, as
explained in more detail below. The third mode of operation is
Power Sequencing Disabled.
Figure 10. Standard Power Up/Down Sequence
in +3.3 V Supply System
Figure 11. Standard Power Up/Down Sequence
in +5.0 V Supply System
Address
Value
Action
0
1
1
0
0
0
0
0
1st Command
0
1
1
0
0
0
0
0
WD OFF
(Note 12)
0
1
1
0
1
0
0
0
WD 1280 ms
WinOFF
0
1
1
0
1
0
0
1
WD 320 ms
WinOFF
0
1
1
0
1
0
1
0
WD 80 ms
WinOFF
0
1
1
0
1
0
1
1
WD 20 ms
WinOFF
0
1
1
0
1
1
0
0
WD 1280 ms
WinON
0
1
1
0
1
1
0
1
WD 320 ms
WinON
0
1
1
0
1
1
1
0
WD 80 ms
WinON
0
1
1
0
1
1
1
1
WD 20 ms
WinON
Notes
12.
The Watchdog feature will be turned
ON automatically after receiving any
other valid command byte changing
watchdog time.
50% of Watchdog Period
Watchdog Period
Timing Selected via 1
2
C Bus See Table 1
Watchdog Closed
No Watchdog Clear Allowed
Window Open
for Watchdog Clear
Window Open for Watchdog Clear
Watchdog Period
Timing Selected via I
2
C Bus See Table 1
Window Watchdog
Time-Out Watchdog
EN1
EN2
Operating Mode
0
0
Regulators Disabled
0
1
Standard Power Sequencing
1
0
Inverted Power Sequencing
1
1
Regulators Enabled,
No Power Sequencing
V = 2.0 V
Max. Lead
V = 0.4 V
Max. Lag
V = 2.0 V
Max. Lead
Slope
1.0 V/ms
(typ.)
V Start-Up
3.3 V Input Supply (I/O Voltage)
1.8 V Core Voltage
V = 2.0 V
Max. Lead
V = 0.4 V
Max. Lag
V = 0.4 V
Max. Lag
V Start-Up
3.3 V I/O Voltage (V
LDO
)
1.8 V Core Voltage
(V
OUT
)
5.0 V Input Supply
V = 2.0 V
Max. Lead
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33702
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
16
Figure 12. Inverted Power Up/Down Sequence in +5.0 V
Supply System
Standard Power Sequencing
When the power supply IC operates in the Standard Power
Sequencing mode, the switcher output provides the core
voltage for the microprocessor. This situation and operating
conditions are illustrated in
Figure 10
and
Figure 11
.
Table 2
,
page 15, shows the Power Sequencing mode selection.
Inverted Power Sequencing
When the power supply IC is operating in the Inverted Power
Sequencing mode, the linear regulator (LDO) output provides
the core voltage for the microprocessor, as illustrated in
Figure 12
.
Table 2
shows the Power Sequencing mode
selection.
33702 POWER SEQUENCING
Requirements
1. I/O supply voltage not to exceed core voltage by more than
2.0 V.
2. Core supply voltage not to exceed I/O voltage by more
than 0.4 V.
Methods of Control
The 33702 has several methods of monitoring and
controlling the regulator output voltages, as described in the
paragraphs below. Power sequencing control is also achieved
through the intrinsic operation of the regulators. The EN1 and
EN2 pins can be used to disable the power sequencing (refer to
Table 2
, page 15.
Intrinsic Operation
For both the LDO and switcher, whenever the output voltage
is below the regulation point, the LDO external Pass FET will be
on or the Buck High-Side FET will be on at a duty cycle
controlled by the switcher. Because these devices are FETs,
current can flow in either direction, balancing the voltages via
the common supply pin. The ability to maintain the FETs on will
depend on the available gate voltage, and thus the size of the
boost regulator storage capacitor.
Standard Power Sequencing Control
Comparators monitor voltage differences between the LDO
(LDO pin) and the switcher (V
OUT
pin) outputs as follows:
1. LDO > V
OUT
+ 1.8 V, turn off LDO. The LDO can be
forced off. This occurs whenever the LDO output voltage
exceeds the switcher output voltage by more than 1.8 V.
2. LDO > V
OUT
+ 1.9 V, shunt LDO to ground. If turning off
the LDO is insufficient and the LDO output voltage
exceeds the switcher output voltage by more than 1.9 V,
a 1.0
shunt FET is turned on that discharges the LDO
load capacitor to ground. The shunt FET is used for
switcher output shorts to ground and for power down in
case of V
IN1
V
IN2
with the switcher output falling faster
than the LDO.
3. LDO < V
OUT
+ 1.7 V, cancel (1) and (2) above, re-enable
LDO. Normal operation resumes when the LDO output
voltage is less than 1.7 V above the switcher output
voltage.
4. LDO < V
OUT
- 0.2 V, turn off switcher. The switcher can
be forced off. This occurs whenever the LDO is less than
V
OUT
- 0.2 V.
5. LDO < V
OUT
- 0.3 V, turn on Sync (LS) FET and 1.0
V
OUT
sink FET. The Buck High-Side FET is forced off and
the Sync FET is forced on. This occurs when the switcher
output voltage exceeds the LDO output by more than
300 mV.
6. LDO > V
OUT
, reset (4) and (5) above. Normal operation
resumes when LDO > V
OUT
.
V = 2.0 V
Max. Lead
V = 0.4 V
Max. Lag
V = 0.4 V
Max. Lag
V Start-Up
3.3 V I/O Voltage (V
OUT
)
1.8 V Core Voltage(V
LDO
)
5.0 V Input Supply
V = 2.0 V
Max. Lead
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33702
17
Inverted Power Sequencing Control
Comparators monitor voltage differences between the
switcher (V
OUT
pin) and LDO (LDO pin) outputs as follows:
1. V
OUT
> LDO + 1.8 V, turn off V
OUT
. The switcher V
OUT
can be forced off. This occurs whenever the V
OUT
output
voltage exceeds the LDO output voltage by more than
1.8 V.
2. V
OUT
> LDO + 1.9 V, shunt V
OUT
to ground. If turning off
the switcher V
OUT
is insufficient and the V
OUT
output
voltage exceeds the LDO output voltage by more than
1.9 V, a 1.0
shunt FET is turned on that discharges the
V
OUT
load capacitor to ground. The shunt FET is used for
LDO output shorts to ground and for power-down in case
of V
IN1
V
IN2
with LDO output falling faster than the
V
OUT
.
3. V
OUT
< LDO + 1.7 V, cancel (1) and (2) above, re-enable
V
OUT
. Normal operation resumes when the V
OUT
output
voltage is less than 1.7 V above the LDO output voltage.
4. V
OUT
< LDO - 0.2 V, turn off LDO. The LDO can be
forced off. This occurs whenever the V
OUT
is less than
V
LDO
- 0.2 V.
5. V
OUT
< LDO - 0.3 V, turn on the 1.0
LDO sink FET.
This occurs when the LDO output voltage exceeds the
V
OUT
output by more than 300 mV.
6. V
OUT
> LDO, reset (4) and (5) above. Normal operation
resumes when V
OUT
> LDO.
Standard Operating Mode
1. Single 3.3 V Supply, V
IN
= V
IN1
= V
IN2
= 3.3 V
The 3.3 V supplies the microprocessor I/O voltage, the
switcher supplies core voltage (e.g., 1.8 V nominal), and the
LDO operates independently (see
Figure 10
, page 15). Power
sequencing depends only on the normal switcher intrinsic
operation to control the Buck High-Side FET.
Power Up
When V
IN
is rising, initially V
OUT
will be below the regulation
point and the Buck High-Side FET will be on. In order not to
exceed the 2.0 V differential requirement between the I/O (V
IN
)
and the core (V
OUT
), the switcher must start up at 2.0 V or less
and be able to maintain the 2.0 V or less differential. The
maximum slew rate for V
IN
is 1.0 V/ms.
Power Down
When V
IN
is falling, V
OUT
will be below the regulation point;
therefore the Buck High-Side FET will be on. In the case where
V
OUT
is falling faster than V
IN
, the Buck High-Side FET will
attempt to maintain V
OUT
. In the case where V
IN
is falling faster
than V
OUT
, the Buck High-Side FET is also on, and the V
OUT
load capacitor will be discharged through the Buck High-Side
FET to V
IN
. Thus, provided V
IN
does not fall too fast, the core
voltage (V
OUT
) will not exceed the I/O voltage (V
IN
) by more
than a maximum of 0.4 V.
Shorted Load
1. V
OUT
shorted to ground. This will cause the I/O voltage to
exceed the core voltage by more than 2.0 V. No load
protection.
2. V
IN
shorted to ground. Until the switcher load
capacitance is discharged, the core voltage will exceed
the I/O voltage by more than 0.4 V. By the intrinsic
operation of the switcher, the load capacitor will be
discharged rapidly through the Buck High-Side FET to
V
IN
.
3. V
OUT
shorted to supply. No load protection. 33702
protected by current limit and thermal limit.
2. Single 5.0 V Supply, V
IN1
= V
IN2
, or Dual Supply V
IN1
V
IN2
The LDO supplies the microprocessor I/O voltage. The
switcher supplies the core (e.g., 1.8 V nominal) (see
Figure 11
,
page 15).
Power Up
This condition depends upon the regulator current limit, load
current and capacitance, and the relative rise times of the V
IN1
and V
IN2
supplies. There are 2 cases:
1. LDO rises faster than V
OUT
. The LDO uses control
methods (1) and (2) described in the
Methods of Control
section, page 16.
2. V
OUT
rises faster than LDO. The switcher uses control
methods (4) and (5) described in the
Methods of Control
section, page 16.
Power Down
This condition depends upon the regulator load current and
capacitance and the relative fall times of the V
IN1
and V
IN2
supplies. There are 2 cases:
1. V
OUT
falls faster than LDO. The LDO uses control
methods (1) and (2) described in the
Methods of Control
section, page 16.
In the case V
IN1
= V
IN2
, the intrinsic operation will turn on
both the Buck High-Side FET and the LDO external Pass
FET, and will discharge the LDO load capacitor into the V
IN
supply.
2. LDO falls faster than V
OUT
. The switcher uses control
methods (4) and (5) described in the
Methods of Control
section, page 16.
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33702
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
18
Shorted Load
1. V
OUT
shorted to ground. The LDO uses method (1) and
(2) described in the
Methods of Control
section, page 16.
2. LDO shorted to ground. The switcher uses control
methods (4) and (5) described in the
Methods of Control
section, page 16.
3. V
IN1
shorted to ground. This is equivalent to the LDO
output shorted to ground.
4. V
IN2
shorted to ground. This is equivalent to the switcher
output shorted to ground.
5. V
OUT
shorted to supply. No load protection. 33702
protected by current limit and thermal limit.
6. LDO shorted to supply. No load protection. 33702
protected by current limit and thermal limit.
Inverted Operating Mode
1. Single 3.3 V Supply, V
IN
= V
IN1
= V
IN2
= 3.3 V
The 3.3 V supplies the microprocessor I/O voltage, the LDO
supplies core voltage (e.g., 1.8 V nominal), and the switcher
V
OUT
operates independently. Power sequencing depends only
on the normal LDO intrinsic operation to control the Pass FET.
Power Up
When V
IN
is rising, initially LDO will be below the regulation
point and the Pass FET will be on. In order not to exceed the
2.0 V differential requirement between the I/O (V
IN
) and the
core (LDO), the LDO must start up at 2.0 V or less and be able
to maintain the 2.0 V or less differential. The maximum slew
rate for V
IN
is 1.0 V/ms.
Power Down
When V
IN
is falling, LDO will be below the regulation point;
therefore the Pass FET will be on. In the case where LDO is
falling faster than V
IN
, the Pass FET will attempt to maintain
LDO. In the case where V
IN
is falling faster than LDO, the Pass
FET is also on, and the LDO load capacitor will be discharged
through the Pass FET to V
IN
. Thus, provided V
IN
does not fall
too fast, the core voltage (LDO) will not exceed the I/O voltage
(V
IN
) by more than maximum of 0.4 V.
Shorted Load
1. LDO shorted to ground. This will cause the I/O voltage to
exceed the core voltage by more than 2.0 V. No load
protection.
2. V
IN
shorted to ground. Until the LDO load capacitance is
discharged, the core voltage will exceed the I/O voltage
by more than 0.4 V. By the intrinsic operation of the LDO,
the load capacitor will be discharged rapidly through the
Pass FET to V
IN
.
3. LDO shorted to supply. No load protection.
2. Single 5.0 V Supply, V
IN1
= V
IN2
, or Dual Supply V
IN1
V
IN2
The switcher V
OUT
supplies the microprocessor I/O voltage.
The LDO supplies the core (e.g., 1.8 V nominal) (see
Figure 12
,
page 16).
Power Up
This condition depends upon the regulator current limit, load
current and capacitance, and the relative rise times of the V
IN1
and V
IN2
supplies. There are 2 cases:
1. V
OUT
rises faster than LDO. The switcher V
OUT
uses
control methods (4) and (5) described in the
Methods of
Control
section,
page 17.
2. LDO rises faster than V
OUT
. The LDO uses control
methods (1) and (2) described in the
Methods of Control
section,
page 17.
Power Down
This condition depends upon the regulator load current and
capacitance and the relative fall times of the V
IN1
and V
IN2
supplies. There are 2 cases:
1. LDO falls faster than V
OUT
. The V
OUT
uses control
methods (4) and (5) described in the
Methods of Control
section,
page 17.
In the case V
IN1
= V
IN2
the intrinsic operation will turn both
the Buck High-Side FET and the LDO external Pass FET,
and will discharge the V
OUT
load capacitor into the V
IN
supply.
2. V
OUT
falls faster than LDO. The LDO uses control
methods (1) and (2) described in the
Methods of Control
section,
page 17.
Shorted Load
1. LDO shorted to ground. The V
OUT
uses methods (4) and
(5) described in the
Methods of Control
section,
page 17.
2. V
OUT
shorted to ground. The LDO uses control methods
(1) and (2) described in the Methods of Control section.
3. V
IN1
shorted to ground. This is equivalent to the LDO
output shorted to ground.
4. V
IN2
shorted to ground. This is equivalent to the switcher
V
OUT
output shorted to ground.
5. LDO shorted to supply. No load protection.
6. V
OUT
shorted to supply. No load protection. 33702
protected by current limit and thermal limit.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33702
19
I
2
C BUS OPERATION
Introduction
The 33702 device is compatible with the I
2
C interface
standard. SDA and SCL pins are the Serial Data and Serial
Clock pins of the I
2
C bus.
I
2
C Command and Data Formats
Communication Start
Communication starts with a START condition, followed by
the slave device unique address.
Figure 13
illustrates the data
transfer beginning an I
2
C communication for a 7-bit slave
address.
Figure 13. Communication Using 7-Bit Address
Slave Address Definition
33702 has the two LSB's address bits defined by the state of
the CLKSEL pin and the ADDR pin.
Note The state of the CLKSEL pin also defines the
configuration of the oscillator synchronization CLKSYN pin.
This feature allows up to four 33702 ICs to communicate in
the same I
2
C bus, all of them sharing the same high-order
address bits. A different combination of bits A1 and A0 is
assigned to each individual part to assure its unique address.
Figure 14
illustrates the flexible addressing feature for a 7-bit
address.
Table 3
provides the definition of the selectable
portion of the device address.
Figure 14. Address Bit Definition for 7-Bit Address
Writing Data Into the Slave Device
After the address acknowledgment by the slave, DATA can
be written into the slave registers. The R/W bit must be set to 0
so DATA will be read.
Figure 15
shows the data write
sequence. Actions performed by the slave device are grayed.
Figure 15. Data Transfer for Write Operations
Data Definition
For the sake of 33702 acting as a slave device, the master
writes a Command Byte and writes one Data Byte. The
Command Byte identifies the kind of operation required by the
master and has two fields, as illustrated in
Figure 16
:
1. Address field
2. Value field
The address field is selected from the list in
Table 4
.
Figure 16. Command Byte
Table 4. Address Field Definitions
Refer to
Table 5
, page 20, which summarizes the value field
definitions for the entire set of operation options.
S
7-Bit Address
R/W
Ack
1 0
2
3
4
5
6
1 1 1 0 1 A1 A0
Bits
Fixed Address Selectable
Address
Table 3. Definition of Selectable Portion of Device Address
CLKSEL Pin
ADDR Pin
A1
A0
Low
Low
0
0
Low
Open
0
1
Open
Low
1
0
Open
Open
1
1
Code
Operation
Write
001
Voltage Margining
W
010
Not Used
011
Watchdog
W
S
7-Bit Address
0
Ack
DATA
Ack
D6 D5 D4 D3
D1 D0
Bits
Address Field
Value Field
7
D7
D2
3
2 1
0
4
5
6
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33702
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
20
Table 5. Command Byte Definitions
Security in Writing Commands
All writing operations are critical and must not be
inadvertently latched after a false command. To improve the
security level, a so-called first command is defined to initiate
each write communications.
A first command has the Command Byte address field equal
to the related operation one, followed by a null value field (all
zeros).
Table 6
summarizes first command definitions. The
master sends the first command before the Command Byte for
the intended operation.
Voltage Margining Operation
After starting the communication in Writing mode, the master
sends the first command followed by the specific Command
Byte to set the required voltage margining for either the LDO or
the switcher (see
Figure 17
). To achieve a simultaneous set for
both LDO and switcher, two specific commands must be issued
in sequence after the first command, one for each supply.
Figure 17. Voltage Margining Programming
(One Supply Only)
Note x bits are defined in
Table 5
.
Watchdog Programming Operation
For watchdog operation control, the master periodically
sends a watchdog first command followed by a command byte
selecting, or confirming, the watchdog period according to the
options listed in
Table 5
. Also see
Figure 18
.
The internal watchdog timer will be cleared each time a
watchdog command is written into the device, provided it
arrives during the window open time. The Command 01100000
sent twice will shut the time OFF, and the watchdog function will
be disabled. Any other valid watchdog command turns on the
timer again.
Figure 18. Watchdog Timer Programming
Note x bits are defined in
Table 5
.
Operation
Address
Value
Action
Voltage Margining
(As a 2nd
Command Byte)
0
0
1
0
0
0
0
0
1st Command
0
0
1
x
0
0
0
0 Output Normal
0
0
1
x
0
0
0
1
+ 1%
0
0
1
x
0
0
1
0
+ 2%
0
0
1
x
0
0
1
1
+ 3%
0
0
1
x
0
1
0
0
+ 4%
LDO Output: x=0
0
0
1
x
0
1
0
1
+ 5%
Switcher Output
x=1 0
0
1
x
0
1
1
0
+ 6%
0
0
1
x
0
1
1
1
+ 7%
0
0
1
x
1
0
0
1
- 1%
0
0
1
x
1
0
1
0
- 2%
0
0
1
x
1
0
1
1
- 3%
0
0
1
x
1
1
0
0
- 4%
0
0
1
x
1
1
0
1
- 5%
0
0
1
x
1
1
1
0
- 6%
0
0
1
x
1
1
1
1
- 7%
Watchdog
Programming
(As a 2nd
Command Byte)
0
1
1
0
0
0
0
0
1st Command
0
1
1
0
0
0
0
0
WD OFF
(Note 13)
0
1
1
0
1
0
0
0
WD 1280 ms
WinOFF
0
1
1
0
1
0
0
1
WD 320 ms
WinOFF
0
1
1
0
1
0
1
0
WD 80 ms
WinOFF
0
1
1
0
1
0
1
1
WD 20 ms
WinOFF
0
1
1
0
1
1
0
0
WD 1280 ms
WinON
0
1
1
0
1
1
0
1
WD 320 ms
WinON
0
1
1
0
1
1
1
0
WD 80 ms
WinON
0
1
1
0
1
1
1
1
WD 20 ms
WinON
Notes
13.
The Watchdog feature will be turned ON automatically
after receiving any other valid command byte changing
watchdog time.
Table 6. First Command Definitions
First Command
Operation
001 00000
Voltage Margining
011 00000
Watchdog Programming
0 0
0 0 0 0 0
1
0
0
1
x
x
x
x
x
First Byte for Voltage Margining
Command Byte
Ack
0 1
0 0 0 0 0
1
1
0
1
x
x
x
x
x
First Byte for Watchdog Programming
Command Byte
Ack
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33702
21
Communication Stop
Only the master can terminate the data transfer by issuing a
STOP condition. The slave waits for this condition to resume its
initial state waiting for the next START condition (see
Figure 19
).
Data Transfer Example
The master device controlling the I
2
C bus will always start
addressing a 33702 slave IC in writing mode (R/W = 0) in order
to be able to write a Command Byte just after the address
acknowledge. I
2
C bus protocol defines this circumstance as a
master-transmitter and slave-receiver configuration.
Eventually this Command Byte can again define a Write
operation (e.g., Voltage Margining, see
Figure 19
), and the
master will keep the data transfer direction.
Figure 19
illustrates a communication beginning with the
slave address, the first command for voltage margining, and a
third byte containing the address field 001 and the value field
00101 corresponding with the LDO fifth setting (LDO output
voltage = +5% above its nominal value). If a simultaneous
setting for switcher is needed, a fourth byte should be included
before the STOP condition (P); for instance, 001 10010 to set
switcher in its second setting (switcher output voltage = +2%
above its nominal value).
Figure 19. Complete Data Transfer Example
START
Slave Address
Write
First Command for Voltage Margining
Address Field Value Field = LDO
5
th
Setting
STOP
P
Ack
A6
A4
A0
0
0
1
0
0
0
Ack
0
0
Ack
0
0
1 0
0
1
0
1
S
A5
A3 A2 A1
0
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33702
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
22
APPLICATION INFORMATION
Figure 20. Simplified Block Diagram and Typical Application
50 uF
Buck
Control
Logic
+
-
+
-
Thermal
Limit
Current
Limit
Error
Amp.
PWM
Comp.
UVLO
VBST
VDDI
SW
FREQ
Power
Down
Reset
Control
POR
Timer
SysCon
SysCon
INV
EN2
GND
0.8V
R
b
(2)
EN1
SoftSt
CLKSYN
Supply
Voltage
V
OUT
= 1.8V
VIN2
Buck
HS
&
LS
Driver
VBST
+
-
Vref
Vref
Power
Enable
8.0V
VBST
Boost
Control
VBD
10uF
VDDI
LDRV
Vref
LFB
CS
LDO
V
LDO
= 2.5V
@ 1.0A
+3.3V
RT
RESET
Reset
to MCU
V
LDO
Supply
Voltage
+3.3V
VDDI
R
S
SDA
SCL
Ct
PGND
Reset
R
F
4.7 uH
10uH
VIN1
VIN
BOOT
CLKSEL
VOUT
VLDO
C
B
LCMP
VBST
L1
C
O
C
IN
Vref
VDDI
Q2
Q1
(2)
(2)
(4)
ADDR
I
2
C
Interface
Rt
I
2
C
Control
I
2
C
Control
C
LDO
5 x 2.2 uF
C
BST
D
B
Q
LDO
L
BST
0.1uF
VDDI
R
pd
10k
VDDI
Internal
Supply
VDDI
Bandgap
Voltage
Reference
Power
Sequencing
Voltage Margining
W-dog Timer
VBST
Slope
Comp.
VOUT
To Reset
Control
Pow.
Seq.
Switcher
Oscillator
300kHz
C
IN
VBST
Linear
Regulator
Control
I-lim
+3.3V
or
VOUT
100pF
1.5k
2 x 10 uF
10uF
6.8nF
?pF
?k
?k
?k
?
(Optional)
5.1k
100k
100nF
1.0 uF
0.068 R
@
Pow. Seq.
?k
?k
Q3
Q4
INV
LFB
50 uF
Buck
Control
Logic
Buck
Control
Logic
+
-
+
-
+
-
+
-
Thermal
Limit
Current
Limit
Error
Amp.
PWM
Comp.
UVLO
VBST
VDDI
SW
FREQ
Power
Down
Reset
Control
POR
Timer
SysCon
SysCon
INV
EN2
GND
0.8V
R
b
(2)
EN1
SoftSt
CLKSYN
Supply
Voltage
V
OUT
= 1.8V
VIN2
Buck
HS
&
LS
Driver
Buck
HS
&
LS
Driver
VBST
+
-
+
-
Vref
Vref
Power
Enable
8.0V
VBST
Boost
Control
Boost
Control
VBD
10uF
VDDI
LDRV
Vref
LFB
CS
LDO
V
LDO
= 2.5V
@ 1.0A
+3.3V
RT
RESET
Reset
to MCU
V
LDO
Supply
Voltage
+3.3V
VDDI
R
S
SDA
SCL
Ct
PGND
Reset
R
F
4.7 uH
10uH
VIN1
VIN
BOOT
CLKSEL
VOUT
VLDO
C
B
LCMP
VBST
L1
C
O
C
IN
Vref
VDDI
Q2
Q1
(2)
(2)
(4)
ADDR
I
2
C
Interface
Rt
I
2
C
Control
I
2
C
Control
C
LDO
5 x 2.2 uF
C
BST
D
B
Q
LDO
L
BST
0.1uF
VDDI
R
pd
10k
VDDI
Internal
Supply
VDDI
Bandgap
Voltage
Reference
Power
Sequencing
Voltage Margining
W-dog Timer
VBST
Slope
Comp.
Slope
Comp.
VOUT
To Reset
Control
Pow.
Seq.
Switcher
Oscillator
300kHz
C
IN
VBST
Linear
Regulator
Control
I-lim
Linear
Regulator
Control
I-lim
+3.3V
or
VOUT
100pF
1.5k
2 x 10 uF
10uF
6.8nF
?pF
?k
?k
?k
?
(Optional)
5.1k
100k
100nF
1.0 uF
0.068 R
@
Pow. Seq.
?k
?k
Q3
Q4
INV
LFB
3.0 A
V
IN1
V
IN
V
BST
V
DDI
V
DDI
V
BST
V
DDI
V
DDI
V
BST
V
IN2
V
OUT
V
OUT
PWR Seq.
V
BST
V
DDI
V
DDI
V
BST
V
LDO
V
OUT
V
DDI
V
BD
V
BST
PWR Seq.
4.7
H
0.1
F
5 x 2.2
F
10
H
10
F
10
F
V
LDO
50
F
+3.3 V
Supply
Voltage
+3.3 V
Supply
Voltage
V
OUT
= 1.8 V
@ 3.0 A
V
LDO
= 2.5 V
@ 1.0 A
V
LDO
+3.3 V or
RESET
to MCU
2 x 10
F
I
LIM
R
t
C
t
I
2
C
I
2
C
Watchdog Timer
I
2
C
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Freescale Semiconductor, Inc.
For More Information On This Product,
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33702
23
PACKAGE DIMENSIONS
NOTES:
1.
ALL DIMENSIONS ARE IN MILLIMETERS.
2.
DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3.
DATUMS B AND C TO BE DETERMINED AT THE PLANE
WHERE THE BOTTOM OF THE LEADS EXIT THE
PLASTIC BODY.
4.
THIS DIMENSION DOES NOT INCLUDE MOLD FLASH,
PROTRUSION OR GATE BURRS. MOLD FLASH,
PROTRUSION OR GATE BURRS SHALL NOT EXCEED
0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED
AT THE PLANE WHERE THE BOTTOM OF THE LEADS
EXIT THE PLASTIC BODY.
5.
THIS DIMENSION DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSIONS. INTERLEAD FLASH AND
PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER
SIDE. THIS DIMENSION IS DETERMINED AT THE
PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE
PLASTIC BODY.
6.
THIS DIMENSION DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.4
MM PER SIDE. DAMBAR CANNOT BE LOCATED ON
THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSION AND ADJACENT LEAD
SHALL NOT LESS THAN 0.07 MM.
7.
EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8.
THESE DIMENSIONS APPLY TO THE FLAT SECTION
OF THE LEAD BETWEEN 0.10 MM AND 0.3 MM FROM
THE LEAD TIP.
9.
THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM. THIS DIMENSION IS
DETERMINED AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE
BAR BURRS, GATE BURRS AND INTER-LEAD FLASH,
BUT INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
CL
10.9
7.4
1
16
17
32
0.10
A
2.35
SEATING
PLANE
0.9
SECTION B-B
0.65
R0.08 MIN
B
A
PIN 1 ID
(0.29)
0.38
0.25
(0.203)
PLATING
BASE METAL
SECTION A-A
ROTATED 90 CLOCKWISE
8
0.19
0.22
9
5
0.13
M
C A
M
B
6
A
C
7.6
11.1
9
4
10.3
5.15
A
32X
30X
2.65
0.3 A
2X 16 TIPS
B C
B
B
0.29
0.13
0.5
0
8
0
0.25
GAUGE PLANE
MIN
DWB SUFFIX
32-LEAD SOIC WIDE BODY
PLASTIC PACKAGE
CASE 1324-02
ISSUE A
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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HOW TO REACH US:
USA/EUROPE/LOCATIONS NOT LISTED:
JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center
Motorola Literature Distribution
3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573, Japan
P.O. Box 5405, Denver, Colorado 80217
81-3-3440-3569
1-800-521-6274 or 480-768-2130
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre
2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong
852-26668334
HOME PAGE: http://motorola.com/semiconductors
MC33702/D
Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied
copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee
regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product
or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be
provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating
parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license
under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product
could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated
with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their
respective owners.
Motorola, Inc. 2003
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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