Äîêóìåíòàöèÿ è îïèñàíèÿ www.docs.chipfind.ru

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

33742 Simplified Application Diagram

Document order number: MC33742

Rev 2.0, 10/2004

33742

33742S

Advance Information

5.0 V

MCU

GND

SUP

33742

GND

RST

V2CTRL

WDOG

PWR

Safe Circuitry

SCLK

MOSI
MISO

SPI

SCLK
MOSI
MISO

INT

TXD

RXD

CANH

CANL

Twisted

Pair

L1
L2
L3

ECU Local

Supply

CAN Bus

33742

System Basis Chip (SBC) with

Enhanced High-Speed CAN

Transceiver

The 33742 and the 33742S are monolithic integrated circuits combining

many functions frequently used by automotive environmental control units
(ECUs).

The 33742 is an SBC having a fully protected fixed 5.0 V low-drop regulator

with current limit, overtemperature pre-warning, and reset. An output drive with
sense input is also provided to implement a second 5.0 V regulator, using an
external PNP bipolar junction transistor. The 33742 has normal, standby, stop,
and sleep modes, an internally switched high-side power supply output with
four wake-up inputs, programmable window watchdog, interrupt, reset, SPI
input control, and a high-speed CAN transceiver compatible with CAN 2.0 A
and B protocols for module-to-module communication.

Features

· High-Speed 1.0 Mbps CAN Interface with Bus Diagnostic Capability

(Detection of CANH and CANL Short to Ground, to V

, and to V

SUP

)

· Low-Drop Voltage 5.0 V, 200 mA V

Regulator with Current-Limiting,

Overtemperature Pre-Warning, and Output Monitoring with Reset

· Additional 5.0 V Regulator with External Series Pass Transistor
· Normal, Standby, Stop, and Sleep Modes with Low Sleep and Stop

Mode Current

· 150 mA High-Side Switch Output for Control of External Circuitry
· Four External Wake-Up Inputs
· Software-Programmable Watchdog Window, Interrupt, and Reset

SYSTEM BASIS CHIP

WITH ENHANCED

HIGH-SPEED CAN

ORDERING INFORMATION

Device

Temperature

Range (T

)

Package

MC33742DW/R2

-40°C to 125°C

28 SOICW

MC33742SDW/R2

DW SUFFIX

CASE 751F-05

28-TERMINAL SOICW

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

33742

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

Figure 1. 33742 Simplified Internal Block Diagram

Table 1. Significance Device Differences

Motorola Part No.

Reset Duration

Device Differences

See Page

33742

15 ms (typical)

The duration of the reset mode, in which the RST terminal is asserted low, is 15 ms
typical. Reset mode is entered after device power up, when a V

undervoltage

condition occurred and if the watchdog register is not properly triggered.

33742S

3.5 ms (typical)

The duration of the reset mode, in which the RST terminal is asserted low, is 3.5 ms
typical. Reset mode is entered after device power up, when a V

undervoltage

condition occurred and if the watchdog register is not properly triggered.

Programmable

HS Control

Mode Control

Reset

Watchdog

Wake-Up Input

SCLK

MOSI

INT

5.0 V/200 mA

V2CTRL

Oscillator

WDOG

SUP

Interrupt

MISO

RXD

TXD

High-Speed 1.0 Mbps

Physical Interface

CANL

CANH

CAN

GND

CAN

Supply

SPI

RST

Dual Voltage Regulator

SUP

Monitor

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33742

TERMINAL DEFINITIONS
A functional description of each terminal can be found in the System/Application Information section beginning on

page 18

Terminal

Name

Formal Name

Definition

RXD

Receive Data

CAN bus receive data output

TXD

Transmit Data

CAN bus transmit data input

Voltage Digital Drain

5.0 V regulator output terminal.

RST

Reset Output
(Active LOW)

This is the device reset output whose main function is to reset the MCU. This terminal
has an internal pull-up current source to V

INT

Interrupt Output

(Active LOW)

This output is asserted LOW when an enabled interrupt condition occurs. The output
is a push-pull structure.

2023

GND

Ground

Ground of the IC. These terminals are connected to the package lead frame in order to
provide a thermal path.

Voltage Source 2

Sense input for V2 regulator using external ballast. V2 is also the internal supply for the
CAN cell.

V2CTRL

Voltage Source 2 Control

Output driver for the external ballast transistor.

SUP

Voltage Supply

Supply input for the complete device.

High-Side Output

Output of internal high-side switch. Current capability is internally limited to 150 mA.

1417

L0L3

Level 0 3 Inputs

Input interfaces to external circuitry (switched or ICs). Levels at these terminals can be
read by SPI and input can be used as programmable wake-up input in Sleep or Stop
mode.

CANH

CAN High

CAN high output.

CANL

CAN Low

CAN low output.

SCLK

Serial Data Clock

Clock input for the Serial Peripheral Interface (SPI) of the device.

MISO

Master In/Slave Out

SPI data sent to MCU. When CS is HIGH, terminal is high impedance.

MOSI

Master Out/Slave In

SPI data received by the 33742.

Chip Select

(Active LOW)

Chip select terminal for SPI. When CS is LOW, device is selected.

WDOG

Watchdog Output

(Active LOW)

Output of watchdog circuitry. Terminal is asserted LOW if software watchdog is not
correctly triggered.

WDOG

MISO
SCLK
GND
GND
GND
GND
CANL
CANH
L3
L2
L1

CS
MOSI

RXD

RST

INT

GND
GND
GND
GND

V2CTRL

SUP

TXD

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

33742

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.

Rating

Symbol

Value

Unit

ELECTRICAL RATINGS

Power Supply Voltage at V

SUP

Terminal

Continuous (Steady-State)
Transient Voltage (Load Dump)

SUP

-0.3 to 27
-0.3 to 40

Logic Inputs (RXD, TXD, MOSI, MISO, CS, SCLK, RST, WDOG, and INT
Terminals)

LOG

-0.3 to V

+ 0.3

Output Current at V

Terminal

Internally Limited

HS Terminal

Voltage
Output Current

-0.3 to V

SUP

+ 0.3

Internally Limited

V
A

ESD Voltage, Human Body Model

(Note 1)

HS, L0, L1, L2, L3, CANH, CANL Terminals
All Other Terminals

ESD1

±4000
±2000

ESD Voltage, Machine Model

(Note 2)

ESD2

±200

L0, L1, L2, L3 Terminals

DC Input Voltage
DC Input Current
Transient Input Voltage with External Component

(Note 3)

DCIN

TRINEC

-0.3 to 40

±2.0

±100

Power Dissipation

(Note 4)

1.0

CANL and CANH Terminals

Continuous Voltage
Continuous Current

CANH/L

-27 to 40

200

CANH and CANL Transient Voltage (Load Dump)

(Note 5)

LDH/L

CANH and CANL Transient Voltage

(Note 6)

TRH/L

±40

Notes

ESD1 testing is performed in accordance with the Human Body Model (C

ZAP

=100 pF, R

ZAP

=1500

ESD2 testing is performed in accordance with the Machine Model (C

ZAP

=200 pF, R

ZAP

Testing in accordance with ISO 7637-1. See also

Figure 2

Maximum power dissipation at 85°C ambient temperature in free air with no heatsink, according to JEDEC JESD51-2 and JESD51-3
specifications.

Load dump test in accordance with ISO 7637-1.

Transient test in accordance with ISO 7637-1. See also

Figure 3

Figure 2. ISO 7637 Test Setup

for L0:L3 Inputs

Figure 3. ISO 7637 Test Setup for CANH/CANL

Transient Pulse

GND

Generator

1.0 nF

(Note)

10 k

Note Waveform per ISO 7637-1. Test Pulses 1, 2, 3a, and 3b.

GND

33742

CANH

CANL

Transient Pulse

GND

Generator

1.0 nF

(Note)

Note Waveform per ISO 7637-1. Test Pulses 1, 2, 3a, and 3b.

33742

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

33742

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.75 V

V2 5.25 V, 5.5 V V

SUP

18 V, and -40°C T

125°C. Typical values noted

reflect the approximate parameter mean at T

= 25

°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

SUP

TERMINAL

Nominal DC Supply Voltage

SUP

5.5

Extended DC Voltage

Full Functionality

(Note 8)

Reduced Functionality

(Note 9)

SUP-EX

4.5

5.5

Input Voltage During Load Dump

SUP-LD

Input Voltage During Jump Start

SUP-JS

Supply Current in Standby Mode

(Note 10)

OUT

at V

= 10 mA,

CAN Recessive or Sleep Mode)

°C

= -

°C to 25°C

SUP(STDBY)

14.5

15
19

Supply Current in Normal Mode

(Note 10)

OUT

at V

= 10 mA,

CAN Recessive or Sleep Mode)

°C

= -

°C to 25°C

SUP(NORM)

12.4

15
19

Supply Current in Sleep Mode

(Note 10)

and V2 OFF, CAN in Sleep

Mode with CAN Wake-Up Disabled

(Note 11)

]

SUP

< 13.5 V, Oscillator Running

(Note 12)

SUP

< 13.5 V, Oscillator Not Running

(Note 13)

SUP

= 18 V, Oscillator Running

(Note 12)

SUP(SLP-WD)

110

105

140

µA

Supply Current in Sleep Mode

(Note 10)

and V2 OFF, V

SUP

< 13.5 V,

Oscillator Not Running

(Note 13)

, CAN in Sleep Mode with Wake-Up Enabled]

= -40

°C

= 25

°C

= 125

°C

SUP(SLP-WE)

80
65
55

µA

Supply Current in Stop Mode

(Note 10)

OUT

at V

< 2.0 mA, V

ON, CAN

in Sleep Mode with Wake-Up Disabled

(Note 11)

SUP

< 13.5 V, Oscillator Running

(Note 12)

SUP

< 13.5 V, Oscillator Not Running

(Note 13)

SUP

= 18 V, Oscillator Running

(Note 12)

SUP(STOP-WD)

100

160

210

µA

Notes

All functions and modes available and operating. Watchdog, HS turn ON/turn OFF, CAN cell operating, L0:L3 inputs operating, SPI read/

write operation. Overtemperature may occur.

> 4.0 V, RST HIGH if reset 2 selected by SPI, logic terminal high level reduced, device is functional.

10.

Current measured at V

SUP

terminal.

11.

If CAN cell is Sleep-Enabled for wake-up, an additional current (I

CAN-

SLEEP

) must be added to specified value.

12.

Oscillator running means one of the following function is active: Forced Wake-Up or Cyclic Sense or Software Watchdog in Stop mode.

13.

Oscillator not running means none of the following functions are active: Forced Wake-Up and Cyclic Sense and Software Watchdog in Stop
mode.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33742

STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.75 V

V2 5.25 V, 5.5 V V

SUP

18 V, and -40°C T

125°C. Typical values noted

reflect the approximate parameter mean at T

= 25

°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

SUP

TERMINAL (continued)

Supply Current in Stop Mode

(Note 14)

OUT

at V

< 2.0 mA, V

ON,

SUP

< 13.5 V, Oscillator Not Running

(Note 15)

, CAN in Sleep Mode with

Wake-Up Enabled]

= -40

°C

= 25

°C

= 125

°C

SUP(STOP-WE)

100

92
80

µA

BATFAIL Flag Internal Threshold

1.5

3.0

4.0

BATFAIL Flag Hysteresis

(Note 16)

BF(HYS)

1.0

Battery Fall Early Warning Threshold

In Normal and Standby Modes

BF(EW)

5.3

5.8

6.3

Battery Fall Early Warning Hysteresis

In Normal and Standby Modes

(Note 16)

BF(EW-HYST)

0.1

0.2

0.3

TERMINAL

(Note 17)

Output Voltage (2.0 mA < I

< 200 mA)

5.5 V < V

SUP

< 27 V

4.5 V < V

SUP

< 5.5 V

DDOUT

4.9
4.0

5.0

5.1

Dropout Voltage

= 200 mA

DDDRP1

0.2

0.5

Dropout Voltage, Limited Output Current and Low V

SUP

= 50 mA, 4.5 V < V

SUP

DDDRP2

0.1

0.25

Output Current

Internally Limited

200

285

350

Thermal Shutdown (Junction)

Normal or Standby Mode

160

200

°C

Overtemperature Pre-Warning (Junction)

VDDTEMP Bit Set

125

160

°C

Temperature Threshold Difference

°C

RST

Threshold, Selectable by RSTTH Bit in SPI Register RCR

Threshold 1, Default Value after Reset, RSTTH Bit set to 0
Threshold 2, RSTTH bit Set to 1

RST

4.5
4.0

4.6
4.2

4.7
4.3

for Reset Active

DDR

1.0

RST

Notes

14.

Current measured at V

SUP

terminal.

15.

Oscillator not running means none of the following functions are active: Forced Wake-Up and Cyclic Sense and Software Watchdog in Stop
mode.

16.

Guaranteed by design; however, it is not production tested.

17.

is the total regulator output current. V

specification with external capacitor. Stability requirement: Capacitance > 47

µF, ESR < 1.3

(tantalum capacitor). In Reset, Normal Request, Normal and Standby modes. Measures with capacitance = 47

µF tantalum.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

33742

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.75 V

V2 5.25 V, 5.5 V V

SUP

18 V, and -40°C T

125°C. Typical values noted

reflect the approximate parameter mean at T

= 25

°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

TERMINAL (continued)

(Note 18)

Line Regulation (I

= 10 mA, Capacitance = 47

µF Tantalum at V

)

9.0 V < V

SUP

< 18 V

5.5 V < V

SUP

< 27 V

5.0

Load Regulation (Capacitance = 47

µF Tantalum at V

)

1.0 mA < I

< 200 mA

Thermal Stability

SUP

= 13.5 V, I

= 100 mA

(Note 19)

THERM-S

TERMINAL IN STOP MODE

(Note 18)

Output Voltage

2.0 mA

10 mA

DDSTOP

4.75
4.75

5.0
5.0

5.25
5.25

Output Current to Wake-Up

DDS-WU

Reset Threshold

Selectable by SPI, Default Value after Reset, Bit Value 0
Selectable by SPI, Bit Value 1

RST

-STOP

4.5
4.1

4.6
4.2

4.7
4.3

Line Regulation (Capacitance = 47

µF Tantalum at V

)

5.5 V < V

SUP

< 27 V, I

= 2.0 mA

LR-STOP

5.0

Load Regulation (Capacitance = 47

µF Tantalum at V

)

1.0 mA < I

< 10 mA

LD-STOP

V2 TRACKING VOLTAGE REGULATOR

(Note 20)

V2 Output Voltage (Capacitance = 10

µF Tantalum at V2)

2.0 mA

200 mA, 5.5 V < V

SUP

< 27 V

0.99

1.0

1.01

Output Current (for Information Only)

Depending on External Ballast Transistor

200

V2 Control Drive Current Capability

(Note 21)

Worst Case at T

= 125°C

2CTRL

V2LOW Flag Threshold

2LTH

3.75

4.0

4.25

Notes

18.

is the total regulator output current. V

specification with external capacitor. Stability requirement: capacitance > 47

µF, ESR < 1.3

(tantalum capacitor). In Reset, Normal Request, Normal and Standby modes, measures with capacitance = 47

µF tantalum.

19.

Guaranteed by characterization and design; however, it is not production tested.

20.

V2 specification with external capacitor. Stability requirement: capacitance > 42

µF and ESR < 1.3 (tantalum capacitor), external resistor

between base and emitter required. Measurement conditions: ballast transistor MJD32C, capacitance > 10

µF tantalum, 2.2 k resistor

between base and emitter of ballast transistor.

21.

Guaranteed current capability of the V2CTRL terminal is 10 mA. Current may be higher. No active limitation is provided.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33742

STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.75 V

V2 5.25 V, 5.5 V V

SUP

18 V, and -40°C T

125°C. Typical values noted

reflect the approximate parameter mean at T

= 25

°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

LOGIC OUTPUT TERMINAL (MISO)

(Note 22)

Low-Level Output Voltage

OUT

= 1.5 mA

1.0

High-Level Output Voltage

OUT

= -250

µA

- 0.9

Tri-Stated MISO Leakage Current

0 V < V

MISO

-2.0

2.0

µA

LOGIC

INPUT TERMINALS (MOSI, SCLK,

)

High-Level Input Voltage

0.7 V

+ 0.3

Low-Level Input Voltage

-0.3

0.3 V

High-Level Input Current on CS

= 4.0 V

-100

-20

µA

Low-Level Input Current on CS

= 1.0 V

-100

-20

µA

MOSI and SCLK Input Current

0 V < V

< V

-10

µA

RST

OUTPUT TERMINAL

(Note 23)

High-Level Output Current

0 V < V

OUT

< 0.7 V

-300

-250

-150

µA

Low-Level Output Voltage

= 1.5 mA, 5.5 V < V

SUP

< 27 V

= 0 mA, 1.0 V <V

SUP

< 5.5 V

0
0

0.9
0.9

RST

Pulldown Current

V > 0.9 V

PDW

2.3

5.0

WDOG

OUTPUT TERMINAL

(Note 24)

Low-Level Output Voltage

= 1.5 mA, 1.0 V < V

SUP

< 27 V

0.9

High-Level Output Voltage

= -250

µA

-0.9

INT

OUTPUT TERMINAL

(Note 24)

Low-Level Output Voltage

= 1.5 mA

0.9

High-Level Output Voltage

= -250

µA

-0.9

Notes

22.

Push-pull structure with tri-state condition (CS HIGH).

23.

Output terminal only. Supply from V

. Structure switch to ground with pullup current source.

24.

Push-pull structure.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

33742

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.75 V

V2 5.25 V, 5.5 V V

SUP

18 V, and -40°C T

125°C. Typical values noted

reflect the approximate parameter mean at T

= 25

°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

HS OUTPUT TERMINAL

Driver Output ON Resistance

= 25°C, I

OUT

150 mA, V

SUP

> 9.0 V

= 125°C, I

OUT

150 mA, V

SUP

> 9.0 V

= 125°C, I

OUT

120 mA, 5.5 V < V

SUP

< 9.0 V

DS(ON)

2.0

3.5

2.5

4.5

5.5

Output Current Limitation

SUP

> 1.0 V

LIM

160

500

HS Thermal Shutdown

155

190

°C

HS Leakage Current

LEAK

µA

Output Clamp Voltage

OUT

= -10 mA, No Inductive Load Drive Capability

-1.5

-0.3

L0, L2, L2, AND L3 INPUT TERMINALS

Negative Switching Threshold

5.5 V < V

SUP

< 6.0 V

6.0 V < V

SUP

< 18 V

18 V < V

SUP

< 27 V

THN

2.0

2.5

2.7

2.5

3.0

3.2

3.0

3.6

3.7

Positive Switching Threshold

5.5 V < V

SUP

< 6.0 V

6.0 V < V

SUP

< 18 V

18 V < V

SUP

< 27 V

THP

2.7

3.0

3.5

3.3

4.0

4.2

3.8

4.6

4.7

Hysteresis

5.5 V < V

SUP

< 27 V

HYST

0.6

1.3

Input Current

-0.2 V < V

< 40 V

-10

µA

CAN SUPPLY

Supply Current of CAN Cell

CAN in Normal Mode, Bus Recessive State

CAN in Normal Mode, Bus Dominant State without Bus Load

CAN in Sleep State, Wake-Up Enabled, V2 Regulator OFF

CAN in Sleep State, Wake-Up Disabled, V2 Regulator OFF

(Note 25)

RES

DOM

CAN-SLEEP

DIS

1.3

1.5

3.0

3.5

1.0

µA
µA

Notes

25.

Guaranteed by design; however, it is not production tested.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33742

STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.75 V

V2 5.25 V, 5.5 V V

SUP

18 V, and -40°C T

125°C. Typical values noted

reflect the approximate parameter mean at T

= 25

°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

CANH AND CANL TERMINALS

Bus Terminals Common Mode Voltage

-27

Differential Input Voltage (Common Mode Between -3.0 V and 7.0 V)

Recessive State at RXD
Dominant State at RXD

CANH

CANL

900

500

Differential Input Hysteresis (RXD)

HYST

100

Input Resistance

5.0

100

Differential Input Resistance

IND

100

CANH Output Voltage

TXD Dominant State
TXD Recessive State

CANH

2.75

4.5
3.0

CANL Output Voltage

TXD Dominant State
TXD Recessive State

CANL

0.5
2.0

2.25

Differential Output Voltage

TXD Dominant State
TXD Recessive State

-Vo

1.5

3.0

100

Output Current Capability (Dominant State)

CANH
CANL

CANH

CANL

-35

Overtemperature Shutdown

160

180

°C

CANL Overcurrent Detection

(Note 26)

CANL
CANH

CANL/OC

CANH/OC

-200

200

-60

CANH and CANL Input Current, Device Supplied (CAN Sleep Mode with
CAN Wake-Up Enabled or Disabled)

CANH

, V

CANL

from 0 V to 5.0 V

CANH

, V

CANL

= -2.0 V

CANH

, V

CANL

= 7.0 V

CAN1

-60

3.0

-50

µA

CANH and CANL Input Current, Device Unsupplied

CANH

, V

CANL

= 2.5 V

CANH

, V

CANL

= -2.0 V

CANH

, V

CANL

= 7.0 V

CAN2

-60

-50

190

100

240

µA

Notes

26.

Reported in CAN register. For a description of the contents of the CAN register, refer to

CAN Register (CAN) on page 40

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

33742

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.75 V

V2 5.25 V, 5.5 V V

SUP

18 V, and -40°C T

125°C. Typical values noted

reflect the approximate parameter mean at T

= 25

°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

CANH AND CANL DIAGNOSTIC INFORMATION

CANL to GND Threshold

1.75

CANH to GND Threshold

1.75

CANL to V

SUP

Threshold

LVB

SUP

- 2.0

CANH to V

SUP

Threshold

HVB

SUP

- 2.0

CANL to V

Threshold

- 0.43

CANH to V

Threshold

- 0.43

RXD Weak Pulldown Current Source

(Note 27)

RXD Permanent Dominant Failure Condition

RXDW

100

µA

TXD AND RXD TERMINALS

TXD Input High Voltage

0.7 V

+ 0.4

TXD Input Low Voltage

-0.4

0.3 V

TXD High-Level Input Current

TXD

= V

-10

µA

TXD Low-Level Input Current

TXD

= 0 V

-150

-100

-50

µA

RXD Output High Voltage

RXD

= 250

µA

1.0

RXD Output Low Voltage

RXD

= 1.0 mA

0.5

Notes

27.

Guaranteed by design; however, it is not production tested.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33742

DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.75 V

V2 5.25 V, 5.5 V V

SUP

18 V, and -40°C T

125°C. Typical values noted

reflect the approximate parameter mean at T

= 25

°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

DIGITAL INTERFACE TIMING

(Note 28)

SPI Operation Frequency

REQ

0.25

4.0

MHz

SCLK Clock Period

PCLK

250

N/A

SCLK Clock High Time

WSCLKH

125

N/A

SCLK Clock Low Time

WSCLKL

125

N/A

Falling Edge of CS to Rising Edge of SCLK

LEAD

100

N/A

Falling Edge of SCLK to Rising Edge of CS

LAG

100

N/A

MOSI to Falling Edge of SCLK

SISU

N/A

Falling Edge of SCLK to MOSI

SIH

N/A

MISO Rise Time

(Note 29)

= 220 pF

RSO

MISO Fall Time

(Note 29)

= 220 pF

FSO

Time from Falling or Rising Edges of CS

MISO Low Impedance
MISO High Impedance

SOEN

SODIS

Time from Rising Edge of SCLK to MISO Data Valid

0.2 V

MISO 0.8 V

, C

= 200 pF

VALID

STATE MACHINE TIMING

Delay Between CS LOW-to-HIGH Transition (at End of SPI Stop Command)
and Stop Mode Activation

(Note 30)

-STOP

µs

Interrupt Low-Level Duration

Stop Mode

INT

7.0

µs

Internal Oscillator Frequency

(Note 31)

OSC

100

kHz

Watchdog Period Normal and Standby Modes

Period 1
Period 2
Period 3
Period 4

8.58
39.6

308

9.75

100
350

10.92

50.4

112
392

Notes

28.

See

Figure 4, SPI Timing Diagram

, page 17.

29.

Not production tested. Guaranteed by design.

30.

Not production tested. Guaranteed by design. Detected by V2 OFF.

31.

OSC

is indirectly measured (1.0 ms reset) and trimmed.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

33742

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.75 V

V2 5.25 V, 5.5 V V

SUP

18 V, and -40°C T

125°C. Typical values noted

reflect the approximate parameter mean at T

= 25

°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

STATE MACHINE TIMING (continued)

Normal Request Mode Timeout

Normal Request Mode

NRTOUT

308

350

392

Watchdog Period Stop Mode

Period 1
Period 2
Period 3
Period 4

WD-STOP

6.82
31.5

245

9.75

100
350

12.7
58.5

130
455

Watchdog Period Accuracy

Normal and Standby Modes
Stop Mode

ACC

-12

-30

12
30

Cyclic Sense/FWU Timing Sleep and Stop Modes

Timing 1
Timing 2
Timing 3
Timing 4
Timing 5
Timing 6
Timing 7
Timing 8

CSFWU

3.22
6.47
12.9
25.9
51.8
66.8

134
271

4.6

9.25
18.5

37
74

95.5

191
388

5.98

12
24

48.1
96.2

124
248
504

Cyclic Sense ON Time

Sleep and Stop Modes.

200

350

500

µs

Cyclic Sense/FWU Timing Accuracy

Sleep and Stop Modes

ACC

-30

Delay Between SPI Command and HS Turn ON

(Note 32)

Normal or Standby Mode, V

SUP

> 9.0 V

S-HSON

µs

Delay Between SPI Command and HS Turn OFF

(Note 32)

Normal or Standby Mode, V

SUP

> 9.0 V

S-HSOFF

µs

Delay Between SPI and V2 Turn ON

(Note 32)

Standby Mode

S-V2ON

9.0

µs

Delay Between SPI and V2 Turn OFF

(Note 32)

Normal Mode

S-V2OFF

9.0

µs

Delay Between Normal Request and Normal Mode After Watchdog Trigger
Command

(Note 32)

Normal Request Mode

S-NR2N

µs

Delay Between SPI and CAN Normal Mode

(Note 32)

Normal Mode

(Note 33)

S-CAN_N

µs

Delay Between SPI and CAN Sleep Mode

(Note 32)

Normal Mode

(Note 33)

S-CAN_S

µs

Notes

32.

Delay starts at falling edge of clock cycle #8 of the SPI command and start of "Turn ON" or "Turn OFF" of HS or V2.

33.

Guaranteed by design; however, it is not production tested.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33742

DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.75 V

V2 5.25 V, 5.5 V V

SUP

18 V, and -40°C T

125°C. Typical values noted

reflect the approximate parameter mean at T

= 25

°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

STATE MACHINE TIMING (continued)

Delay Between CS Wake-Up (CS LOW to HIGH) and Device in Normal
Request Mode (V

ON and RST HIGH)

Stop Mode

W-

µs

Delay Between CS Wake-Up (CS LOW to HIGH) and First Accepted SPI
Command

Device in Stop Mode After Wake-Up

W-SPI

N/A

µs

Delay Between INT Pulse and First SPI Command Accepted

Device in Stop Mode After Wake-Up

S-1STSPI

N/A

µs

Delay Between Two SPI Messages Addressing the Same Register

2SPI

µs

TERMINAL

Reset Delay Time

Measured at 50% of Reset Signal

4.0

µs

Overcurrent to Wake-Up Deglitcher Time

(Note 34)

IDD-DGLT

µs

RST

TERMINAL

Reset Duration After V

HIGH

33742
33742S

RST

DUR

RST

DURS

3.0

3.5

4.0

L0, L2, L2, AND L3 INPUT TERMINALS

Wake-Up Filter Time

WUF

8.0

µs

Notes

34.

Guaranteed by design; however, it is not production tested.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

33742

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.75 V

V2 5.25 V, 5.5 V V

SUP

18 V, and -40°C T

125°C. Typical values noted

reflect the approximate parameter mean at T

= 25

°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

CAN MODULE TIMING

Dominant State Timeout

DOUT

200

360

520

µs

Propagation Loop Delay TXD to RXD (Recessive to Dominant)

(Note 35)

Slew Rate 3
Slew Rate 2
Slew Rate 1
Slew Rate 0

LRD

60
70
80

110

100
110
130
200

210
225
255
310

Propagation Delay TXD to CAN (Recessive to Dominant)

(Note 36)

Slew Rate 3
Slew Rate 2
Slew Rate 1
Slew Rate 0

TRD

20
25
35
50

65
80

100
160

110
150
200
300

Propagation Delay CAN to RXD (Recessive to Dominant)

(Note 37)

RRD

140

Propagation Loop Delay TXD to RXD (Dominant to Recessive)

(Note 35)

Slew Rate 3
Slew Rate 2
Slew Rate 1
Slew Rate 0

LDR

100
120
140
250

150
165
200
340

200
220
250
410

Propagation Delay TXD to CAN (Dominant to Recessive)

(Note 36)

Slew Rate 3
Slew Rate 2
Slew Rate 1
Slew Rate 0

TDR

60
65
75

200

125
150
180
310

150
190
250
460

Propagation Delay CAN to RXD (Dominant to Recessive)

(Note 37)

RDR

Non-Differential Slew Rate (CANL or CANH)

Slew Rate 3

Slew Rate 2

Slew Rate 1

Slew Rate 0

SL3

SL2

SL1

SL0

4.0

3.0

2.0

1.0

13.5

8.0

5.0

µs

Notes

35.

See

Figure 5

, page 17.

36.

See

Figure 6

, page 17.

37.

See

Figure 7

, page 17.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

33742

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

SYSTEM/APPLICATION INFORMATION

INTRODUCTION

The 33742 and the 33742S are integrated circuits dedicated

to automotive applications. Their functions include the
following:

· One fully protected voltage regulator with 200 mA total

output current capability available at the V

terminal.

· Driver for external pass transistor for V2 regulator

function.

· V

regulator undervoltage reset function, programmable

window or timeout software watchdog function.

· Two running modes: Normal and Standby modes when

the microcontroller is running.

· Sleep and Stop modes for operation in low power mode to

reduce the application current consumption, while offering
wake-up capability from CAN interface, L3:L0 wake-up
input, and automatic timer wake-up.

· Programmable wake-up input and cyclic sense wake-up.
· CAN high-speed physical interface with bus failure

diagnostic and enhanced protection feature for TXD and
RXD failure.

· Interface with micro through SPI. Interrupt output to report

device status, diagnostic, and wake-up event.

FUNCTIONAL TERMINAL DESCRIPTION

RXD and TXD

The RXD and TXD terminals (receive data terminal and

transmit data terminal, respectively) are connected to the
microcontroller CAN protocol handler. TXD is an input and
controls the CANH and CANL line state (dominant when TXD is
LOW, recessive when TXD is HIGH). RXD is an output and
reports the bus state (RXD LOW when CAN bus is dominant,
HIGH when CAN bus is recessive).

The V

terminal is the output terminal of the 5.0 V internal

regulator. It can deliver up to 200 mA. This output is protected
against overcurrent and overtemperature. It includes an
overtemperature pre-warning flag, which is set when the
internal regulator temperature exceeds 130°C typical. When
the temperature exceeds the overtemperature shutdown
(170°C typical), the regulator is turned off.

includes an undervoltage reset circuitry, which sets the

RST

terminal LOW when V

is below the undervoltage reset

threshold.

RST

The Reset terminal

RST

is an output that is set LOW when

the device is in reset mode. The

RST

terminal is set HIGH when

the device is not in reset mode.

RST

includes an internal pullup

current source. When

RST

is LOW, the sink current capability is

limited, allowing

RST

to be shorted to 5.0 V for software debug

or software download purposes.

INT

The Interrupt terminal

INT

is an output that is set LOW when

an interrupt occurs.

INT

is enabled using the Interrupt Register

(INTR). When

INT

occurs,

INT

stays LOW until the

INT

source

is cleared.

INT

output also reports a wake-up event by a 10

µs typical

pulse when the device is in stop mode.

The V2 terminal is the input sense of the V2 regulator. It is

connected to the external ballast transistor. V2 is also the 5.0 V
supply of the internal CAN interface. It is possible to connect V2
to an external 5.0 V regulator or to the V

output when no

external ballast transistor is used. In this case, the V2CTRL
terminal must be left open. Refer to

Figure 28, 33742 Typical

Application Schematic

, page 46.

V2CTRL

The V2CTRL terminal is the output drive of the V2 regulator

connected to the external ballast transistor.

SUP

The V

SUP

terminal is the battery supply input of the device.

The HS terminal is the internal high-side driver output. It is

internally protected against overcurrent and overtemperature.

L0, L1, L2, and L3

The L0:L3 input terminals can be connected to external

switches or any IC's output. The state of the inputs can be read
by SPI. Theses inputs can be used as wake-up events when the
device is set in Sleep or Stop mode.

CANH and CANL

The CAN High and CAN Low terminals are the interfaces to

the CAN bus lines. They are controlled by TXD input level, and
the state of CANH and CANL is reported through RXD output.
A 60

impedance termination is connected between CANH

and CANL.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33742

SCLK

This is the Serial Data Clock terminal of the serial peripheral

interface.

MISO

his is the Master In/Slave Out terminal of the serial

peripheral interface. Data are send from the device to the
microcontroller through MISO terminal.

MOSI

This is the Master Out/Slave In terminal of the serial

peripheral interface. Control data from the microcontroller are
received through this terminal.

This is the device Chip Select terminal of the serial peripheral

interface. When this terminal is LOW, the internal serial
peripheral interface of the device is selected.

WDOG

The Watchdog terminal is used to signal that a software

watchdog has not been properly triggered.

DEVICE OPERATION

Power Supply

The 33742 is supplied from the battery line through the V

SUP

terminal. An external diode is required to protect against
negative transients and reverse battery. The 33742 can operate
from 4.5 VDC and under jump-start conditions at 27 VDC.

The V

SUP

terminal sustains standard automotive voltage

conditions such as load dump at 40 V. When V

SUP

falls below

3.0 V typical, the 33742 detects it and stores the information in
the Mode Control Register (MCR) bit BATFAIL

Detection is

available in all operation modes.

Note For a detailed description of all the registers

mentioned in this section, refer to the section titled

SPI

INTERFACE AND REGISTER DESCRIPTION

beginning on

page 38.

The 33742 incorporates a battery early warning function,

which provides a maskable interrupt when the V

SUP

voltage is

below 6.0 V typical. A hysteresis is included. Operation is only
in Normal and Standby modes. V

SUP

LOW is reported in the

Input/Output Register (IOR).

Regulator

The V

regulator is a 5.0 V output with output current

capability up to 200 mA. It includes a voltage monitoring
circuitry associated with an undervoltage reset function. The
V

regulator is fully protected against overcurrent and short

circuit. It has overtemperature detection warning flags (bit
VDDTEMP in the MCR and INTR registers) and
overtemperature shutdown with hysteresis.

V2 Regulator

V2 regulator circuitry is designed to drive an external pass

transistor increasing output current flexibility. Two terminals, V2
and V2CTRL, are used to achieve the flexibility. Output voltage
is 5.0 V and is realized by a tracking function of the V

regulator. The recommended ballast transistor is MJD32C.
Other transistors can be used, however. Depending on the PNP
transistor gain, an external resistor-capacitor network might be
connected. V2 is the supply input for the CAN cell. The state of
V2 is reported in the IOR register (bit V2LOW set to logic [1] if
V2 is below 4.0 V typical).

HS V

SUP

Switch Output

HS output is a 2.0

typical switch from V

SUP

terminal. It

allows the supply of external switches and their associated
pullup or pulldown circuitry, in conjunction, for example, with the
wake-up input terminals L0:L3. Output current is limited to
200 mA and HS is protected against short circuit and has an
overtemperature shutdown (bit HSOT in the IOR register and bit
HSOT-V2LOW in the INTR register).

HS output is controlled by the bit HSON in the IOR register.

Thanks to an internal timer, HS can be activated at regular
intervals in Sleep and Stop modes. It can also be permanently
turned on in Normal or Standby modes to drive loads or supply
peripheral components. No internal clamping protection circuit
is implemented; thus dedicated external protection circuitry is
required in case of inductive load drive. HS negative voltage
should not go below -0.3 V.

Battery Fail Early Warning

Refer to the discussion under the heading

Power Supply

above.

Internal Clock

The 33742 has an internal clock used to generate all timings

(reset, watchdog, cyclic wake-up, filtering time, etc.). Two
oscillators are implemented. A high-accuracy (±12 percent)
oscillator used in Normal Request, Normal, and Standby
modes, and a low-accuracy (±30 percent) oscillator used in
Sleep and Stop modes.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

33742

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

Functional Modes

The 33742 has four modes of operation, all controlled by the

SPI. The modes are Standby, Normal, Stop, and Sleep. An
additional temporary mode called Normal Request mode is
automatically accessed by the device after reset or wake-up
from Stop mode. A Reset mode is also implemented. Special
modes and configuration are possible for debug and program

microcontroller flash memory.

Table 2

below offers a summary of the functional modes.

Reset Mode

In the Reset mode, the

RST

terminal is LOW and a timer runs

for t

RSTDUR

time. After t

RSTDUR

has elapsed, the 33742 enters

Normal Request mode. Reset mode is entered if a reset
condition occurs (V

LOW, watchdog timeout, or watchdog

trigger in a closed window).

Normal Request Mode

Normal Request mode is a temporary mode automatically

accessed by the 33742 after the Reset mode or after the 33742
wakes up from Stop mode. After wake-up from the Sleep mode
or after device power-up, the 33742 enters the Reset mode
before entering the Normal Request mode. After a wake-up
from the Stop mode, the 33742 enters the Normal Request
mode directly.

Table 2. Table of Operation

Mode

Voltage Regulator

HS Switch

Wake-Up

Capabilities

(if Enabled)

RST

Terminal

INT

Terminal

Watchdog

Software

CAN Cell

Normal

Request

: ON,

V2: OFF,

HS: OFF

Low for

RST

DUR

time, then HIGH

Normal

: ON,

V2: ON,

HS: Controllable

Normally HIGH.

Active LOW if

WDOG

or V

undervoltage occurs

If enabled, signal

failure (V

Pre-Warning Temp,

CAN, HS)

Running

TXD/RXD

Standby

: ON,

V2: OFF,

HS: Controllable

Same as Normal

mode

Same as Normal

mode

Running

Low power

Stop

: ON

(Limited Current

Capability),

V2: OFF,

HS:OFF or Cyclic

Sense

CAN, SPI, L0:L3,

Cyclic Sense,

Forced Wake-Up,

Overcurrent

(Note 39)

Normally HIGH.

Active LOW if

WDOG

(Note 40)

or V

undervoltage occurs

Signal 33742

wake-up and

> I

DDS-WU

(not maskable)

Running if enabled.

Not running if

disabled

Low power.

Wake-up capability

if enabled

Sleep

: OFF,

V2: OFF,

HS: OFF or Cyclic

CAN, SPI,

L0:L3, Cyclic Sense

Forced Wake-Up

LOW

Not Active

Not running

Low power.

Wake-up capability

if enabled

Normal

Debug

(Note 38)

Same as Normal

Normally HIGH.

Active LOW if V

undervoltage occurs

Same as Normal

Not running

Same as Normal

Standby

Debug

(Note 38)

Same as Standby

Normally HIGH.

Active LOW if V

undervoltage occurs

Same as Standby

Not running

Same as Standby

Stop Debug

(Note 38)

Same as Stop

Normally HIGH.

Active LOW if V

undervoltage occurs

Same as Stop

Not running

Same as Stop

Flash

Programming

Forced externally

Not operating

Not Operating

Notes

38.

Mode entered via special sequence described under the heading

Debug Mode: Hardware and Software Debug with the 33742

beginning on

page 25.

39.

overcurrent always enabled.

40.

WDOG

if enabled.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33742

In Normal Request mode, the V

regulator is ON, the V2

regulator is OFF, and the

RST

terminal is HIGH. As soon as the

33742 enters the Normal Request mode, an internal 350 ms
timer is started (parameter t

NRTOUT

). During these 350 ms, the

MCU of the application must address the 33742 via SPI and
configure the TIM1 subregister to select the watchdog period.
This is the condition for the 33742 to stop the 350 ms timer and
go into the Normal or Standby mode and set the watchdog timer
according to the configuration.

Normal Request Entered and No Watchdog Configuration
Occurs

If the Normal Request mode is entered after the 33742

powers up or after a wake-up from Stop mode, and if no
watchdog configuration occurs while the 33742 is in Normal
Request mode, the 33742 goes into Reset mode after the
350 ms time period has expired before again going into Normal
Request mode. If no watchdog configuration is achieved, the
33742 alternatively goes from Normal Request mode, to Reset
mode, to Normal Request mode, and so on.

If the Normal Request mode is entered after a wake-up from

Sleep mode, and if no watchdog configuration occurs while the
33742 is in Normal Request mode, the 33742 goes back to
Sleep mode.

Normal Mode

In Normal mode, both the V

and V2 regulators are ON.

This corresponds to the normal application operation. All
functions are available in this mode (watchdog, wake-up input
reading through SPI, HS activation, and CAN communication).
Watchdog software is running and must be periodically cleared
through SPI.

Standby Mode

In Standby mode, only the V

regulator is ON. The V2

regulator is turned OFF by disabling the V2CTRL terminal. The
CAN interface is not able to send messages. If a CAN message
is received, the CANWU bit is set. Other functions available are
L0:L3 input reading through SPI and HS activation. Watchdog
is running.

Sleep Mode

In Sleep mode, the V

and V2 regulators are OFF. Current

from the V

SUP

terminal is reduced. In Sleep mode, the 33742

can be awakened by L0:L3 inputs, by cyclic sense of the L0:L3
inputs, by the automatic forced wake-up timer, and from the
CAN physical interface receiving an incoming CAN message.
When a wake-up occurs, the 33742 goes first into the Reset
mode before entering Normal Request mode.

Stop Mode

The V2 regulator is turned OFF by disabling the V2CTRL

terminal. The V

regulator is activated in a special low power

mode, allowing the delivery of a few mA. The objective is to
maintain power on the MCU of the application while the MCU is
turned into power-saving condition (i.e, Stop or Wait modes). In
Stop mode, the device supply current from V

PWR

is very low.

When the application is in Stop mode (both MCU and

33742), the application can wake up from either the 33742 side
(for example, cyclic sense, forced wake-up, CAN message,
wake-up inputs, and overcurrent on V

) or the MCU side (key

wake-up, etc.).

Stop mode is always selected by SPI. In Stop mode, the

watchdog software may be either running or not running
depending upon selection by SPI (Reset Control Register
[RCR], bit WDSTOP). To clear the watchdog if it is running, the
33742 must be awakened by the

terminal (SPI wake-up). In

Stop mode, the 33742 wake-up capability is identical to that in
Sleep mode, with the addition of

and V

overcurrent wake-

up. Refer to

Table 2

, page 20.

Application Wake-Up from 33742 Side

When the application is in Stop mode, it can wake up from

the 33742 side. When a wake-up is detected by the 33742 (for
example, CAN, wake-up input), the 33742 turns itself into
Normal Request mode and generates an interrupt pulse at the

INT

terminal.

Application Wake-Up from MCU Side

When the application is in Stop mode, the wake-up event

may come from the MCU side. In this case the MCU signals to
the 33742 by a LOW-to-HIGH transition on the

terminal.

Then the 33742 goes into Normal Request mode and generates
an interrupt pulse at the

INT

terminal.

Stop Mode Current Monitor

If the V

output current exceeds an internal threshold

DDS-WU

), the 33742 goes automatically into Normal Request

mode and generates an interrupt at the

INT

terminal. The

interrupt is not maskable and the INTR register will have no flag
set.

Interrupt Generation When Wake-Up from Stop Mode

When the 33742 wakes up from Stop mode, it first enters the

Normal Request mode before generating a pulse (10

µs typical)

on the

INT

terminal. These interrupts are not maskable, and the

wake-up event can be read through the SPI registers, CANWU
bit in the CAN Register (CANR), and LCTRx bit in the Wake-Up
Register (WUR). In case of wake-up from Stop mode
overcurrent or from forced wake-up, no bit is set. After the

INT

pulse, the 33742 accepts SPI command after a time delay
(t

S-1STSPI

Watchdog Software in Stop Mode

If watchdog is enabled, the MCU has to wake up

independently of the 33742 before the end of the 33742
watchdog time. In order to do this, the MCU must signal the
wake-up to the 33742 through the SPI wake-up (

activation).

The 33742 then wakes up and jumps into the Normal Request
mode. The MCU has to configure the 33742 to go to either
Normal or Standby mode. The MCU can then decide to go back
to the Stop mode.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

33742

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

If no MCU wake-up occurs within the watchdog timing the

33742 activates the

RST

terminal and jumps into the Normal

Request mode. The MCU can then be initialized.

Stop Mode Enter Command

Stop mode is entered at the end of the SPI message at the

rising edge of the

. (Refer to the t

CS-STOP

data in the

Dynamic Electrical Characteristics table on

page 13

.) Once

Stop mode is entered, the 33742 can wake up from the V

regulator overcurrent detection. In order to allow time for the
MCU to complete the last CPU instruction, allowing the MCU to
enter its low power mode, a deglitcher time of 40

µs typical is

implemented.

Figure 8

, page 22, depicts the operation of entering the Stop

mode.

Figure 8. Entering Stop Mode

RST

and WDOG Terminals, Software Watchdog

Operations

Watchdog Software (Selectable Watchdog

Window or

Watchdog Timeout)

Watchdog software is used in the 33742 Normal and

Standby modes for monitoring the MCU. Watchdog may be
either watchdog window or watchdog timeout, selectable by
SPI (TIM1 subregister, bit WDW). Default is watchdog window.

The watchdog period may be set from 10 ms to 350 ms

(TIM1 subregister, bits WDT0 and WDT1). When watchdog
window is selected, the closed window is the first part of the
selected period, and the open window is the second part of the
period. (Refer to

Timing Register (TIM1/2)

beginning on

page 43.)

Watchdog can only be cleared within the open window time.

Any attempt to clear watchdog in the closed window will
generate a reset. Watchdog is cleared through SPI by
addressing the TIM1 subregister.

RST

Terminal Description

A reset output is available to reset the MCU. Causes of reset

are the following:

· V

Falling Out of Range--If V

falls below the reset

threshold (V

RSTTH

), the

RST

terminal is pulled LOW until

returns to the normal voltage.

· Power-ON Reset--At 33742 power-on or wake-up from

Sleep mode, the

RST

terminal is maintained LOW until

is within its operation range.

· Watchdog Timeout--If watchdog is not cleared, the

33742 will pull the

RST

terminal LOW for the duration of

the reset time

(

RSTDUR

SPI CS

SPI Stop/Sleep

Command

33742 in Normal

or Standby mode

33742 in Stop mode.

No I

over I

DD-DGLT

33742 in Stop mode.

over I

DD-DGLT

-STOP

IDD-DGLT

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33742

Reset and Watchdog Operation

Table 3

describes watchdog and reset output modes of

operation.

RST

is activated in the event V

fall or watchdog is

not triggered.

WDOG

output is active LOW as soon as

RST

goes

LOW and stays LOW as long as the watchdog is not properly
reactivated by SPI. The

WDOG

output terminal is a push-pull

structure that can drive external components of the application;
for instance, to signal MCU wrong operation.

Figure 9

illustrates the device behavior in the event the TIM1

WDOG

terminal is set LOW until the TIM1

Figure 9.

RST

and

WDOG

Output Operation

Wake-Up Capabilities

Several wake-up capabilities are available to the 33742

when it is in Sleep or Stop mode. When a wake-up has
occurred, the wake-up event is stored in the Wake-Up Register
(WUR) or the CAN register. The MCU can then access the
wake-up source. The wake-up options are selectable through
SPI while the 33742 is in Normal or Standby mode and prior to
entering low power mode (Sleep or Stop mode). When a wake-
up occurs from Sleep mode, the 33742 activates V

. It

generates an interrupt if wake-up occurs from Stop mode.

Wake-Up from Wake-Up Inputs (L0:L3) Without Cyclic
Sense

The wake-up lines are dedicated to sense the state of

external switches and if changes occur to wake up the MCU (in
Sleep or Stop modes). Wake-up terminals L0:L3 are able to
handle 40 VDC. The internal threshold is 3.0 V typical and
these inputs can be used as an input port expander. The wake-
up input states are read through SPI (WUR register).

In order to select and activate direct wake-up from the L0:L3

inputs, the WUR register must be configured with the
appropriate level sensitivity. Additionally, the Low Power

Control (LPC) Register must be configured with 0xx0 data (bits
LX2HS and HSAUTO are set to 0).

Level sensitivity is selected by the WUR register. Level

sensitivity is configured by L0:L3 input pairs: L0 and L1 level
sensitivity are configured together, while L2 and L3 are
configured together.

Cyclic Sense Wake-Up (Cyclic Sense Timer and Wake-Up
Inputs L0:L3)

The 33742 can wake up upon state change of one of the four

wake-up input lines (L0:L3) while the external pullup or
pulldown resistor of the switches associated with the wake-up
input lines are biased with HS V

SUP

switch. The HS switch is

activated in Sleep or Stop modes from an internal timer. Cyclic
Sense and Forced Wake-Up are exclusive. If Cyclic Sense is
enabled, Forced Wake-Up cannot be enabled.

In order to select and activate the cyclic sense wake-up from

the L0:L3 inputs, the WUR register must be configured with the
appropriate level sensitivity, and the LPC register must be
configured with 1xx1 data (bit LX2HS set at 1 and bit HSAUTO
set at 1). The wake-up mode selection (direct or cyclic sense) is
valid for all four wake-up inputs.

Table 3. Watchdog and Reset Output Operation

Events

WDOG

Output

RST

Output

Device Power-Up

LOW to HIGH

Normal,

Watchdog Properly Triggered

HIGH

< RST

HIGH

LOW

Watchdog Timeout Reached

LOW

(Note 41)

LOW

Notes

41.

WDOG

stays LOW until the TIM1 register

is properly

addressed through SPI.

RST

WDOG

SPI

Watchdog Timeout

TIM1 register addressed.

Watchdog

Period

Watchdog Clear

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

33742

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

Forced Wake-Up

The 33742 can wake up automatically after a predetermined

time spent in Sleep or Stop mode. Cyclic Sense and Forced
Wake-up are exclusive. If Forced Wake-Up is enabled (FWU bit
set to 1 in the LPC register), Cyclic Sense cannot be enabled.

CAN Interface Wake-Up

The 33742 incorporates a high-speed 1.0 Mbps CAN

physical interface. It is compatible with ISO 11898-2. The
control of the CAN physical interface operation is accomplished
through the SPI. CAN modes are independent of the 33742
operation modes.

The 33742 can wake up from a CAN message if the CAN

wake-up is enabled. Refer to the section titled

CAN BUS

MODULE DESCRIPTION

beginning on page 29 for details of

the wake-up detection.

SPI Wake-Up

The 33742 can be awakened by the

terminal in Sleep or

Stop modes. Wake-up is detected by the

terminal transition

from LOW to HIGH level. In Stop mode, this corresponds with
the condition where the MCU and the 33742 are in Stop mode
and when the application wake-up event comes through the
MCU.

33742 Power-Up and 33742 Wake-Up from Sleep Mode

After device or system power-up, or after the 33742 wakes

up from Sleep mode, the 33742 enters into the Reset mode
prior to moving into Normal Request mode.

Figure 10

shows the device state diagram and

Figure 11

page 25, shows device behavior after power-up sequence.

Figure 10. 33742 State Diagram (Not Valid in Debug Modes)

tch

dog:

Tri

gger

High Temperature OR [V

Low > 100 ms & V

SUP

> BFew]) & Nostop & !BATFAIL

Watchdog: Timeout & Nostop & !BATFAIL

Power
Down

Reset

Normal Request

Stop

Sleep

Reset Counter (3.4 ms)

Expired

3742

wer-Up

Low OR Watchdog:

Timeout 350 ms & Nostop

ke-

SPI: Standby and

Watchdog Trigger

(Note 42)

t
an

dby

Norma

SPI: Stop & CS

LOW to HIGH

Transition

SPI:

Stop

Low

ransi

tio

Watchdog: Timeout OR V

Low

Nosto

d SP

p
&

LOW

HIG

and S

I
:
S

l
eep

& C

W to

HIG

r
ansition

Watchdog: Timeout OR V

Low

atc

: T

ut O

DD L

(No

)

Wake-Up

4 Denotes priority

State Machine Description
Nostop = Nostop bit = 1
!Nostop = Nostop bit = 0
BATFAIL = Batfail bit = 1
!BATFAIL = Batfail bit = 0
V

Overtemperature = V

thermal shutdown occurs

LOW = V

below reset threshold

LOW > 100 ms = V

below reset threshold for more than 100 ms

Watchdog: Trigger = TIM1 subregister write operation
V

SUP

> BFew = V

SUP

> Battery Fail Early Warning (6.1 V typical)

Watchdog: Timeout = TIM1 register not written before watchdog timeout period

expired, or watchdog written in incorrect time window if watchdog window
selected (except Stop mode). In Normal Request mode, timeout is 355 ms
p2.2 (350 ms p3) ms.

SPI: Sleep = SPI write command to MCR register, data sleep
SPI: Stop = SPI write command to MCR register, data stop
SPI: Normal = SPI write command to MCR register, data normal
SPI: Standby = SPI write command to MCR register, data standby

Normal

Standby

Notes

42.

These two SPI commands must be sent consecutively in this sequence.

43.

If watchdog activated.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33742

Figure 11. Behavior at 33742 Power-Up

Debug Mode: Hardware and Software Debug with the
33742

When the 33742 is mounted on the same printed circuit

board as the MCU it supplies, both application software and
33742 dedicated routines must be debugged. The following
features permit software debugging by allowing the possibility
of disabling the 33742 internal software watchdog timer.

Device Power-Up, Reset Terminal Connected to V

At 33742 power-up, V

voltage is provided; however, if no

SPI communication occurs to configure the device, a reset
occurs every 350 ms. In order to allow software debug and
avoid MCU reset, the

RST

terminal can be connected directly to

by a jumper.

Debug Modes with Software Watchdog Disabled Though
SPI (Normal Debug, Standby Debug, and Stop Debug)

The watchdog software can be disabled through SPI. To

avoid unwanted watchdog disable while limiting the risk of
disabling the watchdog during 33742 normal operation,
watchdog disable must be done using the following sequence:

· Step 1Power down the 33742.
· Step 2Power up the 33742. This sets the BATFAIL bit,

allowing the 33742 to enter Normal Request mode.

· Step 3Write to the TIM1 subregister to allow the 33742

to enter Normal mode.

· Step 4Write to the MCR register with data 0000. This

enables the debug mode. Complete SPI byte is
0001 0000.

· Step 5Write to the MCR register normal debug. SPI byte

is 0001 x101.

Important While in debug mode, the 33742 can be used

without having to clear the watchdog on a regular basis to
facilitate software and hardware debug.

· Step 6To leave the debug mode, write 0000 to the MCR

At Step 2, the 33742 is in Normal Request. Steps 3, 4, and 5

should be completed consecutively and within the 350 ms time
period of the Normal Request mode. If not, the 33742 will go
into Reset mode and enter Normal Request again.

Figure 12,

page 26, illustrates debug mode selection.

Power-Up

Reset

Normal

Request

Normal

Trigger

Batfail

No Stop

Sleep

Yes

Behavior after power-up if no trigger appears

Behavior after reset of BATFAIL if no trigger appears

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

33742

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

Figure 12. Entering Debug Mode

When the 33742 is in debug mode and has been set into

Stop Debug or Sleep, a wake-up causes the 33742 to enter the
Normal Request mode for 350 ms. To avoid having the 33742
generate a reset (enter Reset mode), the desired next debug
mode (Normal Debug or Standby Debug) should be configured
within the 350 ms time period of the Normal Request mode.

To avoid entering debug mode after a power-up, first read

the BATFAIL bit (MCR read) and write 0000 into the MCR
register.

Figure 13

below and

Figure 14

, page 27, show the detailed

operation of the 33742 once the debug mode has been
selected.

Figure 13. Transitions to Enter Debug Modes

SUP

SPI

MCR (Step 4)

BATFAIL

Debug Mode

MCR (Step 5)

SPI: Read BATFAIL

MCR (Step 6)

33742/33742S in Debug mode.

33742/33742S not in Debug mode.

TIM1(Step 3)

No Watchdog

Watchdog ON

Normal Request

Standby Debug

SPI: MCR (0000) and Normal Debug

Normal

t
c
h
d

r
i
g

Reset

Reset Counter

(3.4 ms) Expired

Watchdog: Timeout 350 ms

Normal Debug

SPI: MCR (0000) and Standby Debug

Power
Down

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33742

Figure 14. Simplified 33742 State Diagram in Debug Modes

Wake-Up

SPI

:
S

t
andb

tchd

og:

r
ig

ger

Wake-Up

Normal Request

Standby Debug

I
:
Nor

al Debu

Normal

Watc

hdog

: Trig

ger

Standby

SPI: Standby Debug

t
a
ndby Debu

I: N

orm

al D

ebu

Reset

Reset Counter

(3.4 ms) Expired

Watchdog: Timeout 350 ms

F
A

I
L

& NO

& SP

Sle

SPI: Normal Debug

Normal Debug

I: St

andb

y D

ebug

Stop Debug

t
o
p

-U

SPI

:
S

t
o
p

Deb

& CS

Low

i
g
h

r
an

t
i
on

(1) If Stop mode is

entered, it is entered without watchdog, no matter the WDSTOP bit.

(E) Debug mode entry point (Step 5 of the Debug mode entering sequence).

(R) Represents transitions to Reset mode due to VDD low.

Sleep

Stop (1)

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

33742

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

MCU Flash Programming Configuration

To allow for the possibility of downloading software into the

application memory (MCU EEPROM or Flash), the 33742 is
capable of allowing (1) V

to be forced by an external power

supply to 5.0 V and (2) the

RST

and the

WDOG

outputs to be

forced by external signal sources to 0 V or 5.0 V, both without
damaging the device. This allows, for example, the complete
application board to be supplied by external power supply and
external signal to be applied to the reset terminals. No functions
of the 33742 are operating.

Figure 15

illustrates a typical

configuration for the connection of programming and debugging
tools.

The V

regulator has an internal pass transistor between

SUP

and the V

output terminal. Biasing the V

output

terminal with a voltage greater than V

SUP

potential will force

current through the body diode of the internal pass transistor to
the V

SUP

terminal. Therefore, V

SUP

should be left open or

forced to a value equal to or above V

The

RST

terminal is periodically pulled LOW for t

RSTDUR

time

(device in reset mode), before being pulled to V

for 350 ms

typical (device in Normal Request mode). During the time reset
is LOW, the

RST

terminal sinks 5.0 mA maximum (I

PDW

Figure 15. Simplified Schematic for Microcontroller Flash Programming

33742

MCU with

RST

WDOG

SUP

(Open or > 5.0 V

Programming Bus

Note External supply and sources applied to V

RST

, and

WDOG

test points on application circuit board.

5.0 V

Programming Tool

Flash Memory

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33742

CAN BUS MODULE DESCRIPTION

Introduction

The 33742 features a high-speed CAN physical interface for

bus communication between 60 kbps up to 1.0 Mbps.

Figure 16

below is a simplified block diagram of the CAN interface of the
33742.

Figure 16. Simplified Block Diagram of CAN Interface

CAN Interface Supply

The supply voltage for the CAN driver is the V2 terminal. The

CAN interface has also a supply path from the battery line,
through the V

SUP

terminal. This path is used in CAN Sleep

mode to allow wake-up detection.

During CAN communication (transmission and reception),

the CAN interface current is sourced from the V2 terminal.
During CAN low power mode, the current is sourced from the
V

SUP

terminal.

Main Operation Modes Description

The CAN interface of the 33742 has two main operation

modes: TXRX and Sleep mode. The modes are controlled by
the CAN SPI Register. In the TXRX mode, which is used for
communication, four different slew rates are available for the
user. In the Sleep mode, the user has the option of enabling or
disabling the remote CAN wake-up capability.

CAN Driver Operation in TXRX Mode

When the CAN interface of the 33742 is in TXRX mode, the

driver has two states: recessive or dominant. The driver state is
controlled by the TXD terminal. The bus state is reported
through the RXD terminal.

When TXD is HIGH, the driver is set in recessive state, and

CANH and CANL lines are biased to the voltage set at V2
divided by 2, or approximately. 2.5 V.

When TXD is LOW, the bus is set into dominant state: CAN L

and CANH drivers are active. CANL is pulled to ground, and
CANH is pulled HIGH toward 5.0 V (voltage at V2).

The RXD terminal reports the bus state: CANH minus CANL

voltage is compared versus an internal threshold (a few
hundred millivolts). If CANH minus CANL is below the
threshold, the bus is recessive and RXD is set HIGH. If CANH
minus CANL is above the threshold, the bus is dominant and
RXD is set LOW. This is illustrated in

Figure 16

, page 29.

Bus Termination (60

)

CANH Line

CANL Line

TXD

RXD

Differential

Receiver

Driver

2.5 V

Wake-Up

Receiver

Pattern

Recognition

Internal

SUP

Wake-Up

Signal

CANH

CANL

SPI Control

SPI control

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

33742

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

Figure 17. CAN Interface Levels

TXD and RXD Terminals

The TXD terminal has an internal pullup to V2. The state of

TXD depends on the V2 status. RXD is a push-pull structure,
supplied by V2. When V2 is set at 5.0 V and CAN is TXRX
mode, RXD reports bus status. For details, refer to

Table 2

page 20,

Table 4

, below, and

Table 5

, page 31.

CAN TXRX Mode and Slew Rate Selection

The slew rate selection is done via CAN register (refer to

Tables 16

through

on page 40). Four slew rates are

available, and controls the recessive to dominant and dominant
to recessive transitions. The delay time from TXD terminal to
CAN bus, from CAN bus to RXD and the TXD to RXD loop time
is affected by the slew rate selection.

CANH

TXD

RXD

Typ 2.5 V

CANL

CAN Recessive State

CAN Dominant State

CAN Recessive State

Typ 2.5 V

CANH

-V

CANL

> 900 mV

CANH

-V

CANL

< 500 mV

Table 4. CAN Interface/33742 Modes and Terminal Status--Operation with Ballast on V2

(Note 44)

Mode

CAN Mode

(Controlled by SPI)

V2 Voltage

TXD Terminal

RXD Terminal

CANH/CANL

(Disconnected

from Other Node)

CAN

Communication

Unpowered

0 V

LOW

Floating to GND

Reset (with Ballast)

0 V

LOW

Floating to GND

Normal Request

(with Ballast)

0 V

LOW

Floating to GND

Normal

Sleep

5.0 V

0 V

5.0 V

Floating to GND

Normal

Slew Rate 0, 1, 2, 3

5.0 V

Internal Pullup

to V2

Report Bus State

HIGH if Bus

Recessive,

LOW if dominant

Bus Recessive

CANH = CANL =

2.5 V

YES

Standby with

External Ballast

Normal or Sleep

0 V

LOW

Floating to GND

Sleep

0 V

LOW

Floating to GND

NO.

Wake-up if enabled

Stop

Sleep

0 V

LOW

Floating to GND

NO.

Wake-up if enabled

Notes

44. See also

Figure 28,

page 46.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33742

CAN Sleep Mode

The 33742 offers two CAN Sleep modes:

· Sleep mode with CAN wake-up enable: detection of

incoming CAN message and SBC wake-up.

· Sleep mode with CAN wake-up disable: no detection of

incoming CAN message.

The CAN Sleep mode is done via the CAN SPI register.

In CAN Sleep mode (with wake-up enable or disable), the

CAN interface is internally supplied from the V

SUP

terminal. The

voltage at V2 terminal can be either 5.0 V or turned off. When

the CAN is in Sleep mode, the current sourced from V2 is
extremely low. In most cases the V2 voltage is off; however, the
CAN can be placed into Sleep mode even with 5.0 V applied on
V2.

In CAN Sleep mode, the CANH and CANL drivers are

disabled, and the receiver is also disabled. CANH and CANL
are high ohmic termination to ground.

CAN Signals in TXRX and Sleep Modes

When the CAN interface is set back into TXRX mode by an

SPI command, CAN H and CANL are set in recessive level.
This is illustrated in

Figure 18

Figure 18. CAN Signals in TXRX and Sleep Modes

Table 5. CAN Interface/33742 Modes and Terminal Status--Operation without Ballast on V2

(Note 45)

Mode

CAN Mode

(Controlled by SPI)

V2 Voltage

TXD Terminal

RXD Terminal

CANH/CANL

(Disconnected

from Other Node)

CAN

Communication

Unpowered

0 V

LOW

Floating to GND

Reset (with Ballast)

0 V

LOW

Floating to GND

Normal Request

without Ballast.

V2 Connected to V

5.0 V

LOW

5.0 V

Floating to GND

Standby without

External Ballast, V2

connected to V

Normal or Sleep

5.0 V

0 V

5.0 V

Floating to GND

Normal without

External Ballast. V2

Connected to V

Normal

Slew Rate 0, 1, 2,3

5.0 V

Bus Recessive

CANH = CANL =

2.5 V

YES

Normal without

External Ballast, V2

Connected to V

Sleep

5.0 V

0 V

5.0 V

Floating to GND

Sleep

0 V

LOW

Floating to GND

NO.

Wake-up if enabled

Stop

Sleep

0 V

LOW

Floating to GND

NO.

Wake-up if enabled

Notes

45. See also

Figure 29,

page 47.

CANL

CANH

TXD

RXD

Ground

2.5 V

CANL Dominant

CANH Dominant

CANL/CANH Recessive

CAN in TXRX Mode

CAN in Sleep Mode

(Wake-Up Enable or Disable)

CAN in TXRX Mode

(Controlled by SPI Command)

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

33742

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

CAN in Sleep Mode with Wake-Up Enable

When the CAN interface is in Sleep mode with wake up

enable, the CAN bus traffic is detected. The CAN bus wake up
is a pattern wake up.

Pattern Wake-Up

In order to wake up the CAN interface, the following criteria

must be fulfilled:

· The CAN interface wake-up receiver must receive a

series of three consecutive valid dominant pulses, each of
them has to be longer than 500 ns and shorter than
500

µs.

· The distance between 2 pulses must be lower than

500

µs.

· The three pulses must occur within a time frame of 1.0 ms.

The pattern wake-up of the 33742 CAN interface allow wake-up
by any CAN message content.

Figure 19

below illustrates the CAN signals during a CAN

bus Sleep state and wake-up sequence.

Figure 19. CAN Bus Signal During Can Sleep State and Wake-Up Sequence

CANL

CANH

TXD

RXD

Ground

2.5 V

CANL Dominant

CANH Dominant

CANL/CANH Recessive

CAN in TXRX Mode

CAN in Sleep Mode (Wake-Up Enable)

Incoming CAN Message

CANL Dominant

CANH Dominant

CANL Dominant

CANH Dominant

CANL Dominant

CANH Dominant

WU Receiver

Internal Wake-Up Signal

Min 500 ns
Max 500

µs

CAN Bus Sleep State

Pulse # 1

Pulse # 2

Pulse # 3

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33742

Figure 20

illustrates how the wake-up signal is generated.

First the CAN signal is detected by a low consumption receiver
(WU receiver). Then the signal passes through a pulse width
filter, which discards the undesired pulses. The pulse must
have a width bigger than 0.5

µs and smaller than 500 µs to be

accepted. When a pulse is discarded, the pulse counter is reset

and no wake-up signal is generated. When a pulse is accepted,
the pulse counter is incremented and, after three pulses, the
internal wake-up signal is asserted.

Each one of the pulses must be spaced by no more than

500

µs. If not, the counter will be reset and no wake-up signal

will be generated. This is accomplished by the wake-up timeout
generator. The wake-up cycle is completed (and the wake-up
flag reset) when the CAN interface is brought to CAN Normal
mode.

Figure 20. Wake-Up Functional Block Diagram

CAN Wake-Up Report

The CAN wake-up reports depend upon the 33742 low

power mode.

If the 33742 is placed into Sleep mode (V

and V2 off), the

CAN wake-up or any wake-up results in V

regulator turn on,

leading to MCU supply turn on and reset release. If the 33742
is in Stop mode (V2 off and V

active), the CAN wake-up or

any wake-up is signalled by a pulse on the INT output. In
addition the CAN-WU bit is set in the CAN register.

If the 33742 is in Normal or Standby mode and the CAN

interface is in Sleep mode with wake-up enable, the CAN wake-
up is reported by the bit CANWU in the CAN register.

In the event the 33742 is in Normal mode and CAN Sleep

mode with wake-up enable, it is recommended that the user
check for the CAN WU bit prior to setting the 33742 in Sleep or
Stop mode in case bus traffic has occurred while the CAN
interface was in Sleep mode.

After CAN wake-up, a flag is set in the CAN register. Bit

CAN-WU reports the CAN wake-up event while the 33742 was
in Sleep or Stop mode. This bit is set until the CAN is in placed
by SPI command into TXRX mode and the CAN register read.

Internal Wake-Up

Latch

RST

Timeout

RST

Counter

Pulse OK

Narrow

Pulse

Pulse Width

Filter

Timeout

Generator

Standby

WU Receiver

CANH

CANL

Signal

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

33742

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

CAN Bus Diagnostic

The 33742 can diagnose CANH or CANL lines short to GND,

short to V

SUP

, and short to

As illustrated in

Figure 21

, several single-ended

comparators are implemented on the CANH and CANL bus

lines. These comparators monitor the bus level in recessive and
dominant states. The information is then managed by a logic
circuit to properly determine the failure and report it.

Table 6

indicates the state of the comparators in the event of bus failure
and the state of the drivers; that is, whether they are recessive
or dominant.

Figure 21. CAN Bus Simplified Structure

Table 6. Short to GND, Short to V

SUP

, and Short to 5.0 V Detection Truth Table

Failure Description

Driver Recessive State

Driver Dominant State

Lg (Threshold 1.75 V)

Hg (Threshold 1.75 V)

Lg (Threshold 1.75 V)

Hg (Threshold 1.75 V)

No failure

CANL to GND

CANH to GND

Lb (Threshold V

SUP

-2.0 V) Hb (Threshold V

SUP

-2.0 V) Lb (Threshold V

SUP

-2.0 V) Hb (Threshold V

SUP

-2.0 V)

No failure

CANL to

SUP

CANH to

SUP

L5 (Threshold V

-0.43 V) H5 (Threshold V

-0.43 V) L5 (Threshold V

-0.43 V) H5 (Threshold V

-0.43 V)

No failure

CANL to V

CANH to V

CANH

CANL

Vrg

Vrvb

Logic

TXD

Diagnostic

(5.0 V)

GND (0 V)

Recessive Level (2.5 V)

SUP

(12 V14 V)

Vrvb (V

SUP

- 2.0 V)

Vrg (1.75 V)

CANL Dominant Level (1.4 V)

CANH Dominant Level (3.6 V)

Vr5

Vr5 (V

- 0.43 V)

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33742

Detection Principle

In the recessive state, if one of the two bus lines is shorted to

GND, V

or V

SUP

, then voltage at the other line follows the

shorted line due to bus termination resistance and the high
impedance of the driver. For example, if CANL is shorted to
GND, CANL voltage is zero, and CANH voltage, as measured
by the Hg comparator, is also close to zero.

In the recessive state the failure detection to GND or V

SUP

possible. However, it is impossible to distinguish which bus line,
CANL or CANH, is shorted to GND or V

SUP

. In the dominant

state, the complete diagnostic is possible once the driver is
turned on.

CAN Bus Failure Reporting

CANL bus line failures (for example, CANL short to GND) is

reported in the SPI register TIM1/2. CANH bus line (for
example, CANH short to V

SUP

) is reported in the LPC register.

In addition CANF and CAN-UF bits in the CAN register

indicate that a CAN bus failure has been detected.

Non-Identified and Fully Identified Bus Failures

As indicated in

Table 6

, page 34, when the bus is in a

recessive state it is possible to detect an error condition;
however, is it not possible to fully identify which error. This is
called "non-identified" or "under-acquisition" bus failure. If there
is no communication (i.e., bus idle), it is still possible to warn the
MCU that the device has started to detect a bus failure.

In the CAN register, bits D2 and D1 (CAN-F and CAN-UF,

respectively) are used to signal bus failure. Bit D2 reports a bus
failure and bit D1 indicates if the failure is identified or not (bit
D1 is set to 1 if the error is not identified).

When the detection mechanism is complete, the error will be

fully detected and reported in the TIM1/2 and LPC registers and
bit D1 will be reset to 0.

Number of Samples for Proper Failure Detection

The failure detector requires at least one cycle of recessive

and dominant state to properly recognize the bus failure. The
error will be fully detected after five cycles of recessive-
dominant states. As long as the failure detection circuitry has
not detected the same error for five recessive-dominant cycles,
the bit "non-identified failure" (CAN-UF) will be set.

RXD Permanent Recessive Failure

The purpose of this detection mechanism is to diagnose an

external hardware failure at the RXD output terminal and to
ensure that a permanent failure at the RXD terminal does not
disturb network communication.

In the event RXD is shorted to

a permanent high level signal (i.e., 5.0 V), the CAN protocol
module within the MCU cannot receive any incoming message.
Additionally, the CAN protocol module cannot distinguish the
bus idle state and could start communication at any time. To
prevent this, an RXD failure detection, as illustrated in

Figure 22

and explained below, is necessary.

Figure 22. RXD Path and RXD Permanent Recessive Detection Principle

RXD Failure Detection

The 33742 senses the RXD output voltage at each LOW-to-

HIGH transition of the differential receiver. Excluding internal
propagation delay, RXD output should be LOW when the
differential receiver is LOW. In the event RXD is shorted to
5.0 V (e.g., to V

), RXD will be tied to a high level and the RXD

short to 5.0 V can be detected at the next LOW-to-HIGH
transition of the differential receiver. Compete detection
requires three samples.

When the error is detected, the flag is latched and the CAN

driver is disabled. The error is reported through the SPI register
LPC, bit RXPR.

Recovery Condition

The internal recovery is completed by the sampling of a

correct low level at TXD, as illustrated in

Figure 23

, page 36.

As soon as the RXD permanent recessive is detected, the

RXD driver is deactivated and a weak pulldown current source

CANH

CANL

Diff

RXD Sense

RXD

TXD

Logic

Diag

CANL

Diff Output

RXD Output

RXD Short to V

Prop Delay

RXD Flag

RXD Flag Latched

2.0 V

Sampling

Sampling Sampling

Note RXD Flag is neither the RXPR bit in the LPC register nor the CAN

F bit in the INTR register.

CANH

Driver

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

33742

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

is activated in order to allow recovery conditions. The driver
stays disabled until the failure is cleared (RXD no longer
permanent recessive) and the bus driver is activated by an SPI
register command (write 1 to the CANCLR bit in the CAN
register).

Figure 23. RXD Recovery Conditions

TXD Permanent Dominant Failure

Principle

In the event TXD is set to a permanent low level, the CAN

bus is set into dominant level, and no communication is
possible. The 33742 has a TXD permanent timeout detector.
After timeout, the bus driver is disabled and the bus is released
in a recessive state. The TXD permanent dominant failure is
reported in the TIM1 register.

Recovery

The TXD permanent dominant is used and activated also in

case of TXD short to RXD. The recovery condition for TXD
permanent dominant (recovery means the reactivation of the
CAN drivers) is done by an SPI command and is controlled by
the MCU.

The driver stays disabled until the failure is cleared (TXD no

longer permanent dominant) and the bus driver is activated by
an SPI register command (write 1 to bit CANCLR in the CAN
register).

TXD to RXD Short Circuit Failure

Principle

In the event TXD is shorted to RXD when an incoming CAN

message is received, RXD is set LOW. Consequently, the TXD
terminal is LOW and drives CANH and CANL into the dominant
state. The bus is stuck in dominant and no further
communication is possible.

Detection and Recovery

The TXD permanent dominant timeout will be activated and

release the CANL and CANH drivers. However, at the next
incoming dominant bit, the bus will then be stuck again in
dominant. In order to avoid this situation, the recovery of the
failure (recovery means the reactivation of the CAN drivers) is
done by an SPI command and controlled by the MCU.

Internal Error Output Flags

There are internal error flags to signal whenever thermal

protection is activated or overcurrent detection occurs on the
CANL or CANH terminals (bit THERM-CUR). The errors are
reported in the CAN register.

CANL

Diff Output

RXD Output

RXD Short to V

RXD Flag

RXD Flag Latched

Sampling

Note RXD Flag is neither the RXPR bit in the LPC register

RXD no longer shorted to V

CANH

nor the CAN-F bit in INTR register.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33742

DEVICE FAULT OPERATION

Table 7

describes the relationship between device fault or

warning and the operation of the V

, V2, CAN, and HS

interface.

Table 7. Fault/Warning

Fault/Warning

CAN

Battery Fail

Turn OFF

Turn OFF due to V2.

No communication

OFF

Temperature

Prewarning

Warning flag only.

Leave as is

No change

Overtemperature

Turn OFF

Turn OFF due to V2.

No communication

OFF

Overcurrent

regulator enters linear

mode. V

undervoltage

reset may occurs. V

overtemperature

prewarning or shutdown

may occur

Turn OFF if V

undervoltage reset occurs

If V2 is OFF, turn OFF

and no communication

Turn OFF if V

undervoltage reset occurs

Short Circuit

undervoltage reset

occurs. V

overtemperature

prewarning or shutdown

may occur

Turn OFF

Turn OFF due to V2.

No communication

OFF

Watchdog Reset

Turn OFF

Turn OFF due to V2.

No communication

OFF

V2LOW (e.g., V2 < 4.0 V)

No change

V2 out of range

Turn OFF due to V2 low

No change

HS Overtemperature

No change

OFF

HS Overcurrent

No change

HS overtemperature

may occur

SUP

LOW

No change

CAN Overtemperature

No change

Disable. As soon as

temperature falls, CAN is

re-enabled automatically

No change

CAN Overcurrent

No change

(Note 46)

No change

CANH Short to GND

No change

(Note 47)

No communication

(Note 48)

No change

CANH Short to V

No change

Communication OK

No change

CANH Short to V

SUP

No change

Communication OK

No change

CANL Short to GND

No change

Communication OK

No change

CANL Short to V

No change

No communication

(Note 48)

No change

CANL Short to V

SUP

No change

No communication

(Note 48)

No change

Notes

46.

Refer to descriptions of CANH and CANL short to GND, V

, and V

SUP

elsewhere in table.

47.

Peak current 150 mA during TXD dominant only. Due to loss of communication, CAN controller reaches bus OFF state. Average current
out of V2 is below 10 mA.

48.

Overcurrent might be detected. Bit THERM-CUR set in CAN register.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

33742

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

SPI INTERFACE AND REGISTER DESCRIPTION

Data Format Description

Figure 24

illustrates a register, an 8-bit SPI. The first three

bits are used to identify the internal 33742 register address.
Bit 4 is a read/write bit. The last four bits are data sent from the
MCU to the 33742 or read back from the 33742 to the MCU.

The state of the MISO has no significance during the write

operation. However, during the read operation the final four bits
of MISO have meaning; namely, they contain the content of the
accessed register.

Figure 24. Data Format Description

Table 8

lists the possible reset conditions.

Table 8. Possible Reset Conditions

Register Descriptions

The following tables in this section describe the SPI register

list and register bit meaning. Register reset value is also
described, along with the reset condition. Reset condition is the
condition causing the bit to be set at the reset value.

Bit 7

Bit 5

Bit 3

Bit 4

Bit 2

Bit 6

Bit 1 Bit 0

R/W

MISO

MOSI

Address

Data

Note Read operation: R/W bit = 0; Write operation: R/W = 1.

Condition

Name

Definition

33742 Reset

POR

Power-ON Reset

33742 Mode
Transition

NR2R

Normal Request to Reset Mode

NR2N

Normal Request to Normal Mode

NR2STB

Normal Request to Standby Mode

N2R

Normal to Reset Mode

STB2R

Standby to Reset Mode

STO2R

Stop to Reset Mode

STO2NR

Stop to Normal Request

33742 Mode

RESET

33742 in Reset Mode

Table 9. List of Registers

Register

Address

Formal Name

and Link

Comment and Use

Write

Read

MCR

$000

Mode Control Register (MCR)

on page 39

Selection for Normal, Standby, Sleep,
Stop, and Debug modes

BATFAIL, general failure, V

pre-

warning, and Watchdog flag

RCR

$001

Reset Control Register (RCR)

on page 40

Configuration for reset voltage level, CAN Sleep and Stop modes

CAN

$010

CAN Register (CAN) on page

CAN slew rate, Sleep and Wake-Up
enable/disable modes, drive enable after
failure

CAN wake-up and CAN failure status bits

IOR

$011

Input/Output Register (IOR)

on page 41

HS (High Side switch) control in Normal
and Standby mode

HS overtemperature bit, V

SUP

, and V2

Low status

WUR

$100

Wake-Up Register (WUR) on

page 42

Control of wake-up input polarity

Wake-up input and real time Lx input state

TIM

$101

Timing Register (TIM1/2) on

page 43

· TIM1: Watchdog timing control,

Watchdog Window (WDW) or
Watchdog Timeout (WTO) mode

· TIM2: Cyclic Sense and Forced

Wake-Up timing selection

CANL and TXD failure reporting

LPC

$110

Low Power Control Register

(LPC) on page 44

Control HS periodic activation in Sleep
and Stop modes, Forced Wake-Up mode
activation, CAN-INT mode selection

CANH and RXD failure reporting

INTR

$111

Interrupt Register (INTR) on

page 45

Enable or Disable of Interrupts

Interrupt source

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33742

Mode Control Register (MCR)

Tables 10

through

describe various Mode Control

------------------------------------

Table 10. Mode Control Register

MCR

R/W

$000b

MCTR2

MCTR1

MCTR0

BATFAIL

(Note 49)

VDDTEMP

GFAIL

WDRST

Reset
Value

Reset

Condition

(Write)

(Note 50)

POR,

RESET

POR,

RESET

POR,

RESET

Notes

49.

BATFAIL bit cannot be set by SPI. BATFAIL is set when V

SUP

falls below 3.0 V.

50.

See

Table 8

, page 38, for definitions of reset conditions.

Table 11. Mode Control Register Control Bits

MCTR2 MCTR

MCTR

33742 Mode

Description

Enter/Exit

Debug Mode

To enter/exit Debug
Mode, refer to detailed
description in

Debug

Mode: Hardware and
Software Debug with
the 33742

, page 25.

Normal

Standby

Stop,

Watchdog OFF

(Note 51)

Stop,

Watchdog ON

(Note 51)

Sleep

(Note 52)

Normal

No Watchdog running.
Debug Mode.

Standby

Stop

Notes

51.

Watchdog ON or OFF depends on RCR bit D3.

52.

Before entering Sleep mode, bit BATFAIL in MCR must be
previously cleared (MCR read operation), and bit NOSTOP in
RCR must be previously set to 1.

Table 12. Mode Control Register Status Bits

Name

Value

Description

BATFAIL

SUP

was not below V

SUP

has been below V

VDDTEMP

No overtemperature pre-warning.

Temperature pre-warning on V

regulator (bit latched).

GFAIL

No failure.

CAN Failure or HS overtemperature or
V2 low.

WDRST

No watchdog reset occurred.

Watchdog reset occurred.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

33742

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

Reset Control Register (RCR)

Tables 13

and

contain various Reset Control Register

information.

------------------------------------

CAN Register (CAN)

Tables 15

through

contain various CAN register

information.

Table 15

describes control of the high-speed CAN

module, mode, slew rate, and wake-up.

High-Speed CAN Transceiver Modes

The MODE bit (D0) controls the state of the CAN interface,

TXRX or Sleep mode (

Table 17

). SC0 bit (D1) defines the slew

rate when the CAN module is in TXRX, and it controls the wake-
up option (wake-up enable or disable) when the CAN module is
in Sleep mode.

Table 13. Reset Control Register

RCR

R/W

$001b

WDSTOP

NOSTOP

CAN

SLEEP

RSTTH

Reset Value

Reset

Condition

(Write)

(Note 53)

POR,

RESET,

STO2NR

POR,

NR2N,

NR2STB

POR,

NR2N,

NR2STB

POR

Notes

53.

See

Table 8

, page 38, for definitions of reset conditions.

Table 14. Reset Control Register Control Bits

Name

Value

Description

WDSTOP

No Watchdog in Stop Mode.

Watchdog runs in Stop Mode.

NOSTOP

Device cannot enter Sleep Mode.

Sleep mode allowed. Device can enter
Sleep Mode.

CAN

SLEEP

CAN Sleep Mode disable (despite D0 bit
in CAN register).

CAN Sleep Mode enabled (in addition to
D0 in CAN register).

RSTTH

Reset Threshold 1 selected (typ 4.6 V).

Reset Threshold 2 selected (typ 4.2 V).

Table 15. CAN Register

CAN

R/W

$010b

CANCLR

SC1

SC0

MODE

CANWU

CAN-F

CAN-UF

THERM-

CUR

Reset Value

Reset

Condition

(Write)

(Note 54)

POR

NR2N,

STB2N

Notes

54.

See

Table 8

, page 38, for definitions of reset conditions.

Table 16. CANCLR Control Bits

Value

Description

No effect.

Re-enables CAN driver after TXD permanent
dominant or RXD permanent recessive failure
occurred. Failure recovery conditions must occur to
re-enable.

Table 17. CAN High-Speed Transceiver Modes

SC1

SC0

MODE

CAN Mode

(Pass 1.1)

CAN TXRX, Slew Rate 0

CAN TXRX, Slew Rate 1

CAN TXRX, Slew Rate 2

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33742

------------------------------------

Input/Output Register (IOR)

Tables 19

through

contain various Input/Output Register

information.

Table 20

provides information about HS control in

Normal and Standby modes, while

Table 21

provides status bit

information.

------------------------------------

Table 18. CAN Register Status Bits

Name

Value

Description

CANWU

No CAN wake-up occurred.

CAN wake-up occurred.

CAN-F

No CAN failure.

CAN failure

(Note 55)

CAN-UF

Identified CAN failure

(Note 55)

identified CAN failure.

THERM-

CUR

No overtemperature or overcurrent on
CANH or CANL drivers.

Overtemperature or overcurrent on
CANH or CANL drivers.

Notes

55.

Error bits are latched in the CAN register.

Table 19. Input/Output Register

IOR

R/W

$011b

HSON

V2LOW

HSOT

VSUPLOW

DEBUG

Reset
Value

Reset

Condition

(Write)

(Note 56)

POR

Notes

56.

See

Table 8

, page 38, for definitions of reset conditions.

Table 20. HSON Control Bits

Value

HS State

HS OFF, in Normal and Standby modes.

HS ON, in Normal and Standby modes

(Note 57)

Notes

57.

When HS is turned OFF due to an overtemperature condition,
it can be turned ON again by setting the appropriate control bit
to 1. Error bits are latched in the IOR register.

Table 21. Input/Output Register Status Bits

Name

Value

Description

V2LOW

V2 > 4.0 V.

V2 < 4.0 V.

HSOT

No HS overtemperature.

HS overtemperature.

VSUPLOW

SUP

> 6.1 V.

SUP

< 6.1 V.

DEBUG

33742 not in Debug mode.

33742 accepts command to go to
Debug modes (no Watchdog).

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

33742

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

Wake-Up Register (WUR)

Tables 22

through

contain various Wake-Up Register

information. Local wake-up inputs L0:L3 can be used in both
Normal and Standby modes as port expander, as well as for
waking up the 33742 from Sleep or Stop modes (

Table 22

Wake-up inputs can be configured by pair. L0 and L1 can be

configured together, and L2 and L3 can be configured together
(

Table 23

------------------------------------

Table 22. Wake-Up Register

WUR

R/W

$100b

LCTR3

LCTR2

LCTR1

LCTR0

L3WU

L2WU

L1WU

L0WU

Reset
Value

Reset

Condition

(Write)

(Note 58)

POR, NR2R, N2R, STB2R, STO2R

Notes

58.

See

Table 8

, page 38, for definitions of reset conditions.

Table 23. Wake-Up Register Control Bits

LCTR3 LCTR2 LCTR1 LCTR0

L0:L1 Config

L2:L3 Config

Inputs Disabled

High Level

Sensitive

Low Level

Sensitive

Both Level

Sensitive

Inputs Disabled

High Level

Sensitive

Low Level

Sensitive

Both Level

Sensitive

x = Don't care.

Table 24. Wake-Up Register Status Bits

(Note 59)

Name

Value

Description

L3WU

0 or 1

If bit = 1, wake-up occurred from Sleep
or Stop modes; if bit = 0, no wake-up
has occurred.
When device is in Normal or Standby
mode, bit reports the State on Lx
terminal (LOW or HIGH) (0 = Lx LOW,
1 = Lx HIGH)

L2WU

0 or 1

L1WU

0 or 1

L0WU

0 or 1

Notes

59.

WUR status bits have two functions. After 33742 wake-up,
they indicate the wake up source; for example, L2WU set at 1
if wake-up source is L2 input. After 33742 wake-up and once
the WUR register

has been read, status bits indicate the real-

time state of the Lx inputs (1 = Lx is above threshold, 0 = Lx
input is below threshold). If after a wake-up from Lx input a
watchdog timeout occurs before the first reading of the WUR
register, the LxWU bits are reset. This can occur only if the
33742 was in Stop Mode.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33742

Timing Register (TIM1/2)

Tables 25

through

contain various Timing Register

information. The TIM register is composed of two subregisters:

1. TIM1--Controls the watchdog timing selection as well as

either the watchdog window or the watchdog timeout
option (

Figure 25

and

Figure 26

, respectively). TIM1 is

selected when bit D3 is 0 (

Table 25

). Watchdog timing

characteristics are described in

Table 26

2. TIM2--Selects an appropriate timing for sensing the

wake-up circuitry or cyclically supplying devices by
switching the HS on or off. TIM2 is selected when bit D3
is 1 (

Table 27

Figure 27

, page 44, describes HS

operation when cyclic sense is selected

Cyclic sense

timing characteristics are described in

Table 29

, page 44.

Both subregisters also report the CANL and TXD diagnostic.

Figure 25. Window Watchdog

Figure 26. Timeout Watchdog

Table 25. TIM1 Timing and

CANL Failure Diagnostic Register

TIM1

R/W

$101b

WDW

WDT1

WDT0

CANL2VDD CANL2BAT CANL2GND

TXPD

Reset
Value

Reset

Condition

(Write)

(Note 60)

POR,

RESET

POR,

RESET

POR,

RESET

Notes

60.

See

Table 8

, page 38, for definitions of reset conditions.

Table 26. TIM1 Control Bits

WDW WDT1 WDT0

Timing

(ms typ)

Parameter

Description

9.75

Watchdog

Period 1

No Window
Watchdog

Watchdog

Period 2

100

Watchdog

Period 3

350

Watchdog

Period 4

9.75

Watchdog

Period 1

Watchdog
Window
enabled
(Window
length is half
the Watchdog
Timing).

Watchdog

Period 2

100

Watchdog

Period 3

350

Watchdog

Period 4

Table 27. Timing Register Status Bits

Name

Value

Failure Description

CANL2VDD

No CANL short to V

CANL short to V

CANL2BAT

No CANL short to V

SUP

CANL short to V

SUP

CANL2GND

No CANL short to GND.

CANL short to GND.

TXPD

No TXD dominant

TXD dominant.

Table 28. TIM2 Timing and

CANL Failure Diagnostic

Register

TIM2

R/W

$101b

CSP2

CSP1

CSP0

CANL2VDD CANL2BAT CANL2GND

TXPD

Reset
Value

Reset

Condition

(Write)

(Note 61)

POR,

RESET

POR,

RESET

POR,

RESET

Notes

61.

See

Table 8

, page 38, for definitions of reset conditions.

Watchdog Timing x 50%

Watchdog Period

(Watchdog Timing Selected by TIM1 Bit WDW =1)

Window Closed

No Watchdog Clear Allowed

Window Open for Watchdog Clear

Watchdog Period

(Watchdog Timing Selected by TIM1 Bit WDW = 0)

Window Open for Watchdog Clear

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

33742

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

Figure 27. HS Operation When Cyclic Sense Is Selected

------------------------------------

Low Power Control Register (LPC)

Tables 30

through

contain various Low Power Control

· The state of HS in Stop and Sleep modes (HS

permanently OFF or HS cyclic).

· Enable or disable of the forced wake-up function (33742

automatic wake-up after time spent in Sleep or Stop
modes; time is defined by the TIM2 subregister).

· Enable or disable the sense of the wake-up inputs (Lx) at

the sampling point of the Cyclic Sense period (LX2HS bit).
(Refer to

Reset Control Register (RCR) on page 40

for

details of the LPC register setup required for proper cyclic
sense or direct wake-up operation.

The LPC register also reports the CANH and RXD

diagnostic.

Cyclic Sense Timing, OFF Time

time

Sample

µs

HS OFF

HS ON

Lx Sampling Point

Cyclic Sense Timing,

ON Time

Table 29. TIM2 Control Bits

CSP2 CSP1 CSP0

Cyclic Sense

Timing (ms)

Parameter

4.6

Cyclic Sense/FWU Timing 1

9.25

Cyclic Sense/FWU Timing 2

18.5

Cyclic Sense/FWU Timing 3

Cyclic Sense/FWU Timing 4

Cyclic Sense/FWU Timing 5

95.5

Cyclic Sense/FWU Timing 6

191

Cyclic Sense/FWU Timing 7

388

Cyclic Sense/FWU Timing 8

Table 30. Low Power Control Register

LPC

R/W

$110b

LX2HS

FWU

CAN-INT

HSAUTO

R CANH2VDD CANH2BAT CANH2GND

RXPR

Reset
Value

Reset

Condition

(Write)

(Note 62)

POR,

NR2R, N2R,

STB2R,

STO2R

POR,

NR2R, N2R,

STB2R,

STO2R

POR,

NR2R, N2R,

STB2R,

STO2R

POR,

NR2R, N2R,

STB2R,

STO2R

Notes

62.

See

Table 8

, page 38, for definitions of reset conditions.

Table 31. LX2HS Control Bits

Value

Wake-Up Inputs Supplied by HS

No.

Yes. Lx inputs sensed at sampling point.

Table 32. HSAUTO Control Bits

Value

Auto-Timing HS in Sleep and Stop Modes

OFF.

ON, HS Cyclic, period defined in TIM2 subregister.

Table 33. CAN-INT Control Bits

Value

(Note 63)

Description

Interrupt as soon as CAN bus failure detected.

Interrupt when CAN bus failure detected and fully
identified.

Notes

63.

If CAN-INT is at 0, any undetermined CAN failure will be
latched in the CAN register (bit D1: CAN-UF) and can be
accessed by SPI (refer to

CAN Register (CAN) on page 40

After reading the CAN register or setting CAN-INT to 1, it will
be cleared automatically. The existence of CAN-UF always
has priority over clearing, meaning that a further undetermined
CAN failure does not allow clearing the CAN-UF bit.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33742

------------------------------------

Interrupt Register (INTR)

Tables 35

through

contain various Interrupt Register

information. The INTR register allows masking or enabling the
interrupt source. A read operation identifies the interrupt
source.

Table 37

provides status bit information. The status

bits of the INTR register content are copies of the IOR, CAN,
TIM, and LPC registers status content. To clear the Interrupt
Register bits, the IOR, CAN, TIM, and/or LPC registers must be
cleared (read register) and the recovery condition must occur.
Errors bits are latched in the CAN register and the IOR register.

When the mask bit is set, the INT terminal goes low if the

appropriate condition occurs. Upon a wake-up condition from
Stop mode due to overcurrent detection (I

DDS-WU1

or I

DDS-WU2

an INT pulse is generated; however, INTR register content
remains at 0000 (not bit set into the INTR register).

Table 34. LPC Status Bits

Name

Value

Failure Description

CANH2VDD

No CANH short to V

CANH short to V

CANH2BAT

No CANH short to V

SUP

CANH short to V

SUP

CANH2GND

No CANH short to GND.

CANH short to GND.

RXPR

No RXD permanent recessive.

RXD permanent recessive.

Table 35. Interrupt Register

INTR

R/W

$111b

VSUPLOW

HSOT-

V2LOW

(Note 64)

VDDTEMP

CANF

VSUPLOW

HSOT

VDDTEMP

CANF

Reset Value

Reset

Condition

(Write)

(Note 65)

POR, RST POR, RST POR, RST POR, RST

Notes

64.

If only HSOT- V2LOW interrupt is selected (only bit D2 set in
INTR register), reading INTR register bit D2 leads to two
possibilities:
1. Bit D2 = 1: Interrupt source is HSOT.
2. Bit D2 = 0: Interrupt source is V2LOW.
HSOT and V2LOW bits status are available in the IOR register.

65.

See

Table 8

, page 38, for definitions of reset conditions.

Table 36. Interrupt Register Control Bits

Name

Description

CANF

Mask bit for CAN failures.

VDDTEMP

Mask bit for V

medium temperature

(pre-warning).

HSOT - V2LOW

Mask bit for HS overtemperature AND
V2 < 4.0 V.

VSUPLOW

Mask bit for V

SUP

< 6.1 V.

Table 37. Interrupt Register Status Bits

Name

Value

Description

VSUPLOW

No V

SUP

< 6.1 V.

SUP

< 6.1 V.

HSOT

No HS overtemperature.

HS overtemperature.

VDDTEMP

No V

medium temperature (pre-

warning).

medium temperature (pre-

warning).

CANF

No CAN failure.

CAN failure.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

33742

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

PACKAGE AND THERMAL CONSIDERATIONS

The 33742 is a standard surface mount SOIC 28 package. In

order to improve the thermal performances of the SOIC 28
package, eight terminals are internally connected to the lead
frame and are used for heat transfer to the printed circuit board.

APPLICATIONS

Figure 28

shows a typical 33742 application.

Figure 28. 33742 Typical Application Schematic

Programmable

SPI Interface

Dual Voltage Regulator

GND

RXD

TXD

SUP

monitor

Monitor

Mode Control

Reset

Watchdog

Wake-Up Input

1.0 Mbps CAN

Physical Interface

MISO

SCLK

MOSI

RST

INT

5.0 V/200 mA

V2CTRL

VDD

CANL

CANH

Oscillator

WDOG

SUP

L1
L2

Control

Interrupt

PWR

to L0

to L2

MCU

Safe Circuitry

to L1

to L3

Internal

Connector

Clamp(1)

SW4

SW3

SW2

SW1

C10

Module

Supply

Legend
D1: Example: 1N4002 type
Q1: MJD32C
R1, R2, R3, R4: 10 k

Rp, Rd: Example: 1.0 k

depending on switch type.

R5: 2.2 k

C1: 10

µF

C2: 100 nF
C3: 47

µF

C4: 100 nF
C5: 47

µF tantalum or 100 µF chemical

C6, C7, C8, C9, C10: 100 nF
(1) Clamp circuit to ensure max ratings for HS (HS from
-0.3 V to V

SUP

+ 0.3) are respected.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

HOW TO REACH US:

USA/EUROPE/LOCATIONS NOT LISTED:

JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center

Motorola Literature Distribution

3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573, Japan

P.O. Box 5405, Denver, Colorado 80217

81-3-3440-3569

1-800-521-6274 or 480-768-2130

ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre

2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong

852-26668334

HOME PAGE: http://motorola.com/semiconductors

MC33742

Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied
copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee
regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product
or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be
provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating
parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license
under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product
could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated
with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.

MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their
respective owners.

r
e

s
c

l
e

i
c

t
o

r
,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

.
.

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 33742

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 33742

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 33742