MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1
REV 1
Motorola, Inc. 1997
6/97
Dual D-Type Flip-Flop
with Set and Reset
The MC74VHC74 is an advanced high speed CMOS Dtype flipflop
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
The signal level applied to the D input is transferred to Q output during the
positive going transition of the Clock pulse.
Reset (RD) and Set (SD) are independent of the Clock (CP) and are
accomplished by setting the appropriate input Low.
The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems.
High Speed: fmax = 170MHz (Typ) at VCC = 5V
Low Power Dissipation: ICC = 2
A (Max) at TA = 25
C
High Noise Immunity: VNIH = VNIL = 28% VCC
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2V to 5.5V Operating Range
Low Noise: VOLP = 0.8V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance: HBM > 2000V; Machine Model > 200V
Chip Complexity: 128 FETs or 32 Equivalent Gates
LOGIC DIAGRAM
RD1
D1
CP1
SD1
RD2
D2
CP2
SD2
1
2
3
4
13
12
11
10
5
6
9
8
Q1
Q1
Q2
Q2
FUNCTION TABLE
Inputs
Outputs
SD
RD
CP
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H*
H*
H
H
H
H
L
H
H
L
L
H
H
H
L
X
No Change
H
H
H
X
No Change
H
H
X
No Change
* Both outputs will remain high as long as Set and Reset are low, but the output
states are unpredictable if Set and Reset go high simultaneously.
MC74VHC74
PIN ASSIGNMENT
SD1
CP1
D1
RD1
11
12
13
14
8
9
10
5
4
3
2
1
7
6
SD2
CP2
D2
RD2
VCC
Q2
Q2
GND
Q1
Q1
D SUFFIX
14LEAD SOIC PACKAGE
CASE 751A03
DT SUFFIX
14LEAD TSSOP PACKAGE
CASE 948G01
ORDERING INFORMATION
MC74VHCXXD
MC74VHCXXDT
MC74VHCXXM
SOIC
TSSOP
SOIC EIAJ
M SUFFIX
14LEAD SOIC EIAJ PACKAGE
CASE 96501
MC74VHC74
MOTOROLA
VHC Data Advanced CMOS Logic
DL203 -- Rev 1
2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage
0.5 to + 7.0
V
Vin
DC Input Voltage
0.5 to + 7.0
V
Vout
DC Output Voltage
0.5 to VCC + 0.5
V
IIK
Input Diode Current
20
mA
IOK
Output Diode Current
20
mA
Iout
DC Output Current, per Pin
25
mA
ICC
DC Supply Current, VCC and GND Pins
50
mA
PD
Power Dissipation in Still Air,
SOIC Packages
TSSOP Package
500
450
mW
Tstg
Storage Temperature
65 to + 150
_
C
* Absolute maximum continuous ratings are those values beyond which damage to the device
may occur. Exposure to these conditions or conditions beyond those indicated may adversely
affect device reliability. Functional operation under absolutemaximumrated conditions is not
implied.
Derating -- SOIC Packages: 7 mW/
_
C from 65
_
to 125
_
C
TSSOP Package: 6.1 mW/
_
C from 65
_
to 125
_
C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
DC Supply Voltage
2.0
5.5
V
Vin
DC Input Voltage
0
5.5
V
Vout
DC Output Voltage
0
VCC
V
TA
Operating Temperature, All Package Types
40
+ 85
_
C
tr, tf
Input Rise and Fall Time
VCC = 3.3V
0.3V
VCC =5.0V
0.5V
0
0
100
20
ns/V
DC ELECTRICAL CHARACTERISTICS
S
b l
P
T
C
di i
VCC
TA = 25
C
TA = 40 to 85
C
U i
Symbol
Parameter
Test Conditions
VCC
V
Min
Typ
Max
Min
Max
Unit
VIH
Minimum HighLevel
Input Voltage
2.0
3.0 to
5.5
1.50
VCC x 0.7
1.50
VCC x 0.7
V
VIL
Maximum LowLevel
Input Voltage
2.0
3.0 to
5.5
0.50
VCC x 0.3
0.50
VCC x 0.3
V
VOH
Minimum HighLevel
Output Voltage
Vin = VIH or VIL
IOH = 50
A
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
V
Vin = VIH or VIL
IOH = 4mA
IOH = 8mA
3.0
4.5
2.58
3.94
2.48
3.80
VOL
Maximum LowLevel
Output Voltage
Vin = VIH or VIL
IOL = 50
A
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL
IOL = 4mA
IOL = 8mA
3.0
4.5
0.36
0.36
0.44
0.44
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND
v
(Vin or Vout)
v
VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC74VHC74
VHC Data Advanced CMOS Logic
DL203 -- Rev 1
3
MOTOROLA
DC ELECTRICAL CHARACTERISTICS
Unit
TA = 40 to 85
C
TA = 25
C
VCC
V
Test Conditions
Parameter
Symbol
Unit
Max
Min
Max
Typ
Min
VCC
V
Test Conditions
Parameter
Symbol
Iin
Maximum Input
Leakage Current
Vin = 5.5V or GND
0 to 5.5
0.1
1.0
A
ICC
Maximum Quiescent
Supply Current
Vin = VCC or GND
5.5
2.0
20.0
A
AC ELECTRICAL CHARACTERISTICS
(Input tr = tf = 3.0ns)
S
b l
P
T
C
di i
TA = 25
C
TA = 40 to 85
C
U i
Symbol
Parameter
Test Conditions
Min
Typ
Max
Min
Max
Unit
tPLH,
tPHL
Maximum Propagation Delay,
CP to Q or Q
VCC = 3.3
0.3V
CL = 15pF
CL = 50pF
6.7
9.2
11.9
15.4
1.0
1.0
14.0
17.5
ns
VCC = 5.0
0.5V
CL = 15pF
CL = 50pF
4.6
6.1
7.3
9.3
1.0
1.0
8.5
10.5
tPLH,
tPHL
Maximum Propagation Delay,
SD or RD to Q or Q
VCC = 3.3
0.3V
CL = 15pF
CL = 50pF
7.6
10.1
12.3
15.8
1.0
1.0
14.5
18.0
ns
VCC = 5.0
0.5V
CL = 15pF
CL = 50pF
4.8
6.3
7.7
9.7
1.0
1.0
9.0
11.0
fmax
Maximum Clock Frequency
(50% Duty Cycle)
VCC = 3.3
0.3V
CL = 15pF
CL = 50pF
80
50
125
75
70
45
MHz
VCC = 5.0
0.5V
CL = 15pF
CL = 50pF
130
90
170
115
110
75
Cin
Maximum Input Capacitance
4
10
10
pF
C
P
Di
i
i
C
i
(N
1 )
Typical @ 25
C, VCC = 5.0V
F
CPD
Power Dissipation Capacitance (Note 1.)
25
pF
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR
)
= CPD
VCC
fin + ICC / 2 (per flipflop). CPD is used to determine the
noload dynamic power consumption; PD = CPD
VCC2
fin + ICC
VCC.
TIMING REQUIREMENTS
(Input tr = tf = 3.0ns)
S
b l
P
V
Guaranteed Limit
U i
Symbol
Parameter
VCC
V
TA = 25
_
C
TA = 40 to
85
_
C
Unit
tw
Minimum Pulse Width, CP
3.3
0.3
5.0
0.5
6.0
5.0
7.0
5.0
ns
tw
Minimum Pulse Width, RD or SD
3.3
0.3
5.0
0.5
6.0
5.0
7.0
5.0
ns
tsu
Minimum Setup Time, D to CP
3.3
0.3
5.0
0.5
6.0
5.0
7.0
5.0
ns
th
Minimum Hold Time, D to CP
3.3
0.3
5.0
0.5
0.5
0.5
0.5
0.5
ns
trec
Minimum Recovery Time, SD or RD to CP
3.3
0.3
5.0
0.5
5.0
3.0
5.0
3.0
ns
MC74VHC74
MOTOROLA
VHC Data Advanced CMOS Logic
DL203 -- Rev 1
4
SWITCHING WAVEFORMS
Figure 1.
Figure 2.
50%
50% VCC
50% VCC
50%
VCC
VCC
GND
GND
SD or RD
Q or Q
Q or Q
CP
tPLH
tPHL
50%
D
CP
VCC
VCC
GND
Figure 3.
VALID
GND
tsu
th
trec
tw
* Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 4.
1/fmax
CP
Q or Q
VCC
GND
50%
50% VCC
tPLH
tPHL
tw
50%
Figure 5. Input Equivalent Circuit
INPUT
MC74VHC74
VHC Data Advanced CMOS Logic
DL203 -- Rev 1
5
MOTOROLA
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A03
ISSUE F
MIN
MIN
MAX
MAX
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
J
K
M
P
R
8.55
3.80
1.35
0.35
0.40
0.19
0.10
0
5.80
0.25
8.75
4.00
1.75
0.49
1.25
0.25
0.25
7
6.20
0.50
0.337
0.150
0.054
0.014
0.016
0.008
0.004
0
0.228
0.010
0.344
0.157
0.068
0.019
0.049
0.009
0.009
7
0.244
0.019
1.27 BSC
0.050 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
A
B
P
7 PL
G
C
K
SEATING
PLANE
D
14 PL
M
J
R
X 45
1
7
8
14
0.25 (0.010)
T
B
A
M
S
S
B
0.25 (0.010)
M
M
F
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948G01
ISSUE O
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
4.90
5.10
0.193
0.200
B
4.30
4.50
0.169
0.177
C
1.20
0.047
D
0.05
0.15
0.002
0.006
F
0.50
0.75
0.020
0.030
G
0.65 BSC
0.026 BSC
H
0.50
0.60
0.020
0.024
J
0.09
0.20
0.004
0.008
J1
0.09
0.16
0.004
0.006
K
0.19
0.30
0.007
0.012
K1
0.19
0.25
0.007
0.010
L
6.40 BSC
0.252 BSC
M
0
8
0
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE W.
_
_
_
_
S
U
0.15 (0.006) T
2X
L/2
S
U
M
0.10 (0.004)
V
S
T
L
U
SEATING
PLANE
0.10 (0.004)
T
SECTION NN
DETAIL E
J J1
K
K1
DETAIL E
F
M
W
0.25 (0.010)
8
14
7
1
PIN 1
IDENT.
H
G
A
D
C
B
S
U
0.15 (0.006) T
V
14X REF
K
N
N
MC74VHC74
MOTOROLA
VHC Data Advanced CMOS Logic
DL203 -- Rev 1
6
OUTLINE DIMENSIONS
M SUFFIX
PLASTIC SOIC EIAJ PACKAGE
CASE 96501
ISSUE O
HE
A1
DIM
MIN
MAX
MIN
MAX
INCHES
2.05
0.081
MILLIMETERS
0.05
0.20
0.002
0.008
0.35
0.50
0.014
0.020
0.18
0.27
0.007
0.011
9.90
10.50
0.390
0.413
5.10
5.45
0.201
0.215
1.27 BSC
0.050 BSC
7.40
8.20
0.291
0.323
0.50
0.85
0.020
0.033
1.10
1.50
0.043
0.059
0
0.70
0.90
0.028
0.035
1.42
0.056
A1
HE
Q1
LE
_
10
_
0
_
10
_
LE
Q1
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
0.13 (0.005)
M
0.10 (0.004)
D
Z
E
1
14
8
7
e
A
b
VIEW P
c
L
DETAIL P
M
A
b
c
D
E
e
0.50
M
Z
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals"
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MC74VHC74/D
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