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MC56F8346/D

Rev. 8.0, 6/2004

56F8346

Preliminary Technical Data

56F8346 16-bit Hybrid Controller

· Up to 60 MIPS at 60MHz core frequency
· DSP and MCU functionality in a unified,

C-efficient architecture

· Access up to 1MB of off-chip program and data

memory

· Chip Select Logic for glueless interface to ROM

and SRAM

· 128KB of Program Flash
· 4KB of Program RAM
· 8KB of Data Flash
· 8KB of Data RAM
· 8KB of Boot Flash
· Two 6-channel PWM Modules
· Four 4-channel, 12-bit ADCs

· Temperature Sensor
· Two Quadrature Decoders
· Optional On-Chip Regulator
· FlexCAN module
· Two Serial Communication Interfaces (SCIs)
· Up to two Serial Peripheral Interfaces (SPIs)
· Up to four general-purpose Quad Timers
· Computer Operating Properly (COP) / Watchdog
· JTAG/Enhanced On-Chip Emulation (OnCETM) for

unobtrusive, real-time debugging

· Up to 62 GPIO lines
· 144-pin LQFP Package

56F8346 Block Diagram - 144 LQFP

Program Controller

and

Hardware Looping Unit

Data ALU

16 x 16 + 36 -> 36-Bit MAC

Three 16-bit Input Registers

Four 36-bit Accumulators

Address

Generation Unit

Bit

Manipulation

Unit

PLL

Clock

Generator

EXTAL

Interrupt

Controller

COP/

Watchdog

SCI1 or

GPIOD

External

Address Bus

Switch

ter

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e

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f
ace

i
t

CLKMODE

IRQA IRQB

External Data

Bus Switch

PDB

XAB1

XAB2

XDB2

CDBR

SCI0 or

GPIOE

SPI0 or

GPIOE

IPBus Bridge (IPBB)

Integration

Module

System

P
O
R

O
S
C

Decoding

Peripherals

Peripheral

Device Selects

RW
Control

IPAB

IPWDB

IPRDB

System Bus

R/W Control

PAB

CDBW

CDBR

CDBW

Clock

resets

JTAG/

EOnCE

Port

Digital Reg

Analog Reg

Low Voltage

Supervisor

CAP

DDA

SSA

OCR_DIS

RESET

EXTBOOT

EMI_MODE

RSTO

PWM Outputs

Fault Inputs

PWMA

Current Sense Inputs
or GPIOC

PWM Outputs

Fault Inputs

PWMB

Current Sense Inputs
or GPIOD

Quad

Timer D or

GPIOE

Quad

Timer C or

GPIOE

AD0

AD1

ADCA

Quadrature

Decoder 0 or

Quad

Timer A or

GPIOC

FlexCAN

AD0

AD1

Temp_Sense

Quadrature

Decoder 1 or

Quad

Timer B or

SPI1 or

GPIOC

CLKO

Bus Control

XTAL

DS (CS1) or GPIOD9

PS (CS0) or GPIOD8

GPIOD0-1 or CS2-3

D7-15 or GPIOF0-8

D0-6 or GPIOF9-15

GPIOB0 or A16

A8-15 or GPIOA0-7

A0-5 or GPIOA8-13

A6-7 or GPIOE2-3

VREF

ADCB

16-Bit

56800E Core

Data Memory

4K x 16 Flash

4K x 16 RAM

Memory

Program Memory

64K x 16 Flash

2K x 16 RAM

4K x 16 Boot

Flash

Control

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56F8346 Technical Data

Preliminary

Document Revision History

Version History

Description of Change

Rev 1.0

Pre-Release version, Alpha customers only

Rev 2.0

Initial Public Release

Rev 3.0

Corrected typo in

Table 10-4

, Flash Endurance is 10,000 cycles.

Additional grammar issues address

Rev 4.0

Added Package Pins to GPIO Table in

Part 8, General Purpose Input/Output (GPIO)

Added "Typical Min" values to

Table 10-17

Editing grammar, spelling, consistency of language throughout family

Updated values in Current Consumption per Power Supply Pin,

Table 10-7

Regulator Parameters

Table 10-9

External Clock Operation Timing Requirements

Table 10-13

SPI Timing

Table 10-18

ADC Parameters

Table 10-24

, and

IO Loading Coefficients at 10MHz

Table 10-25

Rev 5.0

Added

Section 4.8

added the word "access" to FM Error Interrupt in

Table 4-5

documenting only Typ. numbers for LVI in

Table 10-6

updated EMI numbers and writeup in

Section 10.9

Rev 6.0

Updated numbers in

Table 10-7

and

Table 10-8

with more recent data,

Corrected typo in

Table 10-3

in Pd characteristics.

Rev 7.0

Replace any reference to Flash Interface Unit with Flash Module, added note to Vcap pin

Table 2-2

, corrected thermal numbers for 144 LQFP in

Table 10-3

, removed

unneccessary notes in

Table 10-12

; corrected temperature range in

Table 10-14

; added

ADC calibration information to

Table 10-24

and new graphs in

Figure 10-22

Rev 8.0

Corrected EMI pin count in

Figure 1-1

, Clarification to

Table 10-23

, corrected Digital Input

Current Low (pull-up enabled) numbers in

Table 10-5

. Removed text and Table 10-2;

replaced with note to

Table 10-1

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56F8346 Technical Data

Preliminary

Part 1: Overview . . . . . . . . . . . . . . . . . . . . 4

1.1. 56F8346 Features . . . . . . . . . . . . . . . . . . 4
1.2. 56F8346 Description . . . . . . . . . . . . . . . . 5
1.3. Award-Winning Development

Environment . . . . . . . . . . . . . . . 6

1.4. Architecture Block Diagram . . . . . . . . . . . 7
1.5. Product Documentation . . . . . . . . . . . . . 10
1.6. Data Sheet Conventions . . . . . . . . . . . . 11

Part 2: Signal/Connection Descriptions 12

2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . 12
2.2. 56F8346 Signal Pins . . . . . . . . . . . . . . . 14

Part 3: On-Chip Clock Synthesis (OCCS) 31

3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . 31
3.2. External Clock Operation . . . . . . . . . . . 32
3.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . 33

Part 4: Memory Map . . . . . . . . . . . . . . . . 34

4.1. Introduction . . . . . . . . . . . . . . . . . . . . . . 34
4.2. Program Map . . . . . . . . . . . . . . . . . . . . 35
4.3. Interrupt Vector Table . . . . . . . . . . . . . . 36
4.4. Data Map . . . . . . . . . . . . . . . . . . . . . . . . 39
4.5. Flash Memory Map . . . . . . . . . . . . . . . . 40
4.6. EOnCE Memory Map . . . . . . . . . . . . . . 41
4.7. Peripheral Memory Mapped Registers . 41
4.8. Factory Programmed Memory . . . . . . . . 67

Part 5: Interrupt Controller (ITCN) . . . . . 68

5.1. Introduction . . . . . . . . . . . . . . . . . . . . . . 68
5.2. Features . . . . . . . . . . . . . . . . . . . . . . . . 68
5.3. Functional Description . . . . . . . . . . . . . . 68
5.4. Block Diagram . . . . . . . . . . . . . . . . . . . . 70
5.5. Operating Modes . . . . . . . . . . . . . . . . . . 70
5.6. Register Descriptions . . . . . . . . . . . . . . 71
5.7. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Part 6: System Integration Module (SIM) 97

6.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . 97
6.2. Features . . . . . . . . . . . . . . . . . . . . . . . . 97
6.3. Operating Modes . . . . . . . . . . . . . . . . . . 98
6.4. Operation Mode Register . . . . . . . . . . . 98
6.5. Register Descriptions . . . . . . . . . . . . . . 99
6.6. Clock Generation Overview . . . . . . . . 112
6.7. Power-Down Modes Overview . . . . . . 112
6.8. Stop and Wait Mode Disable Function 113
6.9. Resets . . . . . . . . . . . . . . . . . . . . . . . . . 113

Part 7: Security Features . . . . . . . . . . . 114

7.1. Operation with Security Enabled . . . . . 114
7.2. Flash Access Blocking Mechanisms . . 114

Part 8: General Purpose Input/Output

(GPIO) . . . . . . . . . . . . . . . . . . . . . 118

8.1. Introduction . . . . . . . . . . . . . . . . . . . . . 118
8.2. Configuration . . . . . . . . . . . . . . . . . . . . 118
8.3. Memory Maps 122

Part 9: Joint Test Action Group (JTAG) 122

9.1. 56F8346 Information . . . . . . . . . . . . . . 122

Part 10: Specifications . . . . . . . . . . . . . 123

10.1. General Characteristics . . . . . . . . . . . 123
10.2. DC Electrical Characteristics . . . . . . . 127
10.3. Temperature Sense . . . . . . . . . . . . . . 130
10.4. AC Electrical Characteristics . . . . . . . 130
10.5. Flash Memory Characteristics . . . . . . 131
10.6. External Clock Operation Timing . . . . 132
10.7. Phase Locked Loop Timing . . . . . . . . 132
10.8. Crystal Oscillator Timing . . . . . . . . . . 133
10.9. External Memory Interface Timing . . . 133
10.10. Reset, Stop, Wait, Mode Select,

and Interrupt Timing . . . . . . . 136

10.11. Serial Peripheral Interface (SPI)

Timing . . . . . . . . . . . . . . . . . . 138

10.12. Quad Timer Timing . . . . . . . . . . . . . 141
10.13. Quadrature Decoder Timing . . . . . . . 141
10.14. Serial Communication Interface

(SCI) Timing . . . . . . . . . . . . . 142

10.15. Controller Area Network (CAN)

Timing . . . . . . . . . . . . . . . . . . 143

10.16. JTAG Timing . . . . . . . . . . . . . . . . . . 143
10.17. Analog-to-Digital Converter (ADC)

Parameters . . . . . . . . . . . . . . 145

10.18. Equivalent Circuit for ADC Inputs . . . 147
10.19. Power Consumption . . . . . . . . . . . . . 147

Part 11: Packaging . . . . . . . . . . . . . . . . 149

11.1. Package and Pin-Out Information

56F8346 . . . . . . . . . . . . . . . . 149

Part 12: Design Considerations . . . . . . 153

12.1. Thermal Design Considerations . . . . . 153
12.2. Electrical Design Considerations . . . . 154
12.3. Power Distribution and I/O Ring

Implementation . . . . . . . . . . . 155

Part 13: Ordering Information . . . . . . . 156

56F8346 Data Sheet Table of Contents

Please see http://www.motorola.com/semiconductors for the most current Data Sheet revision.

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56F8346 Technical Data

Preliminary

Part 1 Overview

1.1 56F8346 Features

1.1.1

Digital Signal Processing Core

Efficient 16-bit 56800E family hybrid controller engine with dual Harvard architecture

As many as 60 Million Instructions Per Second (MIPS) at 60MHz core frequency

Single-cycle 16

16-bit parallel Multiplier-Accumulator (MAC)

Four 36-bit accumulators, including extension bits

Arithmetic and logic multi-bit shifter

Parallel instruction set with unique DSP addressing modes

Hardware DO and REP loops

Three internal address buses

Four internal data buses

Instruction set supports both DSP and controller functions

Controller-style addressing modes and instructions for compact code

Efficient C compiler and local variable support

Software subroutine and interrupt stack with depth limited only by memory

JTAG/EOnCE debug programming interface

1.1.2

Memory

Harvard architecture permits as many as three simultaneous accesses to program and data memory

Flash security protection feature

On-chip memory, including a low-cost, high-volume Flash solution

-- 128KB of Program Flash

-- 4KB of Program RAM

-- 8KB of Data Flash

-- 8KB of Data RAM

-- 8KB of Boot Flash

Off-chip memory expansion capabilities programmable for 0 - 30 wait states

-- Access up to 1MB of program memory or 1MB of data memory

-- Chip select logic for glueless interface to ROM and SRAM

EEPROM emulation capability

1.1.3

Peripheral Circuits for 56F8346

Two Pulse Width Modulator modules each with six PWM outputs, three Current Sense inputs, and
three Fault inputs; fault-tolerant design with dead time insertion; supports both center-aligned and
edge-aligned modes

Four 12-bit, Analog-to-Digital Converters (ADCs), which support four simultaneous conversions
with quad, 4-pin multiplexed inputs; ADC and PWM modules can be synchronized through Timer
C, channels 2 and 3

Two four-input Quadrature Decoders or two additional Quad Timers

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56F8346 Description

56F8346 Technical Data

Preliminary

Temperature Sensor diode can be connected, on the board, to any of the ADC inputs to monitor the
on-chip temperature

Four dedicated general-purpose Quad Timers totaling three dedicated pins: Timer C with one pin
and Timer D with two pins

Optional On-Chip Regulator

FlexCAN (CAN Version 2.0 B-compliant ) module with 2-pin port for transmit and receive

Two Serial Communication Interfaces (SCIs), each with two pins (or four additional GPIO lines)

Up to two Serial Peripheral Interfaces (SPIs), both with configurable 4-pin port (or eight additional
GPIO lines); SPI1 can also be used as Quadrature Decoder 1 or Quad Timer B

Computer Operating Properly (COP)/Watchdog timer

Two dedicated external interrupt pins

62 General Purpose I/O (GPIO) pins

External reset input pin for hardware reset

External reset output pin for system reset

Integrated low-voltage interrupt module

JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent,
real-time debugging

Software-programmable, Phase Lock Loop (PLL)-based frequency synthesizer for the core clock

1.1.4

Energy Information

Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs

On-board 3.3V down to 2.6V voltage regulator for powering internal logic and memories; can be
disabled

On-chip regulators for digital and analog circuitry to lower cost and reduce noise

Wait and Stop modes available

ADC smart power management

Each peripheral can be individually disabled to save power

1.2 56F8346 Description

The 56F8346 is a member of the 56800E core-based family of hybrid controllers. It combines, on
a single chip, the processing power of a DSP and the functionality of a microcontroller with a
flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,
configuration flexibility, and compact program code, the 56F8346 is well-suited for many
applications. The 56F8346 includes many peripherals that are especially useful for motion control,
smart appliances, steppers, encoders, tachometers, limit switches, power supply and control,
automotive control, engine management, noise suppression, remote utility metering, industrial
control for power, lighting, and automation applications.

The 56800E core is based on a Harvard-style architecture consisting of three execution units
operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style
programming model and optimized instruction set allow straightforward generation of efficient,
compact DSP and control code. The instruction set is also highly efficient for C/C++ Compilers to
enable rapid development of optimized control applications.

The 56F8346 supports program execution from either internal or external memories. Two data
operands can be accessed from the on-chip data RAM per instruction cycle. The 56F8346 also

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56F8346 Technical Data

Preliminary

provides two external dedicated interrupt lines and up to 62 General Purpose Input/Output (GPIO)
lines, depending on peripheral configuration.

The 56F8346 hybrid controller includes 128KB of Program Flash and 8KB of Data Flash (each
programmable through the JTAG port) with 4KB of Program RAM and 8KB of Data RAM. It also
supports program execution from external memory.

A total of 8KB of Boot Flash is incorporated for easy customer-inclusion of field-programmable
software routines that can be used to program the main Program and Data Flash memory areas.
Both Program and Data Flash memories can be independently bulk erased or erased in pages.
Program Flash page erase size is 1KB. Boot and Data Flash page erase size is 512 bytes. The Boot
Flash memory can also be either bulk or page erased.

A key application-specific feature of the 56F8346 is the inclusion of two Pulse Width Modulator
(PWM) modules. These modules each incorporate three complementary, individually
programmable PWM signal output pairs (each module is also capable of supporting six
independent PWM functions, for a total of 12 PWM outputs) to enhance motor control
functionality. Complementary operation permits programmable dead time insertion, distortion
correction via current sensing by software, and separate top and bottom output polarity control. The
up-counter value is programmable to support a continuously variable PWM frequency.
Edge-aligned and center-aligned synchronous pulse width control (0% to 100% modulation) is
supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors);
both BDC and BLDC (Brush and Brushless DC motors); SRM and VRM (Switched and Variable
Reluctance Motors); and stepper motors. The PWMs incorporate fault protection and
cycle-by-cycle current limiting with sufficient output drive capability to directly drive standard
optoisolators. A "smoke-inhibit", write-once protection feature for key parameters is also included.
A patented PWM waveform distortion correction circuit is also provided. Each PWM is
double-buffered and includes interrupt controls to permit integral reload rates to be programmable
from 1 to 16. The PWM modules provide reference outputs to synchronize the Analog-to-Digital
Converters through two channels of Quad Timer C.

The 56F8346 incorporates two Quadrature Decoders capable of capturing all four transitions on
the two-phase inputs, permitting generation of a number proportional to actual position. Speed
computation capabilities accommodate both fast- and slow-moving shafts. An integrated watchdog
timer in the Quadrature Decoder can be programmed with a time-out value to alert when no shaft
motion is detected. Each input is filtered to ensure only true transitions are recorded.

This hybrid controller also provides a full set of standard programmable peripherals that include
two Serial Communications Interfaces (SCIs); two Serial Peripheral Interfaces (SPIs); and four
Quad Timers. Any of these interfaces can be used as General Purpose Input/Outputs (GPIOs) if
that function is not required. A Flex Controller Area Network (FlexCAN) interface (CAN Version
2.0 B-compliant) and an internal interrupt controller are a part of the 56F8346.

1.3 Award-Winning Development Environment

Processor Expert

(PE) provides a Rapid Application Design (RAD) tool that combines

easy-to-use component-based software application creation with an expert knowledge system.

The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development
system cards will support concurrent engineering. Together, PE, CodeWarrior and EVMs create a
complete, scalable tools solution for easy, fast, and efficient development.

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Architecture Block Diagram

56F8346 Technical Data

Preliminary

1.4 Architecture Block Diagram

The 56F8346 architecture is shown in

Figure 1-1

and

Figure 1-2

Figure 1-1

illustrates how the

56800E system buses communicate with internal memories, the external memory interface and the
IPBus Bridge.

Table 1-1

lists the internal buses in the 56800E architecture and provides a brief

description of their function.

Figure 1-2

shows the peripherals and control blocks connected to the

IPBus Bridge. The figures do not show the on-board regulator and power and ground signals. They
also do not show the multiplexing between peripherals or the dedicated GPIOs. Please see

Part 2,

Signal/Connection Descriptions,

to see which signals are multiplexed with those of other

peripherals.

Also shown in

Figure 1-2

are connections between the PWM, Timer C and ADC blocks. These

connections allow the PWM and/or Timer C to control the timing of the start of ADC conversions.
The Timer C channel indicated can generate periodic start (SYNC) signals to the ADC to start its
conversions. In another operating mode, the PWM load interrupt (SYNC output) signal is routed
internally to the Timer C input channel as indicated. The timer can then be used to introduce a
controllable delay before generating its output signal. The timer output then triggers the ADC. To
fully understand this interaction, please see the 56F8300 Peripheral User Manual for clarification
on the operation of all three of these peripherals.

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56F8346 Technical Data

Preliminary

1.5 Product Documentation

The documents in

Table 1-2

are required for a complete description and proper design with the

56F8346. Documentation is available from local Motorola distributors, Motorola semiconductor
sales offices, Motorola Literature Distribution Centers, or online at
http://www.motorola.com/semiconductors.

Table 1-2 56F8346 Chip Documentation

Table 1-1 Bus Signal Names

Name

Function

Program Memory Interface

pdb_m[15:0]

Program data bus for instruction word fetches or read operations.

cdbw[15:0]

Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus
are used for writes to program memory.)

pab[20:0]

Program memory address bus. Data is returned on pdb_m bus.

Primary Data Memory Interface Bus

cdbr_m[31:0]

Primary core data bus for memory reads. Addressed via xab1 bus.

cdbw[31:0]

Primary core data bus for memory writes. Addressed via xab1 bus.

xab1[23:0]

Primary data address bus. Capable of addressing bytes

, words, and long data types. Data is written

on cdbw and returned on cdbr_m. Also used to access memory-mapped I/O.

Byte accesses can only occur in the bottom half of the memory address space. The MSB of the address will be forced to 0.

Secondary Data Memory Interface

xdb2_m[15:0] Secondary data bus used for secondary data address bus xab2 in the dual memory reads.

xab2[23:0]

Secondary data address bus used for the second of two simultaneous accesses. Capable of
addressing only words. Data is returned on xdb2_m.

Peripheral Interface Bus

IPBus [15:0]

Peripheral bus accesses all on-chip peripherals registers. This bus operates at the same clock rate
as the Primary Data Memory and therefore generates no delays when accessing the processor.
Write data is obtained from cdbw. Read data is provided to cdbr_m.

Topic

Description

Order Number

DSP56800E
Reference Manual

Detailed description of the 56800E family architecture,
and 16-bit hybrid controller core processor and the
instruction set

DSP56800ERM/D

568300 Peripheral User
Manual

Detailed description of peripherals of the 56F8300
devices

MC56F8300UM/D

56F8300 SCI/CAN
Bootloader User Manual

Detailed description of the SCI/CAN Bootloaders
56F8300 family of devices

MC56F83xxBLUM/D

56F8346
Technical Data Sheet

Electrical and timing specifications, pin descriptions,
and package descriptions (this document)

MC56F8346/D

56F8346
Product Brief

Summary description and block diagram of the
56F8346 core, memory, peripherals and interfaces

MC56F8346PB/D

56F8346
Errata

Details any chip issues that might be present

MC56F8346E/D

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56F8346 Technical Data

Preliminary

Part 2 Signal/Connection Descriptions

2.1 Introduction

The input and output signals of the 56F8346 are organized into functional groups, as detailed in

Table 2-1

and as illustrated in

Figure 2-1

. In

Table 2-2

, each table row describes the signal or

signals present on a pin.

Table 2-1 Functional Group Pin Allocations

Functional Group

Number of Pins

Power (V

or V

DDA

)

Power Option Control

Ground (V

or V

SSA

)

Supply Capacitors

& V

If the on-chip regulator is disabled, the V

CAP

pins serve as 2.5V V

DD_CORE

power inputs

PLL and Clock

Address Bus

Data Bus

Bus Control

Interrupt and Program Control

Pulse Width Modulator (PWM) Ports

Serial Peripheral Interface (SPI) Port 0

Quadrature Decoder Port 0

Alternately, can function as Quad Timer pins or GPIO

Quadrature Decoder Port 1

Pins in this section can function as Quad Timer, SPI #1, or GPIO

Serial Communications Interface (SCI) Ports

CAN Ports

Analog to Digital Converter (ADC) Ports

Timer Module Ports

JTAG/Enhanced On-Chip Emulation (EOnCE)

Temperature Sense

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Introduction

56F8346 Technical Data

Preliminary

Figure 2-1 56F8346 Signals Identified by Functional Group

(144-pin LQFP)

1. Alternate pin functionality is shown in parenthesis; pin direction/type shown is the default functionality.

DD_IO

DDA_ADC

SSA_ADC

Other

Supply

Ports

PLL

and

Clock

External
Address

Bus

or GPIO

External

Data Bus

or GPIO

SCI 0 or

GPIO

SCI 1

or GPIO

1 & V

Power

Ground

Power

Ground

A8 - A15 (GPIOA0 - 7)

TXD0 (GPIOE0)

RXD0 (GPIOE1)

TXD1 (GPIOD6)

RXD1 (GPIOD7)

TCK

TMS

TDI

TDO

TRST

Quadrature
Decoder 0
or Quad
Timer A or
GPIO

PHASEA0 (TA0, GPIOC4)

PHASEB0 (TA1, GPIOC5)

INDEX0 (TA2, GPIOC6)

HOME0 (TA3, GPIOC7)

PHASEB1 (TB1, MOSI1, GPIOC1)

INDEX1 (TB2, MISO1, GPIOC2)

HOME1 (TB3, SS1, GPIOC3)

PWMA0 - 5

ISA0 - 2 (GPIOC8 - 10)

FAULTA0 - 2

ISB0 - 2 (GPIOD10 - 12)

FAULTB0 - 3

PWMB0 - 5

ANA0 - 7

ANB0 - 7

REF

CAN_RX

CAN_TX

TC0 (GPIOE8)

TD0 - 1 (GPIOE10 - 11)

IRQA

IRQB

RESET

RSTO

SPI0 or
GPIO

PWMA or
GPIO

Quadrature
Decoder 1 or
Quad Timer B
or SPI 1 or
GPIO

PWMB or
GPIO

ADCB

ADCA

FlexCAN

QUAD TIMER
C and D or
GPIO

INTERRUPT/
PROGRAM
CONTROL

PHASEA1(TB0, SCLK1, GPIOC0)

GPIOB0 (A16)

56F8346

TEMP_SENSE

EXTAL

XTAL

CLKO

CAP

1 - V

CAP

A0 - A5 (GPIOA8 - 13)

A6 - A7 (GPIOE2 - 3)

PS (CS0)(GPIOD8)

DS (CS1)(GPIOD9)

GPIOD0 - 1 (CS2 - 3)

JTAG/

EOnCE

Port

External

Bus

Control or

GPIO

D7 - D15 (GPIOF0 - 8)

D0-D6 (GPIOF9 - 15)

EXTBOOT

MOSI0 (GPIOE5)

MISO0 (GPIOE6)

SS0 (GPIOE7)

SCLK0 (GPIOE4)

EMI_MODE

OCR_DIS

Power

CLKMODE

DDA_OSC_PLL

Temperature
Sensor

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56F8346 Technical Data

Preliminary

2.2 56F8346 Signal Pins

After reset, each pin is configured for its primary function (listed first). Any alternate functionality
must be programmed.

If the "State During Reset" lists more than one state for a pin, the first state is the actual reset state.
Other states show the reset condition of the alternate function, which you get if the alternate pin
function is selected without changing the configuration of the alternate peripheral. For example,
the A8/GPIOA0 pin shows that it is tri-stated during reset. If the GPIOA_PER is changed to select
the GPIO function of the pin, it will become an input if no other registers are changed.

Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP

Signal Name

Pin No.

Type

State

During

Reset

Signal Description

DD_IO

Supply

I/O Power -- This pin supplies 3.3V power to the chip I/O
interface.

DD_IO

119

DDA_ADC

102

Supply

ADC Power -- This pin supplies 3.3V power to the ADC
modules. It must be connected to a clean analog power
supply.

DDA_OSC_PLL

Supply

Oscillator and PLL Power -- This pin supplies 3.3V
power to the OSC and to the internal regulator that in turn
supplies the Phase Locked Loop. It must be connected to
a clean analog power supply.

Supply

-- These pins provide ground for chip logic and I/O

drivers.

144

SSA_ADC

103

Supply

ADC Analog Ground -- This pin supplies an analog
ground to the ADC modules.

OCR_DIS

Input

On-Chip Regulator Disable --
Tie this pin to V

to enable the on-chip regulator

Tie this pin to V

to disable the on-chip regulator

This pin is intended to be a static DC signal from
power-up to shut down. Do not try to toggle this pin
for power savings during operation.

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56F8346 Signal Pins

56F8346 Technical Data

Preliminary

CAP

Supply

CAP

1 - 4 -- When OCR_DIS is tied to V

(regulator

enabled), connect each pin to a 2.2

F or greater bypass

capacitor in order to bypass the core logic voltage
regulator, required for proper chip operation. When
OCR_DIS is tied to V

(regulator disabled), these pins

become V

DD_CORE

and should be connected to a

regulated 2.5V power supply.

Note: This bypass is required even if the chip is
powered with an external supply.

CAP

128

CAP

125

Input

1 - 2 -- These pins should be left unconnected as an

open circuit for normal functionality.

CLKMODE

Input

Clock Input Mode Selection -- This input determines the
function of the XTAL and EXTAL pins.

1 = External clock input on XTAL is used to directly drive
the input clock of the chip. The EXTAL pin should be
grounded.

0 = A crystal or ceramic resonator should be connected
between XTAL and EXTAL.

EXTAL

Input

External Crystal Oscillator Input -- This input can be
connected to an 8MHz external crystal. Tie this pin low if
XTAL is driven by an external clock source.

XTAL

Input/

Output

Chip-driven

Crystal Oscillator Output -- This output connects the
internal crystal oscillator output to an external crystal.

If an external clock is used, XTAL must be used as the
input and EXTAL connected to GND.

The input clock can be selected to provide the clock
directly to the core. This input clock can also be selected
as the input clock for the on-chip PLL.

CLKO

Output

Tri-Stated

Clock Output -- This pin outputs a buffered clock signal.
Using the SIM CLKO Select Register (SIM_CLKOSR), this
pin can be programmed as any of the following: disabled,
CLK_MSTR (system clock), IPBus clock, oscillator output,
prescaler clock and postscaler clock. Other signals are
also available for test purposes.

See

Section 6.5.7

for details.

Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP

Signal Name

Pin No.

Type

State

During

Reset

Signal Description

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56F8346 Technical Data

Preliminary

(GPIOA8)

138

Output

Input/

Output

Tri-stated

Input

Address Bus -- A0 - A5 specify six of the address lines
for external program or data memory accesses. Depending
upon the state of the DRV bit in the EMI bus control register
(BCR), A0 - A5 and EMI control signals are tri-stated when
the external bus is inactive.

Port A GPIO -- These six GPIO pins can be individually
programmed as input or output pins.

After reset, these pins default to address bus functionality
and must be programmed as GPIO.

To deactivate the internal pull-up resistor, clear the
appropriate GPIO bit in the GPIOA_PUR register.

Example: GPIOA8, clear bit 8 in the GPIOA_PUR register.

(GPIOA9)

(GPIOA10)

(GPIOA11)

(GPIOA12)

(GPIOA13)

(GPIOE2)

Output

Schmitt

Input/

Output

Tri-stated

Input

Address Bus -- A6 - A7 specify two of the address lines
for external program or data memory accesses. Depending
upon the state of the DRV bit in the EMI bus control register
(BCR), A6 - A7 and EMI control signals are tri-stated when
the external bus is inactive.

Port E GPIO -- These two GPIO pins can be individually
programmed as input or output pins.

After reset, the default state is Address Bus.

To deactivate the internal pull-up resistor, clear the
appropriate GPIO bit in the GPIOE_PUR register.

Example: GPIOE2, clear bit 2 in the GPIOE_PUR register.

(GPIOE3)

Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP

Signal Name

Pin No.

Type

State

During

Reset

Signal Description

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56F8346 Signal Pins

56F8346 Technical Data

Preliminary

(GPIOA0)

Output

Schmitt

Input/

Output

Tri-stated

Input

Address Bus-- A8 - A15 specify eight of the address lines
for external program or data memory accesses. Depending
upon the state of the DRV bit in the EMI bus control register
(BCR), A8 - A15 and EMI control signals are tri-stated when
the external bus is inactive.

Port A GPIO -- These eight GPIO pins can be individually
programmed as input or output pins.

After reset, the default state is Address Bus.

To deactivate the internal pull-up resistor, clear the
appropriate GPIO bit in the GPIOA_PUR register.

Example: GPIOA0, clear bit 0 in the GPIOA_PUR register.

(GPIOA1)

A10

(GPIOA2)

A11

(GPIOA3)

A12

(GPIOA4)

A13

(GPIOA5)

A14

(GPIOA6)

A15

(GPIOA7)

GPIOB0

(A16)

Schmitt

Input/

Output

Input

Tri-stated

Port B GPIO -- This GPIO pin can be programmed as an
input or output pin.

Address Bus -- A16 specifies one of the address lines for
external program or data memory accesses. Depending
upon the state of the DRV bit in the EMI bus control register
(BCR), A16 and EMI control signals are tri-stated when the
external bus is inactive.

After reset, the start-up state of GPIOB0 (GPIO or
address) is determined as a function of EXTBOOT,
EMI_MODE and the Flash security setting. See

Table 4-4

for further information on when this pin is configured as an
address pin at reset. In all cases, this state may be
changed by writing to GPIOB_PER.

To deactivate the internal pull-up resistor, clear bit 0 in the
GPIOB_PUR register.

Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP

Signal Name

Pin No.

Type

State

During

Reset

Signal Description

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56F8346 Technical Data

Preliminary

(GPIOF9)

Input/

Outpu

Input/

Outputt

Tri-stated

Input

Data Bus -- D0 - D6 specify part of the data for external
program or data memory accesses.

Depending upon the state of the DRV bit in the EMI bus
control register (BCR), D0-D6 are tri-stated when the
external bus is inactive.

Port F GPIO -- These seven GPIO pins can be
individually programmed as input or output pins.

At reset, these pins default to the EMI data bus function.

To deactivate the internal pull-up resistor, clear the
appropriate GPIO bit in the GPIOF_PUR register.

Example: GPIOF9, clear bit 9 in the GPIOF_PUR register.

(GPIOF10)

(GPIOF11)

(GPIOF12)

(GPIOF13)

(GPIOF14)

(GPIOF15)

(GPIOF0)

Input/

Output

Input/

Output

Tri-stated

Input

Data Bus -- D7 - D14 specify part of the data for external
program or data memory accesses.

Port F GPIO -- These eight GPIO pins can be individually
programmed as input or output pins.

At reset, these pins default to data bus functionality.

To deactivate the internal pull-up resistor, clear the
appropriate GPIO bit in the GPIOF_PUR register.

Example: GPIOF0, clear bit 0 in the GPIOF_PUR register.

(GPIOF1)

(GPIOF2)

D10

(GPIOF3)

D11

(GPIOF4)

133

D12

(GPIOF5)

134

D13

(GPIOF6)

135

D14

(GPIOF7)

136

Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP

Signal Name

Pin No.

Type

State

During

Reset

Signal Description

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56F8346 Signal Pins

56F8346 Technical Data

Preliminary

D15

(GPIOF8)

137

Input/

Output

Input/

Output

Tri-stated

Input

Data Bus -- D15 specifies part of the data for external
program or data memory accesses.

Port F GPIO -- This GPIO pin can be individually
programmed as an input or output pin.

At reset, this pin defaults to the data bus function.

To deactivate the internal pull-up resistor, clear bit 8 in the
GPIOF_PUR register.

Output

Tri-stated

Read Enable -- RD is asserted during external memory
read cycles. When RD is asserted low, pins D0 - D15
become inputs and an external device is enabled onto the
data bus. When RD is deasserted high, the external data is
latched inside the device. When RD is asserted, it qualifies
the A0 - A16, PS, DS, and CSn

pins. RD can be connected

directly to the OE pin of a static RAM or ROM.

Depending upon the state of the DRV bit in the EMI bus
control register (BCR), RD is tri-stated when the external
bus is inactive.

To deactivate the internal pull-up resistor, set the CTRL bit
in the SIM_PUDR register.

Output

Tri-stated

Write Enable -- WR is asserted during external memory
write cycles. When WR is asserted low, pins D0 - D15
become outputs and the device puts data on the bus.
When WR is deasserted high, the external data is latched
inside the external device. When WR is asserted, it
qualifies the A0 - A16, PS, DS, and CSn pins. WR can be
connected directly to the WE pin of a static RAM.

Depending upon the state of the DRV bit in the EMI bus
control register (BCR), WR

is tri-stated when the external

bus is inactive.

To deactivate the internal pull-up resistor, set the CTRL bit
in the SIM_PUDR register.

Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP

Signal Name

Pin No.

Type

State

During

Reset

Signal Description

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56F8346 Technical Data

Preliminary

(CS0)

(GPIOD8)

Output

Input/

Output

Tri-stated

Input

Program Memory Select -- This signal is actually CS0 in
the EMI, which is programmed at reset for compatibility
with the 56F80x PS signal. PS is asserted low for external
program memory access.

Depending upon the state of the DRV bit in the EMI bus
control register (BCR),

PS is tri-stated when the external

bus is inactive.

Port D GPIO -- This GPIO pin can be individually
programmed as an input or output pin.

CS0 resets to provide the PS function as defined on the
56F80x devices.

To deactivate the internal pull-up resistor, clear bit 8 in the
GPIOD_PUR register.

(CS1)

(GPIOD9)

Output

Input/

Output

Tri-stated

Input

Data Memory Select -- This signal is actually CS1 in the
EMI, which is programmed at reset for compatibility with
the 56F80x DS signal. DS is asserted low for external data
memory access.

Depending upon the state of the DRV bit in the EMI bus
control register (BCR), DS is tri-stated when the external
bus is inactive.

Port D GPIO -- This GPIO pin can be individually
programmed as an input or output pin.

CS1 resets to provide the DS function as defined on the
56F80x devices.

To deactivate the internal pull-up resistor, clear bit 9 in the
GPIOD_PUR register.

GPIOD0

(CS2)

Input/

Output

Input

Tri-stated

Port D GPIO -- These two GPIO pins can be individually
programmed as input or output pins.

Chip Select -- CS2 - CS3 may be programmed within the
EMI module to act as chip selects for specific areas of the
external memory map.

Depending upon the state of the DRV bit in the EMI bus
control register (BCR), CS2 - CS3 are tri-stated when the
external bus is inactive.

At reset, these pins are configured as GPIO.

To deactivate the internal pull-up resistor, clear the
appropriate GPIO bit in the GPIOD_PUR register.

Example: GPIOD0, clear bit 0 in the GPIOD_PUR register.

GPIOD1

(CS3)

Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP

Signal Name

Pin No.

Type

State

During

Reset

Signal Description

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56F8346 Signal Pins

56F8346 Technical Data

Preliminary

TXD0

(GPIOE0)

Output

Input/

Output

Tri-stated

Input

Transmit Data -- SCI0 transmit data output

Port E GPIO -- This GPIO pin can be individually
programmed as an input or output pin.

After reset, the default state is SCI output.

To deactivate the internal pull-up resistor, clear bit 0 in the
GPIOE_PUR register.

RXD0

(GPIOE1)

Input

Input/

Output

Input

Receive Data -- SCI0 receive data input

Port E GPIO -- This GPIO pin can be individually
programmed as an input or output pin.

After reset, the default state is SCI output.

To deactivate the internal pull-up resistor, clear bit 1 in the
GPIOE_PUR register.

TXD1

(GPIOD6)

Output

Input/

Output

Tri-stated

Input

Transmit Data -- SCI1 transmit data output

Port D GPIO -- This GPIO pin can be individually
programmed as an input or output pin.

After reset, the default state is SCI output.

To deactivate the internal pull-up resistor, clear bit 6 in the
GPIOD_PUR register.

RXD1

(GPIOD7)

Input

Input/

Output

Input

Receive Data -- SCI1 receive data input

Port D GPIO -- This GPIO pin can be individually
programmed as an input or output pin.

After reset, the default state is SCI input.

To deactivate the internal pull-up resistor, clear bit 7 in the
GPIOD_PUR register.

TCK

121

Schmitt

Input

Input,

pulled low

internally

Test Clock Input -- This input pin provides a gated clock
to synchronize the test logic and shift serial data to the
JTAG/EOnCE port. The pin is connected internally to a
pull-down resistor.

TMS

122

Schmitt

Input

Input,

pulled high

internally

Test Mode Select Input -- This input pin is used to
sequence the JTAG TAP controller's state machine. It is
sampled on the rising edge of TCK and has an on-chip
pull-up resistor.

To deactivate the internal pull-up resistor, set the JTAG bit
in the SIM_PUDR register.

Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP

Signal Name

Pin No.

Type

State

During

Reset

Signal Description

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56F8346 Technical Data

Preliminary

TDI

123

Schmitt

Input

Input,

pulled high

internally

Test Data Input -- This input pin provides a serial input
data stream to the JTAG/EOnCE port. It is sampled on the
rising edge of TCK and has an on-chip pull-up resistor.

To deactivate the internal pull-up resistor, set the JTAG bit
in the SIM_PUDR register.

TDO

124

Output

Tri-stated

Test Data Output -- This tri-stateable output pin provides
a serial output data stream from the JTAG/EOnCE port. It
is driven in the shift-IR and shift-DR controller states, and
changes on the falling edge of TCK.

TRST

120

Schmitt

Input

Input,

pulled high

internally

Test Reset -- As an input, a low signal on this pin
provides a reset signal to the JTAG TAP controller. To
ensure complete hardware reset, TRST should be
asserted whenever RESET is asserted. The only
exception occurs in a debugging environment when a
hardware device reset is required and the JTAG/EOnCE
module must not be reset. In this case, assert RESET, but
do not assert TRST.

To deactivate the internal pull-up resistor, set the JTAG bit
in the SIM_PUDR register.

PHASEA0

(TA0)

(GPIOC4)

139

Schmitt

Input

Schmitt

Input/

Output

Schmitt

Input/

Output

Input

Phase A -- Quadrature Decoder 0, PHASEA input

TA0 -- Timer A, Channel 0

Port C GPIO -- This GPIO pin can be individually
programmed as an input or output pin.

After reset, the default state is PHASEA0.

To deactivate the internal pull-up resistor, clear bit 4 of the
GPIOC_PUR register.

PHASEB0

(TA1)

(GPIOC5)

140

Schmitt

Input

Schmitt

Input/

Output

Schmitt

Input/

Output

Input

Phase B -- Quadrature Decoder 0, PHASEB input

TA1 -- Timer A, Channel

Port C GPIO -- This GPIO pin can be individually
programmed as an input or output pin.

After reset, the default state is PHASEB0.

To deactivate the internal pull-up resistor, clear bit 5 of the
GPIOC_PUR register.

Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP

Signal Name

Pin No.

Type

State

During

Reset

Signal Description

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56F8346 Signal Pins

56F8346 Technical Data

Preliminary

INDEX0

(TA2)

(GPOPC6)

141

Schmitt

Input

Schmitt

Input/

Output

Schmitt

Input/

Output

Input

Index -- Quadrature Decoder 0, INDEX input

TA2 -- Timer A, Channel 2

Port C GPIO -- This GPIO pin can be individually
programmed as an input or output pin.

After reset, the default state is INDEX0.

To deactivate the internal pull-up resistor, clear bit 6 of the
GPIOC_PUR register.

HOME0

(TA3)

(GPIOC7)

142

Schmitt

Input

Schmitt

Input/

Output

Schmitt

Input/

Output

Input

Home -- Quadrature Decoder 0, HOME input

TA3 -- Timer A, Channel 3

Port C GPIO -- This GPIO pin can be individually
programmed as an input or output pin.

After reset, the default state is HOME0.

To deactivate the internal pull-up resistor, clear bit 7 of the
GPIOC_PUR register.

SCLK0

(GPIOE4)

130

Schmitt

Input/

Output

Schmitt

Input/

Output

Input

SPI 0 Serial Clock -- In the master mode, this pin serves
as an output, clocking slaved listeners. In slave mode, this
pin serves as the data clock input.

Port E GPIO -- This GPIO pin can be individually
programmed as an input or output pin.

After reset, the default state is SCLK0.

To deactivate the internal pull-up resistor, clear bit 4 in the
GPIOE_PUR register.

MOSI0

(GPIOE5)

132

Input/

Output

Input/

Output

Tri-stated

Input

SPI 0 Master Out/Slave In -- This serial data pin is an
output from a master device and an input to a slave device.
The master device places data on the MOSI line a
half-cycle before the clock edge the slave device uses to
latch the data.

Port E GPIO -- This GPIO pin can be individually
programmed as an input or output pin.

After reset, the default state is MOSI0.

To deactivate the internal pull-up resistor, clear bit 5 in the
GPIOE_PUR register.

Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP

Signal Name

Pin No.

Type

State

During

Reset

Signal Description

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56F8346 Technical Data

Preliminary

MISO0

(GPIOE6)

131

Input/

Output

Input/

Output

Input

SPI 0 Master In/Slave Out -- This serial data pin is an
input to a master device and an output from a slave device.
The MISO line of a slave device is placed in the
high-impedance state if the slave device is not selected.
The slave device places data on the MISO line a half-cycle
before the clock edge the master device uses to latch the
data.

Port E GPIO -- This GPIO pin can be individually
programmed as an input or output pin.

After reset, the default state is MISO0.

To deactivate the internal pull-up resistor, clear bit 6 in the
GPIOE_PUR register.

SS0

(GPIOE7)

129

Input

Input/

Output

Input

SPI 0 Slave Select -- SS0 is used in slave mode to
indicate to the SPI module that the current transfer is to be
received.

Port E GPIO -- This GPIO pin can be individually
programmed as input or output pin.

After reset, the default state is SS0.

To deactivate the internal pull-up resistor, clear bit 7 in the
GPIOE_PUR register.

PHASEA1

(TB0)

(SCLK1)

(GPIOC0)

Schmitt

Input

Schmitt

Input/

Output

Schmitt

Input/

Output

Schmitt

Input/

Output

Input

Phase A1 -- Quadrature Decoder, PHASEA input for
decoder 1.

TB0 -- Timer B, Channel 0

SPI 1 Serial Clock -- In the master mode, this pin serves
as an output, clocking slaved listeners. In slave mode, this
pin serves as the data clock input. To activate the SPI
function, set the PHSA_ALT bit in the SIM_GPS register.
For details, see

Section 6.5.8

Port C GPIO -- This GPIO pin can be individually
programmed as an input or output pin.

After reset, the default state is PHASEA1.

To deactivate the internal pull-up resistor, clear bit 0 in the
GPIOC_PUR register.

Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP

Signal Name

Pin No.

Type

State

During

Reset

Signal Description

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56F8346 Signal Pins

56F8346 Technical Data

Preliminary

PHASEB1

(TB1)

(MOSI1)

(GPIOC1)

Schmitt

Input

Schmitt

Input/

Output

Schmitt

Input/

Output

Schmitt

Input/

Output

Input

Tri-stated

Input

Phase B1 -- Quadrature Decoder 1, PHASEB input for
decoder 1.

TB1 -- Timer B, Channel 1

SPI 1 Master Out/Slave In -- This serial data pin is an
output from a master device and an input to a slave device.
The master device places data on the MOSI line a
half-cycle before the clock edge the slave device uses to
latch the data. To activate the SPI function, set the
PHSB_ALT bit in the SIM_GPS register. For details, see

Section 6.5.8

Port C GPIO -- This GPIO pin can be individually
programmed as an input or output pin.

After reset, the default state is PHASEB1.

To deactivate the internal pull-up resistor, clear bit 1 in the
GPIOC_PUR register.

INDEX1

(TB2)

(MISO1)

(GPIOC2)

Schmitt

Input

Schmitt

Input/

Output

Schmitt

Input/

Output

Schmitt

Input/

Output

Input

Index1 -- Quadrature Decoder 1, INDEX input

TB2 -- Timer B, Channel 2

SPI 1 Master In/Slave Out -- This serial data pin is an
input to a master device and an output from a slave device.
The MISO line of a slave device is placed in the
high-impedance state if the slave device is not selected.
The slave device places data on the MISO line a half-cycle
before the clock edge the master device uses to latch the
data. To activate the SPI function, set the INDEX_ALT bit
in the SIM_GPS register. For details, see

Section 6.5.8

Port C GPIO -- This GPIO pin can be individually
programmed as an input or output pin.

After reset, the default state is INDEX1.

To deactivate the internal pull-up resistor, clear bit 2 in the
GPIOC_PUR register.

Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP

Signal Name

Pin No.

Type

State

During

Reset

Signal Description

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56F8346 Technical Data

Preliminary

HOME1

(TB3)

(SS1)

(GPIOC3)

Schmitt

Input

Schmitt

Input/

Output

Schmitt

Input

Schmitt

Input/

Output

Input

Home -- Quadrature Decoder 1, HOME input

TB3 -- Timer B, Channel 3

SPI 1 Slave Select -- In the master mode, this pin is used
to arbitrate multiple masters. In slave mode, this pin is
used to select the slave. To activate the SPI function, set
the HOME_ALT bit in the SIM_GPS register. For details,
see

Section 6.5.8

Port C GPIO -- This GPIO pin can be individually
programmed as an input or output pin.

After reset, the default state is HOME1.

To deactivate the internal pull-up resistor, clear bit 3 in the
GPIOC_PUR register.

PWMA0

Output

Tri-State

PWMA0 - 5 -- These are six PWMA outputs.

PWMA1

PWMA2

PWMA3

PWMA4

PWMA5

ISA0

(GPIOC8)

113

Schmitt

Input

Schmitt

Input/

Output

Input

ISA0 - 2 -- These three input current status pins are used
for top/bottom pulse width correction in complementary
channel operation for PWMA.

Port C GPIO -- These three GPIO pins can be individually
programmed as input or output pins.

At reset, these pins default to ISA functionality.

To deactivate the internal pull-up resistor, clear the
appropriate bit of the GPIOC_PUR register. For details,
see

Section 6.5.8

ISA1

(GPIOC9)

114

ISA2

(GPIOC10)

115

FAULTA0

Schmitt

Input

FAULTA0 - 2 -- These three fault input pins are used for
disabling selected PWMA outputs in cases where fault
conditions originate off-chip.

To deactivate the internal pull-up resistor, set the PWMA0
bit in the SIM_PUDR register. For details, see

Section

6.5.8

FAULTtA1

FAULTA2

Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP

Signal Name

Pin No.

Type

State

During

Reset

Signal Description

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56F8346 Signal Pins

56F8346 Technical Data

Preliminary

PWMB0

Output

Tri-State

PWMB0 - 5 -- Six PWMB output pins.

PWMB1

PWMB2

PWMB3

PWMB4

PWMB5

ISB0

(GPIOD10)

Schmitt

Input

Schmitt

Input/

Output

Input

ISB0 - 2 -- These three input current status pins are used
for top/bottom pulse width correction in complementary
channel operation for PWMB.

Port D GPIO -- These three GPIO pins can be individually
programmed as input or output pins.

At reset, these pins default to ISB functionality.

To deactivate the internal pull-up resistor, clear the
appropriate bit of the GPIOD_PUR register. For details,
see

Section 6.5.8

ISB1

(GPIOD11)

ISB2

(GPIOD12)

FAULTB0

Schmitt

Input

FAULTB0 - 3 -- These four fault input pins are used for
disabling selected PWMB outputs in cases where fault
conditions originate off-chip.

To deactivate the internal pull-up resistor, set the PWMB
bit in the SIM_PUDR register. For details, see

Section

6.5.8

FAULTB1

FAULTB2

FAULTB3

ANA0

Input

ANA0 - 3 -- Analog inputs to ADC A, channel 0

ANA1

ANA2

ANA3

ANA4

Input

ANA4 - 7 -- Analog inputs to ADC A, channel 1

ANA5

ANA6

ANA7

REFH

101

Input

REFH

-- Analog Reference Voltage High. V

REFH

must be

less than or equal to

DDA_ADC.

REFP

100

Input/

Output

Input/

Output

REFP

, V

REFMID

& V

REFN

-- Internal pins for voltage

reference which are brought off-chip so they can be
bypassed. Connect to a 0.1

F low ESR capacitor.

REFMID

REFN

REFLO

Input

REFLO

-- Analog Reference Voltage Low. This should

normally be connected to a low-noise V

SSA

Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP

Signal Name

Pin No.

Type

State

During

Reset

Signal Description

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56F8346 Technical Data

Preliminary

ANB0

104

Input

ANB0 - 3 -- Analog inputs to ADC B, channel 0

ANB1

105

ANB2

106

ANB3

107

ANB4

108

Input

ANB4 - 7 -- Analog inputs to ADC B, channel 1

ANB5

109

ANB6

110

ANB7

111

TEMP_SENSE

Output

Temperature Sensor Diode -- This signal connects to an
on-chip diode that can be connected to one of the ADC
inputs and used to monitor the temperature of the die.
Must be bypassed with a 0.01

F capacitor.

CAN_RX

127

Schmitt

Input

FlexCAN Receive Data -- This is the CAN input. This pin
has an internal pull-up resistor.

To deactivate the internal pull-up resistor, set the CAN bit
in the SIM_PUDR register.

CAN_TX

126

Open
Drain

Output

Open
Drain

Output

FlexCAN Transmit Data -- CAN output

TC0

(GPIOE8)

118

Schmitt

Input/

Output

Schmitt

Input/

Output

Input

TC0 -- Timer C Channel 0

Port E GPIO -- This GPIO pin can be programmed as an
input or output pin.

At reset, this pin defaults to timer functionality.

To deactivate the internal pull-up resistor, clear bit 8 of the
GPIOE_PUR register.

TD0

(GPIOE10)

116

Schmitt

Input/

Output

Schmitt

Input/

Output

Input

TD0 -1 -- Timer D, Channels 0 and 1

Port E GPIO -- These GPIO pins can be individually
programmed as input or output pins.

At reset, these pins default to Timer functionality.

To deactivate the internal pull-up resistor, clear the
appropriate bit of the GPIOE_PUR register. See

Section

6.5.6

for details.

TD1

(GPIOE11)

117

Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP

Signal Name

Pin No.

Type

State

During

Reset

Signal Description

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56F8346 Signal Pins

56F8346 Technical Data

Preliminary

IRQA

Schmitt

Input

External Interrupt Request A and B -- The IRQA and
IRQB inputs are asynchronous external interrupt requests
during Stop and Wait mode operation. During other
operating modes, they are synchronized external interrupt
requests, which indicate an external device is requesting
service. They can be programmed to be level-sensitive or
negative-edge triggered.

To deactivate the internal pull-up resistor, set the IRQ bit in
the SIM_PUDR register. See

Section 6.5.6

for details.

IRQB

RESET

Schmitt

Input

Reset -- This input is a direct hardware reset on the
processor. When RESET is asserted low, the device is
initialized and placed in the reset state. A Schmitt trigger
input is used for noise immunity. When the RESET pin is
deasserted, the initial chip operating mode is latched from
the EXTBOOT pin. The internal reset signal will be
deasserted synchronous with the internal clocks after a
fixed number of internal clocks.

To ensure complete hardware reset, RESET and TRST
should be asserted together. The only exception occurs in
a debugging environment when a hardware device reset is
required and the JTAG/EOnCE module must not be reset.
In this case, assert RESET but do not assert TRST.

Note: The internal Power-On Reset will assert on initial
power-up.

To deactivate the internal pull-up resistor, set the RESET
bit in the SIM_PUDR register. See

Section 6.5.6

for

details.

RSTO

Output

Reset Output -- This output reflects the internal reset
state of the chip.

EXTBOOT

112

Schmitt

Input

External Boot -- This input is tied to V

to force the

device to boot from off-chip memory (assuming that the
on-chip Flash memory is not in a secure state). Otherwise,
it is tied to ground. For details, see

Table 4-4

Note: When this pin is tied low, the customer boot software
should disable the internal pull-up resistor by setting the
XBOOT bit of the SIM_PUDR; see

Section 6.5.6

Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP

Signal Name

Pin No.

Type

State

During

Reset

Signal Description

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Introduction

56F8346 Technical Data

Preliminary

Part 3 On-Chip Clock Synthesis (OCCS)

3.1 Introduction

Refer to the OCCS chapter of the 56F8300 Peripheral User Manual for a full description of the
OCCS. The material contained here identifies the specific features of the OCCS design that apply
to the 56F8346 part.

Figure 3-1

shows the specific OCCS block diagram to reference from the

OCCS chapter in the 56F8300 Peripheral User Manual.

Figure 3-1 OCCS Block Diagram

MUX

EXTAL

XTAL

EED

BAC

LCK

Prescaler CLK

Postscaler CLK

OUT/2

Crystal

OSC

Loss of

Reference

Clock

Detector

Lock

Detector

ZSRC

Bus Interface & Control

OUT

PLLDB

PLLCOD

PLLCID

Bus

Interface

Loss of Reference

Clock Interrupt

SYS_CLK2
Source to SIM

CLKMODE

Prescaler

(

1,2,4,8

)

Postscaler

(

1,2,4,8

)

TR_

PLL

x (1 to 128)

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56F8346 Technical Data

Preliminary

3.2 External Clock Operation

The 56F8346 system clock can be derived from an external crystal, ceramic resonator, or an
external system clock signal. To generate a reference frequency using the internal oscillator, a
reference crystal or ceramic resonator, must be connected between the EXTAL and XTAL pins.

3.2.1

Crystal Oscillator

The internal oscillator is designed to interface with a parallel-resonant crystal resonator in the
frequency range specified for the external crystal in

Table 10-15

. A recommended crystal

oscillator circuit is shown in

Figure 3-2

. Follow the crystal supplier's recommendations when

selecting a crystal, since crystal parameters determine the component values required to provide
maximum stability and reliable start-up. The crystal and associated components should be mounted
as near as possible to the EXTAL and XTAL pins to minimize output distortion and start-up
stabilization time.

Figure 3-2 Connecting to a Crystal Oscillator

Note:

The OCCS_COHL bit must be set to 1 when a crystal oscillator is used. The reset condition on
the OCCS_COHL bit is 0. Please see the COHL bit in the Oscillator Control (OSCTL)
register, discussed in the 56F8300 Peripheral User Manual.

Sample External Crystal Parameters:
R

= 750 K

Note: If the operating temperature range is limited to
below 85

(105

C junction), then R

= 10 Meg

CLKMODE = 0

EXTAL XTAL

CL1

CL2

Crystal Frequency = 4 - 8MHz (optimized for 8MHz)

EXTAL XTAL

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Registers

56F8346 Technical Data

Preliminary

3.2.2

Ceramic Resonator (Default)

It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall
system design can tolerate the reduced signal integrity. A typical ceramic resonator circuit is shown
in

Figure 3-3

. Refer to the supplier's recommendations when selecting a ceramic resonator and

associated components. The resonator and components should be mounted as near as possible to
the EXTAL and XTAL pins.

Figure 3-3 Connecting a Ceramic Resonator

Note:

The OCCS_COHL bit must be set to 0 when a ceramic resonator is used. The reset condition
on the OCCS_COHL bit is 0. Please see the COHL bit in the Oscillator Control (OSCTL)
register, discussed in the 56F8300 Peripheral User Manual.

3.2.3

External Clock Source

The recommended method of connecting an external clock is given in

Figure 3-4

. The external

clock source is connected to XTAL and the EXTAL pin is grounded. Set OCCS_COHL bit high
when using an external clock source as well.

Figure 3-4 Connecting an External Clock Register

3.3 Registers

When referring to the register definitions for the OCCS in the 56F8300 Peripheral User Manual,
use the register definitions without the internal Relaxation Oscillator, since the 56F8346 does
NOT contain this oscillator.

EXTAL

XTAL

Sample External Ceramic Resonator Parameters:
R

= 750 K

EXTAL

XTAL

CL1

CL2

Resonator Frequency = 4 - 8MHz (optimized for 8MHz)

3 Terminal

2 Terminal

CLKMODE = 0

56F8346

XTAL

EXTAL

External

Clock

Note: When using an external clocking source
with this configuration, the input "CLKMODE"
should be high and the COHL bit in the OSCTL
register should be set to 1.

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56F8346 Technical Data

Preliminary

Part 4 Memory Map

4.1 Introduction

The 56F8346 device is a 16-bit motor-control chip based on the 56800E core. It uses a
Harvard-style architecture with two independent memory spaces for Data and Program. On-chip
RAM and Flash memories are used in both spaces.

This section provides memory maps for:

Program Address Space, including the Interrupt Vector Table

Data Address Space, including the EOnCE Memory and Peripheral Memory Maps

On-chip memory sizes for each device are summarized in

Table 4-1

. Flash memories' restrictions

are identified in the "Use Restrictions" column of

Table 4-1

Table 4-1 Chip Memory Configurations

On-Chip Memory

56F8346

Use Restrictions

Program Flash

128KB

Erase / Program via Flash interface unit and word writes to CDBW

Data Flash

8KB

Erase / Program via Flash interface unit and word writes to CDBW. Data
Flash can be read via either CDBR or XDB2, but not by both simultaneously

Program RAM

4KB

None

Data RAM

8KB

None

Program Boot Flash

8KB

Erase / Program via Flash Interface unit and word to CDBW

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Program Map

56F8346 Technical Data

Preliminary

4.2 Program Map

The operating mode control bits (MA and MB) in the Operating Mode Register (OMR) control the
Program memory map. At reset, these bits are set as indicated in

Table 4-2

Table 4-4

shows the

memory map configurations that are possible at reset. After reset, the OMR MA bit can be changed
and will have an effect on the P-space memory map, as shown in

Table 4-3

. Changing the OMR

MB bit will have no effect.

The 56F8346's external memory interface (EMI) can operate much like the 56F80x family's EMI,
or it can be operated in a mode similar to that used on other products in the 56800E family. Initially,
CS0 and CS1 are configured as PS and DS, in a mode compatible with earlier 56800 devices.

Eighteen address lines are required to shadow the first 192K of internal program space when
booting externally for development purposes. Therefore, the entire complement of on-chip
memory cannot be accessed using a 16-bit 56800-compatible address bus. To address this
situation, the EMI_MODE pin can be used to configure four GPIO pins as Address[19:16] upon
reset (only one of these pins [A16] is usable in the 56F8346).

The EMI_MODE pin also affects the reset vector address, as provided in

Table 4-4

. Additional

pins must be configured as address or chip select signals to access addresses at P:$10 0000 and
above.

Table 4-2 OMR MB/MA Value at Reset

OMR MB =

Flash Secured

State

This bit is only configured at reset. If the Flash secured state changes, this will not be reflected in MB until the next reset.

Changing MB in software will not affect Flash memory security.

OMR MA =

EXTBOOT Pin

Chip Operating Mode

Mode 0 Internal Boot; EMI is configured to use 16 address lines; Flash
Memory is secured; external P-space is not allowed; the EOnCE is disabled

Not valid; cannot boot externally if the Flash is secured and will actually
configure to 00 state

Mode 0 Internal Boot; EMI is configured to use 16 address lines

Mode 1 External Boot; Flash Memory is not secured; EMI configuration is
determined by the state of the EMI_MODE pin

Table 4-3 Changing OMR MA Value During Normal Operation

OMR MA

Chip Operating Mode

Use internal P-space memory map configuration

Use external P-space memory map configuration If MB = 0 at reset, changing this bit has no
effect.

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56F8346 Technical Data

Preliminary

4.3 Interrupt Vector Table

Table 4-5

provides the reset and interrupt priority structure, including on-chip peripherals. The

table is organized with higher-priority vectors at the top and lower-priority interrupts lower in the
table. The priority of an interrupt can be assigned to different levels, as indicated, allowing some
control over interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For
a selected priority level, the lowest vector number has the highest priority.

The location of the vector table is determined by the Vector Base Address (VBA) register. Please
see

Section 5.6.12

for the reset value of the VBA.

In some configurations, the reset address and COP reset address will correspond to vector 0 and 1
of the interrupt vector table. In these instances, the first two locations in the vector table must
contain branch or JMP instructions. All other entries must contain JSR instructions.

Table 4-4 Program Memory Map at Reset

Begin/End

Address

Mode 0 (MA = 0)

Mode 1

(MA = 1)

If Flash Security Mode is enabled, EXTBOOT Mode 1 cannot be used. See Security Features,

Part 7

Internal Boot

External Boot

Internal Boot

16-Bit External Address Bus

EMI_MODE = 0

16-Bit External Address Bus

This mode provides maximum compatibility with 56F80x parts while operating externally.

"EMI_MODE =0" when EMI_MODE pin is tied to ground at boot up.

EMI_MODE = 1

20-Bit External Address Bus

"EMI_MODE =1" when EMI_MODE pin is tied to V

at boot up.

P:$1F FFFF
P:$10 0000

External Program Memory

Not accessible in reset configuration, since the address is above P:$00 FFFF. The higher bit address/GPIO (and/or chip

selects) pins must be reconfigured before this external memory is accessible.

External Program Memory

P:$0F FFFF
P:$03 0000

External Program RAM

COP Reset Address = 02 0002

Boot Location = 02 0000

Booting from this external address allows prototyping of the internal Boot Flash.

P:$02 FFFF
P:$02 F800

On-Chip Program RAM

4KB

P:$02 F7FF
P:$02 1000

Reserved

116KB

P:$02 0FFF
P:$02 0000

Boot Flash
8KB
COP Reset Address = 02 0002
Boot Location = 02 0000

Boot Flash
8KB
(Not Used for Boot in this Mode)

P:$01 FFFF
P:$01 0000

External Program RAM

Internal Program Flash

128KB

The internal Program Flash is relocated in this mode making it accessible.

P:$00 FFFF
P:$00 0000

Internal Program Flash
128KB

External Program RAM
COP Reset Address = 00 0002
Boot Location = 00 0000

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Interrupt Vector Table

56F8346 Technical Data

Preliminary

Table 4-5 Interrupt Vector Table Contents

Peripheral

Vector

Number

Priority

Level

Vector Base

Address +

Interrupt Function

Reserved for Reset Overlay

Reserved for COP Reset Overlay

core

P:$04

Illegal Instruction

core

P:$06

SW Interrupt 3

core

P:$08

HW Stack Overflow

core

P:$0A

Misaligned Long Word Access

core

1-3

P:$0C

OnCE Step Counter

core

1-3

P:$0E

OnCE Breakpoint Unit 0

Reserved

core

1-3

P:$12

OnCE Trace Buffer

core

1-3

P:$14

OnCE Transmit Register Empty

core

1-3

P:$16

OnCE Receive Register Full

Reserved

core

P:$1C

SW Interrupt 2

core

P:$1E

SW Interrupt 1

core

P:$20

SW Interrupt 0

core

0-2

P:$22

IRQA

core

0-2

P:$24

IRQB

Reserved

LVI

0-2

P:$28

Low Voltage Detector (power sense)

PLL

0-2

P:$2A

PLL

0-2

P:$2C

FM Access Error Interrupt

0-2

P:$2E

FM Command Complete

0-2

P:$30

FM Command, data and address Buffers Empty

Reserved

FLEXCAN

0-2

P:$34

FLEXCAN Bus Off

FLEXCAN

0-2

P:$36

FLEXCAN Error

FLEXCAN

0-2

P:$38

FLEXCAN Wake Up

FLEXCAN

0-2

P:$3A

FLEXCAN Message Buffer Interrupt

GPIOF

0-2

P:$3C

GPIO F

GPIOE

0-2

P:$3E

GPIO E

GPIOD

0-2

P:$40

GPIO D

GPIOC

0-2

P:$42

GPIO C

GPIOB

0-2

P:$44

GPIO B

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56F8346 Technical Data

Preliminary

GPIOA

0-2

P:$46

GPIO A

Reserved

SPI1

0-2

P:$4C

SPI 1 Receiver Full

SPI1

0-2

P:$4E

SPI 1 Transmitter Empty

SPI0

0-2

P:$50

SPI 0 Receiver Full

SPI0

0-2

P:$52

SPI 0 Transmitter Empty

SCI1

0-2

P:$54

SCI 1 Transmitter Empty

SCI1

0-2

P:$56

SCI 1 Transmitter Idle

Reserved

SCI1

0-2

P:$5A

SCI 1 Receiver Error

SCI1

0-2

P:$5C

SCI 1 Receiver Full

DEC1

0-2

P:$5E

Quadrature Decoder #1 Home Switch or Watchdog

DEC1

0-2

P:$60

Quadrature Decoder #1 INDEX Pulse

DEC0

0-2

P:$62

Quadrature Decoder #0 Home Switch or Watchdog

DEC0

0-2

P:$64

Quadrature Decoder #0 INDEX Pulse

Reserved

TMRD

0-2

P:$68

Timer D, Channel 0

TMRD

0-2

P:$6A

Timer D, Channel 1

TMRD

0-2

P:$6C

Timer D, Channel 2

TMRD

0-2

P:$6E

Timer D, Channel 3

TMRC

0-2

P:$70

Timer C, Channel 0

TMRC

0-2

P:$72

Timer C, Channel 1

TMRC

0-2

P:$74

Timer C, Channel 2

TMRC

0-2

P:$76

Timer C, Channel 3

TMRB

0-2

P:$78

Timer B, Channel 0

TMRB

0-2

P:$7A

Timer B, Channel 1

TMRB

0-2

P:$7C

Timer B, Channel 2

TMRB

0-2

P:$7E

Timer B, Channel 3

TMRA

0-2

P:$80

Timer A, Channel 0

TMRA

0-2

P:$82

Timer A, Channel 1

TMRA

0-2

P:$84

Timer A, Channel 2

TMRA

0-2

P:$86

Timer A, Channel 3

SCI0

0-2

P:$88

SCI 0 Transmitter Empty

SCI0

0-2

P:$8A

SCI 0 Transmitter Idle

Table 4-5 Interrupt Vector Table Contents

(Continued)

Peripheral

Vector

Number

Priority

Level

Vector Base

Address +

Interrupt Function

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Data Map

56F8346 Technical Data

Preliminary

4.4 Data Map

Reserved

SCI0

0-2

P:$8E

SCI 0 Receiver Error

SCI0

0-2

P:$90

SCI 0 Receiver Full

ADCB

0-2

P:$92

ADC B Conversion Compete

ADCA

0-2

P:$94

ADC A Conversion Complete

ADCB

0-2

P:$96

ADC B Zero Crossing of Limit Error

ADCA

0-2

P:$98

ADC A Zero Crossing of Limit Error

PWMB

0-2

P:$9A

Reload PWM B

PWMA

0-2

P:$9C

Reload PWM A

PWMB

0-2

P:$9E

PWM B Fault

PWMA

0-2

P:$A0

PWM A Fault

core

- 1

P:$A2

SW Interrupt LP

Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced

from the vector table, providing only 19 bits of address.

2. If the VBA is set to 0200 (or VBA = 0000 for Mode 1, EMI_MODE = 0), the first two locations of the vector table are the chip
reset addresses; therefore, these locations are not interrupt vectors.

Table 4-6 Data Memory Map

All addresses are 16-bit Word addresses, not byte addresses.

Begin/End

Address

EX = 0

In the Operation Mode Register (OMR).

EX = 1

X:$FF FFFF
X:$FF FF00

EOnCE
256 locations allocated

X:$FF FEFF
X:$01 0000

External Memory

X:$00 FFFF
X:$00 F000

On-Chip Peripherals
4096 locations allocated

X:$00 EFFF
X:$00 2000

External Memory

X:$00 1FFF
X:$00 1000

On-Chip Data Flash
8KB

X:$00 0FFF
X:$00 0000

On-Chip Data RAM

8KB

The Data RAM is organized as a 2K x 32-bit memory to allow single-cycle long-word operations.

Table 4-5 Interrupt Vector Table Contents

(Continued)

Peripheral

Vector

Number

Priority

Level

Vector Base

Address +

Interrupt Function

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56F8346 Technical Data

Preliminary

4.5 Flash Memory Map

Figure 4-1

illustrates the Flash Memory (FM) map on the system bus.

The Flash Memory is divided into three functional blocks. The Program and boot memories reside
on the Program Memory buses. They are controlled by one set of banked registers. Data Memory
Flash resides on the Data Memory buses and is controlled separately by own set of banked
registers.

The top nine words of the Program Memory Flash are treated as special memory locations. The
content of these words is used to control the operation of the Flash Controller. Because these words
are part of the Flash Memory content, their state is maintained during power-down and reset.
During chip initialization, the content of these memory locations is loaded into Flash Memory
control registers, detailed in the Flash Memory chapter of the 56F8300 Peripheral User Manual.
In the 56F8346, these configuration parameters are located between $00_FFF7 and $00_FFFF.

Figure 4-1 Flash Array Memory Maps

Table 4-7

shows the page and sector sizes used within each Flash memory block on the chip.

Please see 56F8300 Peripheral User Manual for additional Flash information.

Table 4-7. Flash Memory Partitions

Flash Size

Sectors

Sector Size

Page Size

Program Flash

128KB

4K x 16 bits

512 x 16 bits

Data Flash

8KB

256 x 16 bits

Boot Flash

8KB

1K x 16 bits

256 x 16 bits

BOOT_FLASH_START = $02_0000

BOOT_FLASH_START + $1FFF

Block 0 Odd

Block 0 Even

PROG_FLASH_START + $00_FFFF

8KB

Boot

Reserved

Configure Field

PROG_FLASH_START + $00_FFF7
PROG_FLASH_START + $00_FFF6

128K Bytes

PROG_FLASH_START = $00_0000

FM_PROG_MEM_TOP = $00_FFFF

BLOCK 0 Odd (2 Bytes) $00_0003
BLOCK 0 Even (2 Bytes) $00_0002
BLOCK 0 Odd (2 Bytes) $00_0001
BLOCK 0 Even (2 Bytes) $00_0000

FM_BASE + $14

Banked Registers

Unbanked Registers

8KB

FM_BASE + $00

DATA_FLASH_START + $0FFF

DATA_FLASH_START + $0000

Data Memory

Program Memory

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EOnCE Memory Map

56F8346 Technical Data

Preliminary

4.6 EOnCE Memory Map

4.7 Peripheral Memory Mapped Registers

On-chip peripheral registers are part of the data memory map on the 56800E series. These locations
may be accessed with the same addressing modes used for ordinary data memory, except all
peripheral registers should be read/written using word accesses only.

Table 4-8 EOnCE Memory Map

Address

Register Acronym

Register Name

Reserved

X:$FF FF8A

OESCR

External Signal Control Register

Reserved

X:$FF FF8E

OBCNTR

Breakpoint Unit [0] Counter

Reserved

X:$FF FF90

OBMSK (32 bits)

Breakpoint 1 Unit [0] Mask Register

X:$FF FF91

Breakpoint 1 Unit [0] Mask Register

X:$FF FF92

OBAR2 (32 bits)

Breakpoint 2 Unit [0] Address Register

X:$FF FF93

Breakpoint 2 Unit [0] Address Register

X:$FF FF94

OBAR1 (24 bits)

Breakpoint 1 Unit [0] Address Register

X:$FF FF95

Breakpoint 1 Unit [0] Address Register

X:$FF FF96

OBCR (24 bits)

Breakpoint Unit [0] Control Register

X:$FF FF97

Breakpoint Unit [0] Control Register

X:$FF FF98

OTB (21-24 bits/stage)

Trace Buffer Register Stages

X:$FF FF99

Trace Buffer Register Stages

X:$FF FF9A

OTBPR (8 bits)

Trace Buffer Pointer Register

X:$FF FF9B

OTBCR

Trace Buffer Control Register

X:$FF FF9C

OBASE (8 bits)

Peripheral Base Address Register

X:$FF FF9D

OSR

Status Register

X:$FF FF9E

OSCNTR (24 bits)

Instruction Step Counter

X:$FF FF9F

Instruction Step Counter

X:$FF FFA0

OCR (bits)

Control Register

Reserved

X:$FF FFFC

OCLSR (8 bits)

Core Lock / Unlock Status Register

X:$FF FFFD

OTXRXSR (8 bits)

Transmit and Receive Status and Control Register

X:$FF FFFE

OTX / ORX (32 bits)

Transmit Register / Receive Register

X:$FF FFFF

OTX1 / ORX1

Transmit Register Upper Word
Receive Register Upper Word

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56F8346 Technical Data

Preliminary

Table 4-9

summarizes base addresses for the set of peripherals on the 56F8346 device. Peripherals

are listed in order of the base address.

The following tables list all of the peripheral registers required to control or access the peripherals.

Table 4-9 Data Memory Peripheral Base Address Map Summary

Peripheral

Prefix

Base Address

Table Number

External Memory Interface

EMI

X:$00 F020

4-10

Timer A

TMRA

X:$00 F040

4-11

Timer B

TMRB

X:$00 F080

4-12

Timer C

TMRC

X:$00 F0C0

4-13

Timer D

TMRD

X:$00 F100

4-14

PWM A

PWMA

X:$00 F140

4-15

PWM B

PWMB

X:$00 F160

4-16

Quadrature Decoder 0

DEC0

X:$00 F180

4-17

Quadrature Decoder 1

DEC1

X:$00 F190

4-18

ITCN

X:$00 F1A0

4-19

ADC A

ADCA

X:$00 F200

4-20

ADC B

ADCB

X:$00 F240

4-21

Temperature Sensor

TSENSOR

X:$00 F270

4-22

SCI #0

SCI0

X:$00 F280

4-23

SCI #1

SCI1

X:$00 F290

4-24

SPI #0

SPI0

X:$00 F2A0

4-25

SPI #1

SPI1

X:$00 F2B0

4-26

COP

X:$00 F2C0

4-27

PLL, OSC

CLKGEN

X:$00 F2D0

4-28

GPIO Port A

GPIOA

X:$00 F2E0

4-29

GPIO Port B

GPIOB

X:$00 F300

4-30

GPIO Port C

GPIOC

X:$00 F310

4-31

GPIO Port D

GPIOD

X:$00 F320

4-32

GPIO Port E

GPIOE

X:$00 F330

4-33

GPIO Port F

GPIOF

X:$00 F340

4-34

SIM

X:$00 F350

4-35

Power Supervisor

LVI

X:$00 F360

4-36

X:$00 F400

4-37

FlexCAN

X:$00 F800

4-38

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Peripheral Memory Mapped Registers

56F8346 Technical Data

Preliminary

Table 4-10 External Memory Integration Registers Address Map

(EMI_BASE = $00 F020)

Register Acronym

Address Offset

Register Description

Reset Value

CSBAR 0

Chip Select Base Address Register 0

CSBAR 1

Chip Select Base Address Register 1

CSBAR 2

Chip Select Base Address Register 2

CSBAR 3

Chip Select Base Address Register 3

CSBAR 4

Chip Select Base Address Register 4

CSBAR 5

Chip Select Base Address Register 5

CSBAR 6

Chip Select Base Address Register 6

CSBAR 7

Chip Select Base Address Register 7

CSOR 0

Chip Select Option Register 0

0x5FCB programmed for
chip select for program
space, word wide, read and
write, 11 waits

CSOR 1

Chip Select Option Register 1

0x5FAB programmed for
chip select for data space,
word wide, read and write,
11 waits

CSOR 2

Chip Select Option Register 2

CSOR 3

Chip Select Option Register 3

CSOR 4

Chip Select Option Register 4

CSOR 5

Chip Select Option Register 5

CSOR 6

Chip Select Option Register 6

CSOR 7

Chip Select Option Register 7

CSTC 0

$10

Chip Select Timing Control Register 0

CSTC 1

$11

Chip Select Timing Control Register 1

CSTC 2

$12

Chip Select Timing Control Register 2

CSTC 3

$13

Chip Select Timing Control Register 3

CSTC 4

$14

Chip Select Timing Control Register 4

CSTC 5

$15

Chip Select Timing Control Register 5

CSTC 6

$16

Chip Select Timing Control Register 6

CSTC 7

$17

Chip Select Timing Control Register 7

BCR

$18

Bus Control Register

0x016B sets the default
number of wait states to 11
for both read and write
accesses

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56F8346 Technical Data

Preliminary

Table 4-11 Quad Timer A Registers Address Map

(TMRA_BASE = $00 F040)

Register Acronym

Address Offset

Register Description

TMRA0_CMP1

Compare Register 1

TMRA0_CMP2

Compare Register 2

TMRA0_CAP

Capture Register

TMRA0_LOAD

Load Register

TMRA0_HOLD

Hold Register

TMRA0_CNTR

Counter Register

TMRA0_CTRL

Control Register

TMRA0_SCR

Status and Control Register

TMRA0_CMPLD1

Comparator Load Register 1

TMRA0_CMPLD2

Comparator Load Register 2

TMRA0_COMSCR

Comparator Status and Control Register

Reserve

TMRA1_CMP1

$10

Compare Register 1

TMRA1_CMP2

$11

Compare Register 2

TMRA1_CAP

$12

Capture Register

TMRA1_LOAD

$13

Load Register

TMRA1_HOLD

$14

Hold Register

TMRA1_CNTR

$15

Counter Register

TMRA1_CTRL

$16

Control Register

TMRA1_SCR

$17

Status and Control Register

TMRA1_CMPLD1

$18

Comparator Load Register 1

TMRA1_CMPLD2

$19

Comparator Load Register 2

TMRA1_COMSCR

$1A

Comparator Status and Control Register

Reserved

TMRA2_CMP1

$20

Compare Register 1

TMRA2_CMP2

$21

Compare Register 2

TMRA2_CAP

$22

Capture Register

TMRA2_LOAD

$23

Load Register

TMRA2_HOLD

$24

Hold Register

TMRA2_CNTR

$25

Counter Register

TMRA2_CTRL

$26

Control Register

TMRA2_SCR

$27

Status and Control Register

TMRA2_CMPLD1

$28

Comparator Load Register 1

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Peripheral Memory Mapped Registers

56F8346 Technical Data

Preliminary

TMRA2_CMPLD2

$29

Comparator Load Register 2

TMRA2_COMSCR

$2A

Comparator Status and Control Register

Reserved

TMRA3_CMP1

$30

Compare Register 1

TMRA3_CMP2

$31

Compare Register 2

TMRA3_CAP

$32

Capture Register

TMRA3_LOAD

$33

Load Register

TMRA3_HOLD

$34

Hold Register

TMRA3_CNTR

$35

Counter Register

TMRA3_CTRL

$36

Control Register

TMRA3_SCR

$37

Status and Control Register

TMRA3_CMPLD1

$38

Comparator Load Register 1

TMRA3_CMPLD2

$39

Comparator Load Register 2

TMRA3_COMSC

$3A

Comparator Status and Control Register

Table 4-12 Quad Timer B Registers Address Map

(TMRB_BASE = $00 F080)

Register Acronym

Address Offset

Register Description

TMRB0_CMP1

Compare Register 1

TMRB0_CMP2

Compare Register 2

TMRB0_CAP

Capture Register

TMRB0_LOAD

Load Register

TMRB0_HOLD

Hold Register

TMRB0_CNTR

Counter Register

TMRB0_CTRL

Control Register

TMRB0_SCR

Status and Control Register

TMRB0_CMPLD1

Comparator Load Register 1

TMRB0_CMPLD2

Comparator Load Register 2

TMRB0_COMSCR

Comparator Status and Control Register

Reserved

TMRB1_CMP1

$10

Compare Register 1

TMRB1_CMP2

$11

Compare Register 2

TMRB1_CAP

$12

Capture Register

TMRB1_LOAD

$13

Load Register

Table 4-11 Quad Timer A Registers Address Map

(TMRA_BASE = $00 F040) (Continued)

Register Acronym

Address Offset

Register Description

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56F8346 Technical Data

Preliminary

TMRB1_HOLD

$14

Hold Register

TMRB1_CNTR

$15

Counter Register

TMRB1_CTRL

$16

Control Register

TMRB1_SCR

$17

Status and Control Register

TMRB1_CMPLD1

$18

Comparator Load Register 1

TMRB1_CMPLD2

$19

Comparator Load Register 2

TMRB1_COMSCR

$1A

Comparator Status and Control Register

Reserved

TMRB2_CMP1

$20

Compare Register 1

TMRB2_CMP2

$21

Compare Register 2

TMRB2_CAP

$22

Capture Register

TMRB2_LOAD

$23

Load Register

TMRB2_HOLD

$24

Hold Register

TMRB2_CNTR

$25

Counter Register

TMRB2_CTRL

$26

Control Register

TMRB2_SCR

$27

Status and Control Register

TMRB2_CMPLD1

$28

Comparator Load Register 1

TMRB2_CMPLD2

$29

Comparator Load Register 2

TMRB2_COMSCR

$2A

Comparator Status and Control Register

Reserved

TMRB3_CMP1

$30

Compare Register 1

TMRB3_CMP2

$31

Compare Register 2

TMRB3_CAP

$32

Capture Register

TMRB3_LOAD

$33

Load Register

TMRB3_HOLD

$34

Hold Register

TMRB3_CNTR

$35

Counter Register

TMRB3_CTRL

$36

Control Register

TMRB3_SCR

$37

Status and Control Register

TMRB3_CMPLD1

$38

Comparator Load Register 1

TMRB3_CMPLD2

$39

Comparator Load Register 2

TMRB3_COMSCR

$3A

Comparator Status and Control Register

Table 4-12 Quad Timer B Registers Address Map

(TMRB_BASE = $00 F080) (Continued)

Register Acronym

Address Offset

Register Description

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Peripheral Memory Mapped Registers

56F8346 Technical Data

Preliminary

Table 4-13 Quad Timer C Registers Address Map

(TMRC_BASE = $00 F0C0)

Register Acronym

Address Offset

Register Description

TMRC0_CMP1

Compare Register 1

TMRC0_CMP2

Compare Register 2

TMRC0_CAP

Capture Register

TMRC0_LOAD

Load Register

TMRC0_HOLD

Hold Register

TMRC0_CNTR

Counter Register

TMRC0_CTRL

Control Register

TMRC0_SCR

Status and Control Register

TMRC0_CMPLD1

Comparator Load Register 1

TMRC0_CMPLD2

Comparator Load Register 2

TMRC0_COMSCR

Comparator Status and Control Register

Reserved

TMRC1_CMP1

$10

Compare Register 1

TMRC1_CMP2

$11

Compare Register 2

TMRC1_CAP

$12

Capture Register

TMRC1_LOAD

$13

Load Register

TMRC1_HOLD

$14

Hold Register

TMRC1_CNTR

$15

Counter Register

TMRC1_CTRL

$16

Control Register

TMRC1_SCR

$17

Status and Control Register

TMRC1_CMPLD1

$18

Comparator Load Register 1

TMRC1_CMPLD2

$19

Comparator Load Register 2

TMRC1_COMSCR

$1A

Comparator Status and Control Register

Reserved

TMRC2_CMP1

$20

Compare Register 1

TMRC2_CMP2

$21

Compare Register 2

TMRC2_CAP

$22

Capture Register

TMRC2_LOAD

$23

Load Register

TMRC2_HOLD

$24

Hold Register

TMRC2_CNTR

$25

Counter Register

TMRC2_CTRL

$26

Control Register

TMRC2_SCR

$27

Status and Control Register

TMRC2_CMPLD1

$28

Comparator Load Register 1

TMRC2_CMPLD2

$29

Comparator Load Register 2

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56F8346 Technical Data

Preliminary

TMRC2_COMSCR

$2A

Comparator Status and Control Register

Reserved

TMRC3_CMP1

$30

Compare Register 1

TMRC3_CMP2

$31

Compare Register 2

TMRC3_CAP

$32

Capture Register

TMRC3_LOAD

$33

Load Register

TMRC3_HOLD

$34

Hold Register

TMRC3_CNTR

$35

Counter Register

TMRC3_CTRL

$36

Control Register

TMRC3_SCR

$37

Status and Control Register

TMRC3_CMPLD1

$38

Comparator Load Register 1

TMRC3_CMPLD2

$39

Comparator Load Register 2

TMRC3_COMSCR

$3A

Comparator Status and Control Register

Table 4-14 Quad Timer D Registers Address Map

(TMRD_BASE = $00 F100)

Register Acronym

Address Offset

Register Description

TMRD0_CMP1

Compare Register 1

TMRD0_CMP2

Compare Register 2

TMRD0_CAP

Capture Register

TMRD0_LOAD

Load Register

TMRD0_HOLD

Hold Register

TMRD0_CNTR

Counter Register

TMRD0_CTRL

Control Register

TMRD0_SCR

Status and Control Register

TMRD0_CMPLD1

Comparator Load Register 1

TMRD0_CMPLD2

Comparator Load Register 2

TMRD0_COMSCR

Comparator Status and Control Register

Reserved

TMRD1_CMP1

$10

Compare Register 1

TMRD1_CMP2

$11

Compare Register 2

TMRD1_CAP

$12

Capture Register

TMRD1_LOAD

$13

Load Register

TMRD1_HOLD

$14

Hold Register

Table 4-13 Quad Timer C Registers Address Map

(TMRC_BASE = $00 F0C0) (Continued)

Register Acronym

Address Offset

Register Description

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Peripheral Memory Mapped Registers

56F8346 Technical Data

Preliminary

TMRD1_CNTR

$15

Counter Register

TMRD1_CTRL

$16

Control Register

TMRD1_SCR

$17

Status and Control Register

TMRD1_CMPLD1

$18

Comparator Load Register 1

TMRD1_CMPLD2

$19

Comparator Load Register 2

TMRD1_COMSCR

$1A

Comparator Status and Control Register

Reserved

TMRD2_CMP1

$20

Compare Register 1

TMRD2_CMP2

$21

Compare Register 2

TMRD2_CAP

$22

Capture Register

TMRD2_LOAD

$23

Load Register

TMRD2_HOLD

$24

Hold Register

TMRD2_CNTR

$25

Counter Register

TMRD2_CTRL

$26

Control Register

TMRD2_SCR

$27

Status and Control Register

TMRD2_CMPLD1

$28

Comparator Load Register 1

TMRD2_CMPLD2

$29

Comparator Load Register 2

TMRD2_COMSCR

$2A

Comparator Status and Control Register

Reserved

TMRD3_CMP1

$30

Compare Register 1

TMRD3_CMP2

$31

Compare Register 2

TMRD3_CAP

$32

Capture Register

TMRD3_LOAD

$33

Load Register

TMRD3_HOLD

$34

Hold Register

TMRD3_CNTR

$35

Counter Register

TMRD3_CTRL

$36

Control Register

TMRD3_SCR

$37

Status and Control Register

TMRD3_CMPLD1

$38

Comparator Load Register 1

TMRD3_CMPLD2

$39

Comparator Load Register 2

TMRD3_COMSCR

$3A

Comparator Status and Control Register

Table 4-14 Quad Timer D Registers Address Map

(TMRD_BASE = $00 F100) (Continued)

Register Acronym

Address Offset

Register Description

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56F8346 Technical Data

Preliminary

Table 4-15 Pulse Width Modulator A Registers Address Map

(PWMA_BASE = $00 F140)

Register Acronym

Address Offset

Register Description

PWMA_PMCTL

Control Register

PWMA_PMFCTL

Fault Control Register

PWMA_PMFSA

Fault Status Acknowledge Register

PWMA_PMOUT

Output Control Register

PWMA_PMCNT

Counter Register

PWMA_PWMCM

Counter Modulo Register

PWMA_PWMVAL0

Value Register 0

PWMA_PWMVAL1

Value Register 1

PWMA_PWMVAL2

Value Register 2

PWMA_PWMVAL3

Value Register 3

PWMA_PWMVAL4

Value Register 4

PWMA_PWMVAL5

Value Register 5

PWMA_PMDEADTM

Dead Time Register

PWMA_PMDISMAP1

Disable Mapping Register 1

PWMA_PMDISMAP2

Disable Mapping Register 2

PWMA_PMCFG

Configure Register

PWMA_PMCCR

$10

Channel Control Register

PWMA_PMPORT

$11

Port Register

PWMA_PMICCR

$12

PWM Internal Correction Control Register

Table 4-16 Pulse Width Modulator B Registers Address Map

(PWMB_BASE = $00 F160)

Register Acronym

Address Offset

Register Description

PWMB_PMCTL

Control Register

PWMB_PMFCTL

Fault Control Register

PWMB_PMFSA

Fault Status Acknowledge Register

PWMB_PMOUT

Output Control Register

PWMB_PMCNT

Counter Register

PWMB_PWMCM

Counter Modulo Register

PWMB_PWMVAL0

Value Register 0

PWMB_PWMVAL1

Value Register 1

PWMB_PWMVAL2

Value Register 2

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Peripheral Memory Mapped Registers

56F8346 Technical Data

Preliminary

PWMB_PWMVAL3

Value Register 3

PWMB_PWMVAL4

Value Register 4

PWMB_PWMVAL5

Value Register 5

PWMB_PMDEADTM

Dead Time Register

PWMB_PMDISMAP1

Disable Mapping Register 1

PWMB_PMDISMAP2

Disable Mapping Register 2

PWMB_PMCFG

Configure Register

PWMB_PMCCR

$10

Channel Control Register

PWMB_PMPORT

$11

Port Register

PWMB_PMICCR

$12

PWM Internal Correction Control Register

Table 4-17 Quadrature Decoder 0 Registers Address Map

(DEC0_BASE = $00 F180)

Register Acronym

Address Offset

Register Description

DEC0_DECCR

Decoder Control Register

DEC0_FIR

Filter Interval Register

DEC0_WTR

Watchdog Time-out Register

DEC0_POSD

Position Difference Counter Register

DEC0_POSDH

Position Difference Counter Hold Register

DEC0_REV

Revolution Counter Register

DEC0_REVH

Revolution Hold Register

DEC0_UPOS

Upper Position Counter Register

DEC0_LPOS

Lower Position Counter Register

DEC0_UPOSH

Upper Position Hold Register

DEC0_LPOSH

Lower Position Hold Register

DEC0_UIR

Upper Initialization Register

DEC0_LIR

Lower Initialization Register

DEC0_IMR

Input Monitor Register

Table 4-16 Pulse Width Modulator B Registers Address Map

(PWMB_BASE = $00 F160) (Continued)

Register Acronym

Address Offset

Register Description

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56F8346 Technical Data

Preliminary

Table 4-18 Quadrature Decoder 1 Registers Address Map

(DEC1_BASE = $00 F190)

Register Acronym

Address Offset

Register Description

DEC1_DECCR

Decoder Control Register

DEC1_FIR

Filter Interval Register

DEC1_WTR

Watchdog Time-out Register

DEC1_POSD

Position Difference Counter Register

DEC1_POSDH

Position Difference Counter Hold Register

DEC1_REV

Revolution Counter Register

DEC1_REVH

Revolution Hold Register

DEC1_UPOS

Upper Position Counter Register

DEC1_LPOS

Lower Position Counter Register

DEC1_UPOSH

Upper Position Hold Register

DEC1_LPOSH

Lower Position Hold Register

DEC1_UIR

Upper Initialization Register

DEC1_LIR

Lower Initialization Register

DEC1_IMR

Input Monitor Register

Table 4-19 Interrupt Control Registers Address Map

(ITCN_BASE = $00 F1A0)

Register Acronym

Address Offset

Register Description

IPR 0

Interrupt Priority Register 0

IPR 1

Interrupt Priority Register 1

IPR 2

Interrupt Priority Register 2

IPR 3

Interrupt Priority Register 3

IPR 4

Interrupt Priority Register 4

IPR 5

Interrupt Priority Register 5

IPR 6

Interrupt Priority Register 6

IPR 7

Interrupt Priority Register 7

IPR 8

Interrupt Priority Register 8

IPR 9

Interrupt Priority Register 9

VBA

Vector Base Address Register

FIM0

Fast Interrupt Match Register 0

FIVAL0

Fast Interrupt Vector Address Low 0 Register

FIVAH0

Fast Interrupt Vector Address High 0 Register

FIM1

Fast Interrupt Match Register 1

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Peripheral Memory Mapped Registers

56F8346 Technical Data

Preliminary

FIVAL1

Fast Interrupt Vector Address Low 1 Register

FIVAH1

$10

Fast Interrupt Vector Address High 1 Register

IRQP 0

$11

IRQ Pending Register 0

IRQP 1

$12

IRQ Pending Register 1

IRQP 2

$13

IRQ Pending Register 2

IRQP 3

$14

IRQ Pending Register 3

IRQP 4

$15

IRQ Pending Register 4

IRQP 5

$16

IRQ Pending Register 5

$17

Reserved

ICTL

$1D

Interrupt Control Register

Table 4-20 Analog-to-Digital Converter Registers Address Map

(ADCA_BASE = $00 F200)

Register Acronym

Address Offset

Register Description

ADCA_CR 1

Control Register 1

ADCA_CR 2

Control Register 2

ADCA_ZCC

Zero Crossing Control Register

ADCA_LST 1

Channel List Register 1

ADCA_LST 2

Channel List Register 2

ADCA_SDIS

Sample Disable Register

ADCA_STAT

Status Register

ADCA_LSTAT

Limit Status Register

ADCA_ZCSTAT

Zero Crossing Status Register

ADCA_RSLT 0

Result Register 0

ADCA_RSLT 1

Result Register 1

ADCA_RSLT 2

Result Register 2

ADCA_RSLT 3

Result Register 3

ADCA_RSLT 4

Result Register 4

ADCA_RSLT 5

Result Register 5

ADCA_RSLT 6

Result Register 6

ADCA_RSLT 7

$10

Result Register 7

ADCA_LLMT 0

$11

Low Limit Register 0

ADCA_LLMT 1

$12

Low Limit Register 1

ADCA_LLMT 2

$13

Low Limit Register 2

ADCA_LLMT 3

$14

Low Limit Register 3

Table 4-19 Interrupt Control Registers Address Map

(ITCN_BASE = $00 F1A0) (Continued)

Register Acronym

Address Offset

Register Description

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56F8346 Technical Data

Preliminary

ADCA_LLMT 4

$15

Low Limit Register 4

ADCA_LLMT 5

$16

Low Limit Register 5

ADCA_LLMT 6

$17

Low Limit Register 6

ADCA_LLMT 7

$18

Low Limit Register 7

ADCA_HLMT 0

$19

High Limit Register 0

ADCA_HLMT 1

$1A

High Limit Register 1

ADCA_HLMT 2

$1B

High Limit Register 2

ADCA_HLMT 3

$1C

High Limit Register 3

ADCA_HLMT 4

$1D

High Limit Register 4

ADCA_HLMT 5

$1E

High Limit Register 5

ADCA_HLMT 6

$1F

High Limit Register 6

ADCA_HLMT 7

$20

High Limit Register 7

ADCA_OFS 0

$21

Offset Register 0

ADCA_OFS 1

$22

Offset Register 1

ADCA_OFS 2

$23

Offset Register 2

ADCA_OFS 3

$24

Offset Register 3

ADCA_OFS 4

$25

Offset Register 4

ADCA_OFS 5

$26

Offset Register 5

ADCA_OFS 6

$27

Offset Register 6

ADCA_OFS 7

$28

Offset Register 7

ADCA_POWER

$29

Power Control Register

ADCA_CAL

$2A

ADC Calibration Register

Table 4-21 Analog-to-Digital Converter Registers Address Map

(ADCB_BASE = $00 F240)

Register Acronym

Address Offset

Register Description

ADCB_CR 1

Control Register 1

ADCB_CR 2

Control Register 2

ADCB_ZCC

Zero Crossing Control Register

ADCB_LST 1

Channel List Register 1

ADCB_LST 2

Channel List Register 2

ADCB_SDIS

Sample Disable Register

ADCB_STAT

Status Register

ADCB_LSTAT

Limit Status Register

ADCB_ZCSTAT

Zero Crossing Status Register

Table 4-20 Analog-to-Digital Converter Registers Address Map

(ADCA_BASE = $00 F200) (Continued)

Register Acronym

Address Offset

Register Description

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Peripheral Memory Mapped Registers

56F8346 Technical Data

Preliminary

ADCB_RSLT 0

Result Register 0

ADCB_RSLT 1

Result Register 1

ADCB_RSLT 2

Result Register 2

ADCB_RSLT 3

Result Register 3

ADCB_RSLT 4

Result Register 4

ADCB_RSLT 5

Result Register 5

ADCB_RSLT 6

Result Register 6

ADCB_RSLT 7

$10

Result Register 7

ADCB_LLMT 0

$11

Low Limit Register 0

ADCB_LLMT 1

$12

Low Limit Register 1

ADCB_LLMT 2

$13

Low Limit Register 2

ADCB_LLMT 3

$14

Low Limit Register 3

ADCB_LLMT 4

$15

Low Limit Register 4

ADCB_LLMT 5

$16

Low Limit Register 5

ADCB_LLMT 6

$17

Low Limit Register 6

ADCB_LLMT 7

$18

Low Limit Register 7

ADCB_HLMT 0

$19

High Limit Register 0

ADCB_HLMT 1

$1A

High Limit Register 1

ADCB_HLMT 2

$1B

High Limit Register 2

ADCB_HLMT 3

$1C

High Limit Register 3

ADCB_HLMT 4

$1D

High Limit Register 4

ADCB_HLMT 5

$1E

High Limit Register 5

ADCB_HLMT 6

$1F

High Limit Register 6

ADCB_HLMT 7

$20

High Limit Register 7

ADCB_OFS 0

$21

Offset Register 0

ADCB_OFS 1

$22

Offset Register 1

ADCB_OFS 2

$23

Offset Register 2

ADCB_OFS 3

$24

Offset Register 3

ADCB_OFS 4

$25

Offset Register 4

ADCB_OFS 5

$26

Offset Register 5

ADCB_OFS 6

$27

Offset Register 6

ADCB_OFS 7

$28

Offset Register 7

ADCB_POWER

$29

Power Control Register

ADCB_CAL

$2A

ADC Calibration Register

Table 4-21 Analog-to-Digital Converter Registers Address Map

(ADCB_BASE = $00 F240) (Continued)

Register Acronym

Address Offset

Register Description

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56F8346 Technical Data

Preliminary

Table 4-22 Temperature Sensor Register Address Map

(TSENSOR_BASE = $00 F270)

Register Acronym

Address Offset

Register Description

TSENSOR_CNTL

Control Register

Table 4-23 Serial Communication Interface 0 Registers Address Map

(SCI0_BASE = $00 F280)

Register Acronym

Address Offset

Register Description

SCI0_SCIBR

Baud Rate Register

SCI0_SCICR

Control Register

Reserved

SCI0_SCISR

Status Register

SCI0_SCIDR

Data Register

Table 4-24 Serial Communication Interface 1 Registers Address Map

(SCI1_BASE = $00 F290)

Register Acronym

Address Offset

Register Description

SCI1_SCIBR

Baud Rate Register

SCI1_SCICR

Control Register

Reserved

SCI1_SCISR

Status Register

SCI1_SCIDR

Data Register

Table 4-25 Serial Peripheral Interface 0 Registers Address Map

(SPI0_BASE = $00 F2A0)

Register Acronym

Address Offset

Register Description

SPI0_SPSCR

Status and Control Register

SPI0_SPDSR

Data Size Register

SPI0_SPDRR

Data Receive Register

SPI0_SPDTR

Data Transmitter Register

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Peripheral Memory Mapped Registers

56F8346 Technical Data

Preliminary

Table 4-26 Serial Peripheral Interface 1 Registers Address Map

(SPI1_BASE = $00 F2B0)

Register Acronym

Address Offset

Register Description

SPI1_SPSCR

Status and Control Register

SPI1_SPDSR

Data Size Register

SPI1_SPDRR

Data Receive Register

SPI1_SPDTR

Data Transmitter Register

Table 4-27 Computer Operating Properly Registers Address Map

(COP_BASE = $00 F2C0)

Register Acronym

Address Offset

Register Description

COPCTL

Control Register

COPTO

Time Out Register

COPCTR

Counter Register

Table 4-28 Clock Generation Module Registers Address Map

(CLKGEN_BASE = $00 F2D0)

Register Acronym

Address Offset

Register Description

PLLCR

Control Register

PLLDB

Divide-By Register

PLLSR

Status Register

Reserved

SHUTDOWN

Shutdown Register

OSCTL

Oscillator Control Register

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56F8346 Technical Data

Preliminary

Table 4-29 GPIOA Registers Address Map

(GPIOA_BASE = $00 F2E0)

Register Acronym

Address Offset

Register Description

Reset Value

GPIOA_PUR

Pull-up Enable Register

0 x 3FFF

GPIOA_DR

Data Register

0 x 0000

GPIOA_DDR

Data Direction Register

0 x 0000

GPIOA_PER

Peripheral Enable Register

0 x 3FFF

GPIOA_IAR

Interrupt Assert Register

0 x 0000

GPIOA_IENR

Interrupt Enable Register

0 x 0000

GPIOA_IPOLR

Interrupt Polarity Register

0 x 0000

GPIOA_IPR

Interrupt Pending Register

0 x 0000

GPIOA_IESR

Interrupt Edge-Sensitive Register

0 x 0000

GPIOA_PPMODE

Push-Pull Mode Register

0 x 3FFF

GPIOA_RAWDATA

Raw Data Input Register

Table 4-30 GPIOB Registers Address Map

(GPIOB_BASE = $00 F300)

Register Acronym

Address Offset

Register Description

Reset Value

GPIOB_PUR

Pull-up Enable Register

0 x 00FF

GPIOB_DR

Data Register

0 x 0000

GPIOB_DDR

Data Direction Register

0 x 0000

GPIOB_PER

Peripheral Enable Register

0 x 0000 or

0 x 000F

Determined by EMI_MODE and EXTBOOT. Can be 0x00 or 0x0F, depending on address pin configuration. See

Table 4-4

GPIOB_IAR

Interrupt Assert Register

0 x 0000

GPIOB_IENR

Interrupt Enable Register

0 x 0000

GPIOB_IPOLR

Interrupt Polarity Register

0 x 0000

GPIOB_IPR

Interrupt Pending Register

0 x 0000

GPIOB_IESR

Interrupt Edge-Sensitive Register

0 x 0000

GPIOB_PPMODE

Push-Pull Mode Register

0 x 00FF

GPIOB_RAWDATA

Raw Data Input Register

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Peripheral Memory Mapped Registers

56F8346 Technical Data

Preliminary

Table 4-31 GPIOC Registers Address Map

(GPIOC_BASE = $00 F310)

Register Acronym

Address Offset

Register Description

Reset Value

GPIOC_PUR

Pull-up Enable Register

0 x 07FF

GPIOC_DR

Data Register

0 x 0000

GPIOC_DDR

Data Direction Register

0 x 0000

GPIOC_PER

Peripheral Enable Register

0 x 07FF

GPIOC_IAR

Interrupt Assert Register

0 x 0000

GPIOC_IENR

Interrupt Enable Register

0 x 0000

GPIOC_IPOLR

Interrupt Polarity Register

0 x 0000

GPIOC_IPR

Interrupt Pending Register

0 x 0000

GPIOC_IESR

Interrupt Edge-Sensitive Register

0 x 0000

GPIOC_PPMODE

Push-Pull Mode Register

0 x 07FF

GPIOC_RAWDATA

Raw Data Input Register

Table 4-32 GPIOD Registers Address Map

(GPIOD_BASE = $00 F320)

Register Acronym

Address Offset

Register Description

Reset Value

GPIOD_PUR

Pull-up Enable Register

0 x 1FFF

GPIOD_DR

Data Register

0 x 0000

GPIOD_DDR

Data Direction Register

0 x 0000

GPIOD_PER

Peripheral Enable Register

0 x 1FC0

GPIOD_IAR

Interrupt Assert Register

0 x 0000

GPIOD_IENR

Interrupt Enable Register

0 x 0000

GPIOD_IPOLR

Interrupt Polarity Register

0 x 0000

GPIOD_IPR

Interrupt Pending Register

0 x 0000

GPIOD_IESR

Interrupt Edge-Sensitive Register

0 x 0000

GPIOD_PPMODE

Push-Pull Mode Register

0 x 1FFF

GPIOD_RAWDATA

Raw Data Input Register

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56F8346 Technical Data

Preliminary

Table 4-33 GPIOE Registers Address Map

(GPIOE_BASE = $00 F330)

Register Acronym

Address Offset

Register Description

Reset Value

GPIOE_PUR

Pull-up Enable Register

0 x 3FFF

GPIOE_DR

Data Register

0 x 0000

GPIOE_DDR

Data Direction Register

0 x 0000

GPIOE_PER

Peripheral Enable Register

0 x 3FFF

GPIOE_IAR

Interrupt Assert Register

0 x 0000

GPIOE_IENR

Interrupt Enable Register

0 x 0000

GPIOE_IPOLR

Interrupt Polarity Register

0 x 0000

GPIOE_IPR

Interrupt Pending Register

0 x 0000

GPIOE_IESR

Interrupt Edge-Sensitive Register

0 x 0000

GPIOE_PPMODE

Push-Pull Mode Register

0 x 3FFF

GPIOE_RAWDATA

Raw Data Input Register

Table 4-34 GPIOF Registers Address Map

(GPIOF_BASE = $00 F340)

Register Acronym

Address Offset

Register Description

Reset Value

GPIOF_PUR

Pull-up Enable Register

0 x FFFF

GPIOF_DR

Data Register

0 x 0000

GPIOF_DDR

Data Direction Register

0 x 0000

GPIOF_PER

Peripheral Enable Register

0 x FFFF

GPIOF_IAR

Interrupt Assert Register

0 x 0000

GPIOF_IENR

Interrupt Enable Register

0 x 0000

GPIOF_IPOLR

Interrupt Polarity Register

0 x 0000

GPIOF_IPR

Interrupt Pending Register

0 x 0000

GPIOF_IESR

Interrupt Edge-Sensitive Register

0 x 0000

GPIOF_PPMODE

Push-Pull Mode Register

0 x FFFF

GPIOF_RAWDATA

Raw Data Input Register

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Peripheral Memory Mapped Registers

56F8346 Technical Data

Preliminary

Table 4-35 System Integration Module Registers Address Map

(SIM_BASE = $00 F350)

Register Acronym

Address Offset

Register Description

SIM_CONTROL

Control Register

SIM_RSTSTS

Reset Status Register

SIM_SCR0

Software Control Register 0

SIM_SCR1

Software Control Register 1

SIM_SCR2

Software Control Register 2

SIM_SCR3

Software Control Register 3

SIM_MSH_ID

Most Significant Half JTAG ID

SIM_LSH_ID

Least Significant Half JTAG ID

SIM_PUDR

Pull-up Disable Register

Reserved

SIM_CLKOSR

Clock Out Select Register

SIM_GPS

Quad Decoder 1 / Timer B / SPI 1 Select Register

SIM_PCE

Peripheral Clock Enable Register

SIM_ISALH

I/O Short Address Location High Register

SIM_ISALL

I/O Short Address Location Low Register

Table 4-36 Power Supervisor Registers Address Map

(LVI_BASE = $00 F360)

Register Acronym

Address Offset

Register Description

LVI_CONTROL

Control Register

LVI_STATUS

Status Register

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56F8346 Technical Data

Preliminary

Table 4-37 Flash Module Registers Address Map

(FM_BASE = $00 F400)

Register Acronym

Address Offset

Register Description

FMCLKD

Clock Divider Register

FMMCR

Module Control Register

Reserved

FMSECH

Security High Half Register

FMSECL

Security Low Half Register

FMMNTR

Monitor Data Register

Reserved

FMPROT

$10

Protection Register (Banked)

FMPROTB

$11

Protection Boot Register (Banked)

Reserved

FMUSTAT

$13

User Status Register (Banked)

FMCMD

$14

Command Register (Banked)

FMCTL

$15

Control Register (Banked)

Reserved

FMIFROPT 0

$1A

16-Bit Information Option Register 0
Hot temperature ADC reading of Temperature Sensor;
value set during factory test

FMIFROPT 1

$1B

16-Bit Information Option Register 1
Not used

FMIFROPT 2

$1C

16-Bit Information Option Register 2
Room temperature ADC reading of Temperature Sensor;
value set during factory test

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Peripheral Memory Mapped Registers

56F8346 Technical Data

Preliminary

Table 4-38 FlexCAN Registers Address Map

(FC_BASE = $00 F800)

Register Acronym

Address Offset

Register Description

FCMCR

Module Configuration Register

Reserved

FCCTL0

Control Register 0 Register

FCCTL1

Control Register 1 Register

FCTMR

Free-Running Timer Register

FCMAXMB

Maximum Message Buffer

Configuration Register

FCIMASK2

Interrupt Masks 2 Register

FCRXGMASK_H

Receive Global Mask High Register

FCRXGMASK_L

Receive Global Mask Low Register

FCRX14MASK_H

Receive Buffer 14 Mask High Register

FCRX14MASK_L

Receive Buffer 14 Mask Low Register

FCRX15MASK_H

Receive Buffer 15 Mask High Register

FCRX15MASK_L

Receive Buffer 15 Mask Low Register

Reserved

FCSTATUS

$10

Error and Status Register

FCIMASK1

$11

Interrupt Masks 1 Register

FCIFLAG1

$12

Interrupt Flags 1 Register

FCR/T_ERROR_CNTRS

$13

Receive and Transmit Error Counters Register

Reserved

FCIFLAG 2

$1B

Interrupt Flags 2 Register

Reserved

FCMB0_CONTROL

$40

Message Buffer 0 Control / Status Register

FCMB0_ID_HIGH

$41

Message Buffer 0 ID High Register

FCMB0_ID_LOW

$42

Message Buffer 0 ID Low Register

FCMB0_DATA

$43

Message Buffer 0 Data Register

FCMB0_DATA

$44

Message Buffer 0 Data Register

FCMB0_DATA

$45

Message Buffer 0 Data Register

FCMB0_DATA

$46

Message Buffer 0 Data Register

Reserved

FCMSB1_CONTROL

$48

Message Buffer 1 Control / Status Register

FCMSB1_ID_HIGH

$49

Message Buffer 1 ID High Register

FCMSB1_ID_LOW

$4A

Message Buffer 1 ID Low Register

FCMB1_DATA

$4B

Message Buffer 1 Data Register

FCMB1_DATA

$4C

Message Buffer 1 Data Register

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56F8346 Technical Data

Preliminary

FCMB1_DATA

$4D

Message Buffer 1 Data Register

FCMB1_DATA

$4E

Message Buffer 1 Data Register

Reserved

FCMB2_CONTROL

$50

Message Buffer 2 Control / Status Register

FCMB2_ID_HIGH

$51

Message Buffer 2 ID High Register

FCMB2_ID_LOW

$52

Message Buffer 2 ID Low Register

FCMB2_DATA

$53

Message Buffer 2 Data Register

FCMB2_DATA

$54

Message Buffer 2 Data Register

FCMB2_DATA

$55

Message Buffer 2 Data Register

FCMB2_DATA

$56

Message Buffer 2 Data Register

Reserved

FCMB3_CONTROL

$58

Message Buffer 3 Control / Status Register

FCMB3_ID_HIGH

$59

Message Buffer 3 ID High Register

FCMB3_ID_LOW

$5A

Message Buffer 3 ID Low Register

FCMB3_DATA

$5B

Message Buffer 3 Data Register

FCMB3_DATA

$5C

Message Buffer 3 Data Register

FCMB3_DATA

$5D

Message Buffer 3 Data Register

FCMB3_DATA

$5E

Message Buffer 3 Data Register

Reserved

FCMB4_CONTROL

$60

Message Buffer 4 Control / Status Register

FCMB4_ID_HIGH

$61

Message Buffer 4 ID High Register

FCMB4_ID_LOW

$62

Message Buffer 4 ID Low Register

FCMB4_DATA

$63

Message Buffer 4 Data Register

FCMB4_DATA

$64

Message Buffer 4 Data Register

FCMB4_DATA

$65

Message Buffer 4 Data Register

FCMB4_DATA

$66

Message Buffer 4 Data Register

Reserved

FCMB5_CONTROL

$68

Message Buffer 5 Control / Status Register

FCMB5_ID_HIGH

$69

Message Buffer 5 ID High Register

FCMB5_ID_LOW

$6A

Message Buffer 5 ID Low Register

FCMB5_DATA

$6B

Message Buffer 5 Data Register

FCMB5_DATA

$6C

Message Buffer 5 Data Register

FCMB5_DATA

$6D

Message Buffer 5 Data Register

FCMB5_DATA

$6E

Message Buffer 5 Data Register

Table 4-38 FlexCAN Registers Address Map

(FC_BASE = $00 F800) (Continued)

Register Acronym

Address Offset

Register Description

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Peripheral Memory Mapped Registers

56F8346 Technical Data

Preliminary

Reserved

FCMB6_CONTROL

$70

Message Buffer 6 Control / Status Register

FCMB6_ID_HIGH

$71

Message Buffer 6 ID High Register

FCMB6_ID_LOW

$72

Message Buffer 6 ID Low Register

FCMB6_DATA

$73

Message Buffer 6 Data Register

FCMB6_DATA

$74

Message Buffer 6 Data Register

FCMB6_DATA

$75

Message Buffer 6 Data Register

FCMB6_DATA

$76

Message Buffer 6 Data Register

Reserved

FCMB7_CONTROL

$78

Message Buffer 7 Control / Status Register

FCMB7_ID_HIGH

$79

Message Buffer 7 ID High Register

FCMB7_ID_LOW

$7A

Message Buffer 7 ID Low Register

FCMB7_DATA

$7B

Message Buffer 7 Data Register

FCMB7_DATA

$7C

Message Buffer 7 Data Register

FCMB7_DATA

$7D

Message Buffer 7 Data Register

FCMB7_DATA

$7E

Message Buffer 7 Data Register

Reserved

FCMB8_CONTROL

$80

Message Buffer 8 Control / Status Register

FCMB8_ID_HIGH

$81

Message Buffer 8 ID High Register

FCMB8_ID_LOW

$82

Message Buffer 8 ID Low Register

FCMB8_DATA

$83

Message Buffer 8 Data Register

FCMB8_DATA

$84

Message Buffer 8 Data Register

FCMB8_DATA

$85

Message Buffer 8 Data Register

FCMB8_DATA

$86

Message Buffer 8 Data Register

Reserved

FCMB9_CONTROL

$88

Message Buffer 9 Control / Status Register

FCMB9_ID_HIGH

$89

Message Buffer 9 ID High Register

FCMB9_ID_LOW

$8A

Message Buffer 9 ID Low Register

FCMB9_DATA

$8B

Message Buffer 9 Data Register

FCMB9_DATA

$8C

Message Buffer 9 Data Register

FCMB9_DATA

$8D

Message Buffer 9 Data Register

FCMB9_DATA

$8E

Message Buffer 9 Data Register

Reserved

Table 4-38 FlexCAN Registers Address Map

(FC_BASE = $00 F800) (Continued)

Register Acronym

Address Offset

Register Description

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56F8346 Technical Data

Preliminary

FCMB10_CONTROL

$90

Message Buffer 10 Control / Status Register

FCMB10_ID_HIGH

$91

Message Buffer 10 ID High Register

FCMB10_ID_LOW

$92

Message Buffer 10 ID Low Register

FCMB10_DATA

$93

Message Buffer 10 Data Register

FCMB10_DATA

$94

Message Buffer 10 Data Register

FCMB10_DATA

$95

Message Buffer 10 Data Register

FCMB10_DATA

$96

Message Buffer 10 Data Register

Reserved

FCMB11_CONTROL

$98

Message Buffer 11 Control / Status Register

FCMB11_ID_HIGH

$99

Message Buffer 11 ID High Register

FCMB11_ID_LOW

$9A

Message Buffer 11 ID Low Register

FCMB11_DATA

$9B

Message Buffer 11 Data Register

FCMB11_DATA

$9C

Message Buffer 11 Data Register

FCMB11_DATA

$9D

Message Buffer 11 Data Register

FCMB11_DATA

$9E

Message Buffer 11 Data Register

Reserved

FCMB12_CONTROL

$A0

Message Buffer 12 Control / Status Register

FCMB12_ID_HIGH

$A1

Message Buffer 12 ID High Register

FCMB12_ID_LOW

$A2

Message Buffer 12 ID Low Register

FCMB12_DATA

$A3

Message Buffer 12 Data Register

FCMB12_DATA

$A4

Message Buffer 12 Data Register

FCMB12_DATA

$A5

Message Buffer 12 Data Register

FCMB12_DATA

$A6

Message Buffer 12 Data Register

Reserved

FCMB13_CONTROL

$A8

Message Buffer 13 Control / Status Register

FCMB13_ID_HIGH

$A9

Message Buffer 13 ID High Register

FCMB13_ID_LOW

$AA

Message Buffer 13 ID Low Register

FCMB13_DATA

$AB

Message Buffer 13 Data Register

FCMB13_DATA

$AC

Message Buffer 13 Data Register

FCMB13_DATA

$AD

Message Buffer 13 Data Register

FCMB13_DATA

$AE

Message Buffer 13 Data Register

Reserved

Table 4-38 FlexCAN Registers Address Map

(FC_BASE = $00 F800) (Continued)

Register Acronym

Address Offset

Register Description

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Factory Programmed Memory

56F8346 Technical Data

Preliminary

4.8 Factory Programmed Memory

During manufacturing the Boot Flash memory block is programmed with a default Serial Boot-
loader program. The Serial Bootloader application can be used to load a user application into the
Program and Data Flash memories of the device. The document MC56F83xxBLUM/D, 56F83xx
SCI/CAN Bootloader User Manual provides detailed information on this firmware. The appli-
cation note AN1973/D, Production Flash Programming provides additional information on
how the Serial Bootloader program can be used to perform production flash programming of the
on board flash memories as well as other potential methods.

Like all the flash memory blocks the Boot Flash can be erased and programmed by the user. The
Serial Bootloader application is programmed as an aid to the end user, but is not required to be used
or maintained in the Boot Flash memory.

FCMB14_CONTROL

$B0

Message Buffer 14 Control / Status Register

FCMB14_ID_HIGH

$B1

Message Buffer 14 ID High Register

FCMB14_ID_LOW

$B2

Message Buffer 14 ID Low Register

FCMB14_DATA

$B3

Message Buffer 14 Data Register

FCMB14_DATA

$B4

Message Buffer 14 Data Register

FCMB14_DATA

$B5

Message Buffer 14 Data Register

FCMB14_DATA

$B6

Message Buffer 14 Data Register

Reserved

FCMB15_CONTROL

$B8

Message Buffer 15 Control / Status Register

FCMB15_ID_HIGH

$B9

Message Buffer 15 ID High Register

FCMB15_ID_LOW

$BA

Message Buffer 15 ID Low Register

FCMB15_DATA

$BB

Message Buffer 15 Data Register

FCMB15_DATA

$BC

Message Buffer 15 Data Register

FCMB15_DATA

$BD

Message Buffer 15 Data Register

FCMB15_DATA

$BE

Message Buffer 15 Data Register

Reserved

Table 4-38 FlexCAN Registers Address Map

(FC_BASE = $00 F800) (Continued)

Register Acronym

Address Offset

Register Description

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56F8346 Technical Data

Preliminary

Part 5 Interrupt Controller (ITCN)

5.1 Introduction

The Interrupt Controller (ITCN) module is used to arbitrate between various interrupt requests
(IRQs), to signal to the 56800E core when an interrupt of sufficient priority exists, and to what
address to jump in order to service this interrupt.

5.2 Features

The ITCN module design includes these distinctive features:

Programmable priority levels for each IRQ

Two programmable Fast Interrupts

Notification to SIM module to restart clocks out of Wait and Stop modes

Drives initial address on the address bus after reset

For further information, see

Table 4-5

, Interrupt Vector Table Contents.

5.3 Functional Description

The Interrupt Controller is a slave on the IPBus. It contains registers allowing each of the 82
interrupt sources to be set to one of four priority levels, excluding certain interrupts of fixed
priority. Next, all of the interrupt requests of a given level are priority encoded to determine the
lowest numerical value of the active interrupt requests for that level. Within a given priority level,
zero is the highest priority, while number 81 is the lowest.

5.3.1

Normal Interrupt Handling

Once the ITCN has determined that an interrupt is to be serviced and which interrupt has the
highest priority, an interrupt vector address is generated. Normal interrupt handling concatenates
the VBA and the vector number to determine the vector address. In this way, an offset is generated
into the vector table for each interrupt.

5.3.2

Interrupt Nesting

Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to
be serviced. The following tables define the nesting requirements for each priority level.

Table 5-1 Interrupt Mask Bit Definition

SR[9]

Core status register bits indicating current interrupt mask within the core.

SR[8]

Permitted Exceptions

Masked Exceptions

Priorities 0, 1, 2, 3

None

Priorities 1, 2, 3

Priority 0

Priorities 2, 3

Priorities 0, 1

Priority 3

Priorities 0, 1, 2

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Functional Description

56F8346 Technical Data

Preliminary

5.3.3

Fast Interrupt Handling

Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller
recognizes fast interrupts before the core does.

A fast interrupt is defined (to the ITCN) by:

1. Setting the priority of the interrupt as level 2, with the appropriate field in the IPR registers

2. Setting the FIMn register to the appropriate vector number

3. Setting the FIVALn and FIVAHn registers with the address of the code for the fast interrupt

When an interrupt occurs, its vector number is compared with the FIM0 and FIM1 register values.
If a match occurs, and it is a level 2 interrupt, the ITCN handles it as a fast interrupt. The ITCN
takes the vector address from the appropriate FIVALn and FIVAHn registers, instead of generating
an address that is an offset from the VBA.

The core then fetches the instruction from the indicated vector adddress and if it is not a JSR, the
core starts its fast interrupt handling.

Table 5-2 Interrupt Priority Encoding

IPIC_LEVEL[1:0]

See IPIC field definition in

Section 5.6.30.2

Current Interrupt

Priority Level

Required Nested

Exception Priority

No Interrupt or SWILP

Priorities 0, 1, 2, 3

Priority 0

Priorities 1, 2, 3

Priority 1

Priorities 2, 3

Priorities 2 or 3

Priority 3

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56F8346 Technical Data

Preliminary

5.4 Block Diagram

Figure 5-1 Interrupt Controller Block Diagram

5.5 Operating Modes

The ITCN module design contains two major modes of operation:

Functional Mode
The ITCN is in this mode by default.

Wait and Stop Modes
During Wait and Stop modes, the system clocks and the 56800E core are turned off. The ITCN will
signal a pending IRQ to the System Integration Module (SIM) to restart the clocks and service the
IRQ. An IRQ can only wake up the core if the IRQ is enabled prior to entering the Wait or Stop
mode. Also, the IRQA and IRQB signals automatically become low-level sensitive in these modes
even if the control register bits are set to make them falling-edge sensitive. This is because there is
no clock available to detect the falling edge.

A peripheral which requires a clock to generate interrupts will not be able to generate interrupts
during Stop mode. The FlexCAN module can wake the device from Stop mode, and a reset will do
just that, or IRQA and IRQB can wake it up.

Priority

Level

2 -> 4

Decode

INT1

Priority

Level

2 -> 4

Decode

INT82

Level 0

82 -> 7

Priority

Encoder

any0

Level 3

82 -> 7

Priority

Encoder

any3

INT

VAB

IPIC

CONTROL

PIC_EN

IACK

SR[9:8]

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56F8346 Technical Data

Preliminary

5.6 Register Descriptions

A register address is the sum of a base address and an address offset. The base address is defined
at the system level and the address offset is defined at the module level. The ITCN peripheral has
24 registers.

Table 5-3 ITCN Register Summary

(ITCN_BASE = $00F1A0)

Register

Acronym

Base Address +

Register Name

Section Location

IPR0

Interrupt Priority Register 0

5.6.1

IPR1

Interrupt Priority Register 1

5.6.2

IPR2

Interrupt Priority Register 2

5.6.3

IPR3

Interrupt Priority Register 3

5.6.4

IPR4

Interrupt Priority Register 4

5.6.5

IPR5

Interrupt Priority Register 5

5.6.6

IPR6

Interrupt Priority Register 6

5.6.7

IPR7

Interrupt Priority Register 7

5.6.8

IPR8

Interrupt Priority Register 8

5.6.9

IPR9

Interrupt Priority Register 9

5.6.10

VBA

Vector Base Address Register

5.6.11

FIM0

Fast Interrupt 0 Match Register

5.6.12

FIVAL0

Fast Interrupt 0 Vector Address Low Register

5.6.13

FIVAH0

Fast Interrupt 0 Vector Address High Register

5.6.14

FIM1

Fast Interrupt 1 Match Register

5.6.15

FIVAL1

Fast Interrupt 1 Vector Address Low Register

5.6.16

FIVAH1

$10

Fast Interrupt 1 Vector Address High Register

5.6.17

IRQP0

$11

IRQ Pending Register 0

5.6.18

IRQP1

$12

IRQ Pending Register 1

5.6.19

IRQP2

$13

IRQ Pending Register 2

5.6.20

IRQP3

$14

IRQ Pending Register 3

5.6.21

IRQP4

$15

IRQ Pending Register 4

5.6.22

IRQP5

$16

IRQ Pending Register 5

5.6.23

Reserved

$17

ICTL

$1D

Interrupt Control Register

5.6.30

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56F8346 Technical Data

Preliminary

Add.

Offset

Register

Name

IPR0

BKPT_U0 IPL

STPCNT IPL

IPR1

RX_REG IPL

TX_REG IPL

TRBUF IPL

IPR2

FMCBE IPL

FMCC IPL

FMERR IPL

LOCK IPL

LVI IPL

IRQB IPL

IRQA IPL

IPR3

GPIOD

IPL

GPIOE

IPL

GPIOF

IPL

FCMSGBUF IPL

FCWKUP IPL

FCERR IPL

FCBOFF IPL

IPR4

SPI0_RCV IPL

SPI1_XMIT IPL

SPI1_RCV

IPL

GPIOA

IPL

GPIOB

IPL

GPIOC

IPL

IPR5

DEC1_XIRQ IPL DEC1_HIRQ IPL

SCI1_RCV

IPL

SCI1_RERR IPL

SCI1_TIDL IPL

SCI1_XMIT IPL

SPI0_XMIT IPL

IPR6

TMRC0 IPL

TMRD3 IPL

TMRD2 IPL

TMRD1 IPL

TMRD0 IPL

DEC0_XIRQ IPL DEC0_HIRQ IPL

IPR7

TMRA0 IPL

TMRB3 IPL

TMRB2 IPL

TMRB1 IPL

TMRB0 IPL

TMRC3 IPL

TMRC2 IPL

TMRC1 IPL

IPR8

SCI0_RCV IPL

SCI0_RERR IPL

SCI0_TIDL IPL

SCI0_XMIT IPL

TMRA3 IPL

TMRA2 IPL

TMRA1 IPL

IPR9

PWMA F IPL

PWMB F IPL

PWMA_RL

IPL

PWMB_RL IPL

ADCA_ZC IPL

ABCB_ZC IPL

ADCA_CC IPL

ADCB_CC IPL

VBA

VECTOR BASE ADDRESS

VBA0

FAST INTERRUPT 0

FIVAL0

FAST INTERRUPT 0 VECTOR ADDRESS LOW

FIVAH0

FAST INTERRUPT 0

VECTOR ADDRESS HIGH

FIM1

FAST INTERRUPT 1

FIVAL1

FAST INTERRUPT 1

VECTOR ADDRESS LOW

$10

FIVAH1

FAST INTERRUPT 1

VECTOR ADDRESS HIGH

$11

IRQP0

PENDING [16:2]

$12

IRQP1

PENDING [32:17]

$13

IRQP2

PENDING [48:33]

$14

IRQP3

PENDING [64:49]

$15

IRQP4

PENDING [80:65]

$16

IRQP5

PEND-

ING

[81]

Reserved

$1D

ICTL

INT

IPIC

VAB

INT_DIS

IRQB

STATE

IRQA

STATE

IRQB

EDG

IRQA

EDG

= Reserved

Figure 5-2 ITCN Register Map Summary

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56F8346 Technical Data

Preliminary

5.6.1

Interrupt Priority Register 0 (IPR0)

Figure 5-3 Interrupt Priority Register 0 (IPR0)

5.6.1.1

Reserved--Bits 1514

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.1.2

EOnCE Breakpoint Unit 0 Interrupt Priority Level (BKPT_U0 IPL)--

Bits1312

This field is used to set the interrupt priority levels for IRQs. This IRQ is limited to priorities 1
through 3. It is disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 1

10 = IRQ is priority level 2

11 = IRQ is priority level 3

5.6.1.3

EOnCE Step Counter Interrupt Priority Level (STPCNT IPL)--

Bits 1110

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1
through 3. It is disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 1

10 = IRQ is priority level 2

11 = IRQ is priority level 3

5.6.1.4

Reserved--Bits 90

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.2

Interrupt Priority Register 1 (IPR1)

Figure 5-4 Interrupt Priority Register 1 (IPR1)

5.6.2.1

Reserved--Bits 156

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

Base + $0

Read

BKPT_U0 IPL

STPCNT IPL

Write

RESET

Base + $1

Read

RX_REG IPL

TX_REG IPL

TRBUF IPL

Write

RESET

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56F8346 Technical Data

Preliminary

5.6.2.2

EOnCE Receive Register Full Interrupt Priority Level

(RX_REG IPL)--Bits 54

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1
through 3. It is disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 1

10 = IRQ is priority level 2

11 = IRQ is priority level 3

5.6.2.3

EOnCE Transmit Register Empty Interrupt Priority Level

(TX_REG IPL)--Bits 32

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1
through 3. It is disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 1

10 = IRQ is priority level 2

11 = IRQ is priority level 3

5.6.2.4

EOnCE Trace Buffer Interrupt Priority Level (TRBUF IPL)--

Bits 10

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1
through 3. It is disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 1

10 = IRQ is priority level 2

11 = IRQ is priority level 3

5.6.3

Interrupt Priority Register 2 (IPR2)

Figure 5-5 Interrupt Priority Register 2 (IPR2)

Base + $2

Read

FMCBE IPL

FMCC IPL

FMERR IPL

LOCK IPL

LVI IPL

IRQB IPL

IRQA IPL

Write

RESET

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56F8346 Technical Data

Preliminary

5.6.3.1

Flash Memory Command, Data, Address Buffers Empty Interrupt

Priority Level (FMCBE IPL)--Bits 1514

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. It is disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.3.2

Flash Memory Command Complete Priority Level

(FMCC IPL)--Bits 1312

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. It is disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.3.3

Flash Memory Error Interrupt Priority Level

(FMERR IPL)--Bits 1110

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. It is disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.3.4

PLL Loss of Lock Interrupt Priority Level (LOCK IPL)--Bits 98

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. It is disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

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56F8346 Technical Data

Preliminary

5.6.3.5

Low Voltage Detector Interrupt Priority Level (LVI IPL)--Bits 76

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. It is disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.3.6

Reserved--Bits 54

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.3.7

External IRQ B Interrupt Priority Level (IRQB IPL)--Bits 32

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. It is disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.3.8

External IRQ A Interrupt Priority Level (IRQA IPL)--Bits 10

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. It is disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.4

Interrupt Priority Register 3 (IPR3)

Figure 5-6 Interrupt Priority Register 3 (IPR3)

5.6.4.1

GPIO D Interrupt Priority Level (GPIOD IPL)--Bits 1514

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

Base + $3

Read

GPIODIPL

GPIOE IPL

GPIOFIPL

FCMSGBUF IPL

FCWKUP IPL

FCERR IPL

FCBOFF IPL

Write

RESET

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56F8346 Technical Data

Preliminary

5.6.4.2

GPIO E Interrupt Priority Level (GPIOE IPL)--Bits 1312

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.4.3

GPIO F Interrupt Priority Level (GPIOF IPL)--Bits 1110

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2two. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.4.4

FlexCAN Message Buffer Interrupt Priority Level

(FCMSGBUF IPL)--Bits 98

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.4.5

FlexCAN Wake Up Interrupt Priority Level (FCWKUP IPL)--

Bits 76

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.4.6

FlexCAN Error Interrupt Priority Level (FCERR IPL)-- Bits 54

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

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56F8346 Technical Data

Preliminary

5.6.4.7

FlexCAN Bus Off Interrupt Priority Level (FCBOFF IPL)-- Bits 32

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.4.8

Reserved--Bits 10

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.5

Interrupt Priority Register 4 (IPR4)

Figure 5-7 Interrupt Priority Register 4 (IPR4)

5.6.5.1

SPI0 Receiver Full Interrupt Priority Level (SPI0_RCV IPL)--

Bits 1514

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.5.2

SPI1 Transmit Empty Interrupt Priority Level (SPI1_XMIT IPL)--

Bits 1312

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

Base + $4

Read

SPI0_RCV

IPL

SPI1_XMIT

IPL

SPI1_RCV

IPL

GPIOA IPL

GPIOB IPL

GPIOC IPL

Write

RESET

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56F8346 Technical Data

Preliminary

5.6.5.3

SPI1 Receiver Full Interrupt Priority Level (SPI1_RCV IPL)--

Bits 1110

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.5.4

Reserved--Bits 96

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.5.5

GPIO A Interrupt Priority Level (GPIOA IPL)--Bits 54

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.5.6

GPIO B Interrupt Priority Level (GPIOB IPL)--Bits 32

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.5.7

GPIO C Interrupt Priority Level (GPIOC IPL)--Bits 10

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

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56F8346 Technical Data

Preliminary

5.6.6

Interrupt Priority Register 5 (IPR5)

Figure 5-8 Interrupt Priority Register 5 (IPR5)

5.6.6.1

Quadrature Decoder 1 INDEX Pulse Interrupt Priority Level

(DEC1_XIRQ IPL)--Bits 1514

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.6.2

Quadrature Decoder 1 HOME Signal Transition or Watchdog Timer

Interrupt Priority Level (DEC1_HIRQ IPL)--Bits 1312

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.6.3

SCI 1 Receiver Full Interrupt Priority Level (SCI1_RCV IPL)--

Bits 1110

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

Base + $5

Read

DEC1_XIRQ

IPL

DEC1_HIRQ

IPL

SCI1_RCV

IPL

SCI1_RERR

IPL

SCI1_TIDL

IPL

SCI1_XMIT

IPL

SPI0_XMIT

IPL

Write

RESET

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56F8346 Technical Data

Preliminary

5.6.6.4

SCI 1 Receiver Error Interrupt Priority Level (SCI1_RERR IPL)--

Bits 98

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.6.5

Reserved--Bits 76

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.6.6

SCI 1 Transmitter Idle Interrupt Priority Level (SCI1_TIDL IPL)--

Bits 54

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.6.7

SCI 1 Transmitter Empty Interrupt Priority Level (SCI1_XMIT IPL)--

Bits 32

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.6.8

SPI 0 Transmitter Empty Interrupt Priority Level (SPI0_XMIT IPL)--

Bits 10

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

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56F8346 Technical Data

Preliminary

5.6.7

Interrupt Priority Register 6 (IPR6)

Figure 5-9 Interrupt Priority Register 6 (IPR6)

5.6.7.1

Timer C, Channel 0 Interrupt Priority Level (TMRC0 IPL)--

Bits 1514

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.7.2

Timer D, Channel 3 Interrupt Priority Level (TMRD3 IPL)--

Bits 1312

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.7.3

Timer D, Channel 2 Interrupt Priority Level (TMRD2 IPL)--

Bits 1110

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

Base + $6

Read

TMRC0 IPL

TMRD3 IPL

TMRD2 IPL

TMRD1 IPL

TMRD0 IPL

DEC0_XIRQ

IPL

DEC0_HIRQ

IPL

Write

RESET

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56F8346 Technical Data

Preliminary

5.6.7.4

Timer D, Channel 1 Interrupt Priority Level (TMRD1 IPL)--

Bits 98

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.7.5

Timer D, Channel 0 Interrupt Priority Level (TMRD0 IPL)--

Bits 76

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.7.6

Reserved--Bits 54

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.7.7

Quadrature Decoder 0, INDEX Pulse Interrupt Priority Level

(DEC0_XIRQ IPL)--Bits 32

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.7.8

Quadrature Decoder 0, HOME Signal Transition or Watchdog

Timer Interrupt Priority Level (DEC0_HIRQ IPL)--Bits 10

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

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56F8346 Technical Data

Preliminary

5.6.8

Interrupt Priority Register 7 (IPR7)

Figure 5-10 Interrupt Priority Register (IPR7)

5.6.8.1

Timer A, Channel 0 Interrupt Priority Level (TMRA0 IPL)--

Bits 1514

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.8.2

Timer B, Channel 3 Interrupt Priority Level (TMRB3 IPL)--

Bits 1312

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.8.3

Timer B, Channel 2 Interrupt Priority Level (TMRB2 IPL)--

Bits 1110

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

Base + $7

Read

TMRA0 IPL

TMRB3 IPL

TMRB2 IPL

TMRB1 IPL

TMRB0 IPL

TMRC3 IPL

TMRC2 IPL

TMRC1 IPL

Write

RESET

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56F8346 Technical Data

Preliminary

5.6.8.4

Timer B, Channel 1 Interrupt Priority Level (TMRB1 IPL)--Bits 98

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.8.5

Timer B, Channel 0 Interrupt Priority Level (TMRB0 IPL)--Bits 76

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.8.6

Timer C, Channel 3 Interrupt Priority Level (TMRC3 IPL)--Bits 54

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.8.7

Timer C, Channel 2 Interrupt Priority Level (TMRC2 IPL)--Bits 32

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.8.8

Timer C, Channel 1 Interrupt Priority Level (TMRC1 IPL)--Bits 10

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

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56F8346 Technical Data

Preliminary

5.6.9

Interrupt Priority Register 8 (IPR8)

Figure 5-11 Interrupt Priority Register 8 (IPR8)

5.6.9.1

SCI0 Receiver Full Interrupt Priority Level (SCI0_RCV IPL)--

Bits 1514

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.9.2

SCI0 Receiver Error Interrupt Priority Level (SCI0_RERR IPL)--

Bits 1312

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.9.3

Reserved--Bits 1110

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.9.4

SCI0 Transmitter Idle Interrupt Priority Level (SCI0_TIDL IPL)--

Bits 98

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

Base + $8

Read

SCI0_RCV

IPL

SCI0_RERR

IPL

SCI0_TIDL

IPL

SCI0_XMIT

IPL

TMRA3 IPL

TMRA2 IPL

TMRA1 IPL

Write

RESET

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56F8346 Technical Data

Preliminary

5.6.9.5

SCI0 Transmitter Empty Interrupt Priority Level (SCI0_XMIT IPL)--

Bits 76

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.9.6

Timer A, Channel 3 Interrupt Priority Level (TMRA3 IPL)--Bits 54

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.9.7

Timer A, Channel 2 Interrupt Priority Level (TMRA2 IPL)--Bits 32

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.9.8

Timer A, Channel 1 Interrupt Priority Level (TMRA1 IPL)--Bits 10

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.10

Interrupt Priority Register 9 (IPR9)

Figure 5-12 Interrupt Priority Register 9 (IPR9)

Base + $9

Read

PWMA_F IPL

PWMB_F IPL

PWMA_RL

IPL

PWM_RL IPL

ADCA_ZC IPL ABCB_ZC IPL

ADCA_CC

IPL

ADCB_CC

IPL

Write

RESET

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56F8346 Technical Data

Preliminary

5.6.10.1 PWM A Fault Interrupt Priority Level (PWMA_F IPL)--Bits 1514

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.10.2 PWM B Fault Interrupt Priority Level (PWMB_F IPL)--Bits 1312

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.10.3 Reload PWM A Interrupt Priority Level (PWMA_RL IPL)--

Bits 1110

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.10.4 Reload PWM B Interrupt Priority Level (PWMB_RL IPL)--Bits 98

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.10.5 ADC A Zero Crossing Interrupt Priority Level (ADCA_ZC IPL)--

Bits 76

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

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56F8346 Technical Data

Preliminary

5.6.10.6 ADC B Zero Crossing Interrupt Priority Level (ADCB_ZC IPL)--

Bits 54

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.10.7 ADC A Conversion Complete Interrupt Priority Level

(ADCA_CC IPL)--Bits 32

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.10.8 ADC B Conversion Complete Interrupt Priority Level

(ADCB_CC IPL)--Bits 10

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0
through 2. They are disabled by default.

00 = IRQ disabled (default)

01 = IRQ is priority level 0

10 = IRQ is priority level 1

11 = IRQ is priority level 2

5.6.11

Vector Base Address Register (VBA)

Figure 5-13 Vector Base Address Register (VBA)

5.6.11.1 Reserved--Bits 1513

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

Base + $A

Read

VECTOR BASE ADDRESS

Write

RESET

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56F8346 Technical Data

Preliminary

5.6.11.2 Interrupt Vector Base Address (VECTOR BASE ADDRESS)--

Bits 120

The contents of this register determine the location of the Vector Address Table. The value in this
register is used as the upper 13 bits of the interrupt Vector Address Bus (VAB[20:0]). The lower
eight bits are determined based upon the highest-priority interrupt. They are then appended onto
VBA before presenting the full VAB to the 56800E core; see

Section 5.3.1

for details.

5.6.12

Fast Interrupt 0 Match Register (FIM0)

Figure 5-14 Fast Interrupt 0 Match Register (FIM0)

5.6.12.1 Reserved--Bits 157

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.12.2 Fast Interrupt 0 Vector Number (FAST INTERRUPT 0)--Bits 60

This value determines which IRQ will be a Fast Interrupt 0. Fast interrupts vector directly to a
service routine based on values in the Fast Interrupt Vector Address registers without having to go
to a jump table first; see

Section 5.3.3

. IRQs used as fast interrupts must be set to priority level 2.

Unexpected results will occur if a fast interrupt vector is set to any other priority. Fast interrupts
automatically become the highest-priority level 2 interrupt, regardless of their location in the
interrupt table, prior to being declared as fast interrupt. Fast Interrupt 0 has priority over Fast
Interrupt 1. To determine the vector number of each IRQ, refer to

Table 4-5

5.6.13

Fast Interrupt 0 Vector Address Low Register (FIVAL0)

Figure 5-15 Fast Interrupt 0 Vector Address Low Register (FIVAL0)

5.6.13.1 Fast Interrupt 0 Vector Address Low (FIVAL0)--Bits 150

The lower 16 bits of the vector address used for Fast Interrupt 0. This register is combined with
FIVAH0 to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.

Base + $B

Read

FAST INTERRUPT 0

Write

RESET

Base + $C

Read

FAST INTERRUPT 0

VECTOR ADDRESS LOW

Write

RESET

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56F8346 Technical Data

Preliminary

5.6.14

Fast Interrupt 0 Vector Address High Register (FIVAH0)

Figure 5-16 Fast Interrupt 0 Vector Address High Register (FIVAH0)

5.6.14.1 Reserved--Bits 155

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.14.2 Fast Interrupt 0 Vector Address High (FIVAH0)--Bits 40

The upper five bits of the vector address used for Fast Interrupt 0. This register is combined with
FIVAL0 to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.

5.6.15

Fast Interrupt 1 Match Register (FIM1)

Figure 5-17 Fast Interrupt 1 Match Register (FIM1)

5.6.15.1 Reserved--Bits 157

This bit field is reserved or not implemented. It is read as 0, but cannot be modified by writing.

5.6.15.2 Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)--Bits 60

This value determines which IRQ will be a Fast Interrupt 1. Fast interrupts vector directly to a
service routine based on values in the Fast Interrupt Vector Address registers without having to go
to a jump table first; see

Section 5.3.3

. IRQs used as fast interrupts must be set to priority level 2.

Table 4-5

5.6.16

Fast Interrupt 1 Vector Address Low Register (FIVAL1)

Figure 5-18 Fast Interrupt 1 Vector Address Low Register (FIVAL1)

Base + $D

Read

FAST INTERRUPT 0

VECTOR ADDRESS HIGH

Write

RESET

Base + $E

Read

FAST INTERRUPT 1

Write

RESET

Base + $F

Read

FAST INTERRUPT 1

VECTOR ADDRESS LOW

Write

RESET

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56F8346 Technical Data

Preliminary

5.6.16.1 Fast Interrupt 1 Vector Address Low (FIVAL1)--Bits 150

The lower 16 bits of vector address are used for Fast Interrupt 1. This register is combined with
FIVAL1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.

5.6.17

Fast Interrupt 1 Vector Address High Register (FIVAH1)

Figure 5-19 Fast Interrupt 1 Vector Address High Register (FIVAH1)

5.6.17.1 Reserved--Bits 155

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.17.2 Fast Interrupt 1 Vector Address High (FIVAH1)--Bits 40

The upper five bits of the vector address are used for Fast Interrupt 1. This register is combined
with FIVAH1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.

5.6.18

IRQ Pending 0 Register (IRQP0)

Figure 5-20 IRQ Pending 0 Register (IRQP0)

5.6.18.1 IRQ Pending (PENDING)--Bits 162

This register combines with the other five to represent the pending IRQs for interrupt vector
numbers 2 through 81.

0 = IRQ pending for this vector number

1 = No IRQ pending for this vector number

5.6.18.2 Reserved--Bit 0

This bit is reserved or not implemented. It is read as 1 and cannot be modified by writing.

5.6.19

IRQ Pending 1 Register (IRQP1)

Figure 5-21 IRQ Pending 1 Register (IRQP1)

Base + $10

Read

FAST INTERRUPT 1

VECTOR ADDRESS HIGH

Write

RESET

Base + $11

Read

PENDING [16:2]

Write

RESET

$Base + $12

Read

PENDING [32:17]

Write

RESET

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56F8346 Technical Data

Preliminary

5.6.19.1 IRQ Pending (PENDING)--Bits 3217

This register combines with the other five to represent the pending IRQs for interrupt vector
numbers 2 through 81.

0 = IRQ pending for this vector number

1 = No IRQ pending for this vector number

5.6.20

IRQ Pending 2 Register (IRQP2)

Figure 5-22 IRQ Pending 2 Register (IRQP2)

5.6.20.1 IRQ Pending (PENDING)--Bits 4833

This register combines with the other five to represent the pending IRQs for interrupt vector
numbers 2 through 81.

0 = IRQ pending for this vector number

1 = No IRQ pending for this vector number

5.6.21

IRQ Pending 3 Register (IRQP3)

Figure 5-23 IRQ Pending 3 Register (IRQP3)

5.6.21.1 IRQ Pending (PENDING)--Bits 6449

This register combines with the other five to represent the pending IRQs for interrupt vector
numbers 2 through 81.

0 = IRQ pending for this vector number

1 = No IRQ pending for this vector number

5.6.22

IRQ Pending 4 Register (IRQP4)

Figure 5-24 IRQ Pending 4 Register (IRQP4)

Base + $13

Read

PENDING [48:33]

Write

RESET

Base + $14

Read

PENDING [64:49]

Write

RESET

Base + $15

Read

PENDING [80:65]

Write

RESET

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56F8346 Technical Data

Preliminary

5.6.22.1 IRQ Pending (PENDING)--Bits 8065

This register combines with the other five to represent the pending IRQs for interrupt vector
numbers 2 through 81.

0 = IRQ pending for this vector number

1 = No IRQ pending for this vector number

5.6.23

IRQ Pending 5 Register (IRQP5)

Figure 5-25 IRQ Pending Register 5 (IRQP5)

5.6.23.1 Reserved--Bits 9682

This bit field is reserved or not implemented. The bits are read as 1 and cannot be modified by
writing.

5.6.23.2 IRQ Pending (PENDING)--Bit 81

This register combines with the other five to represent the pending IRQs for interrupt vector
numbers 2 through 81.

0 = IRQ pending for this vector number

1 = No IRQ pending for this vector number

5.6.24

Reserved

--Base + 17

5.6.25

Reserved

--Base + 18

5.6.26

Reserved

--Base + 19

5.6.27

Reserved

--Base + 1A

5.6.28

Reserved

--Base + 1B

5.6.29

Reserved

--Base + 1C

Base + $16

Read

PEND-

ING

[81]

Write

RESET

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56F8346 Technical Data

Preliminary

5.6.30

ITCN Control Register (ICTL)

Figure 5-26 ITCN Control Register (ICTL)

5.6.30.1 Interrupt (INT)--Bit 15

This read-only bit reflects the state of the interrupt to the 56800E core.

0 = No interrupt is being sent to the 56800E core

1 = An interrupt is being sent to the 56800E core

5.6.30.2 Interrupt Priority Level (IPIC)--Bits 1413

These read-only bits reflect the state of the new interrupt priority level bits being presented to the
56800E core at the time the last IRQ was taken. This field is only updated when the 56800E core
jumps to a new interrupt service routine.

Note:

Nested interrupts may cause this field to be updated before the original interrupt service
routine can read it.

00 = Required nested exception priority levels are 0, 1, 2, or 3

01 = Required nested exception priority levels are 1, 2, or 3

10 = Required nested exception priority levels are 2 or 3

11 = Required nested exception priority level is 3

5.6.30.3 Vector Number - Vector Address Bus (VAB)--Bits 126

This read-only field shows the vector number (VAB[7:1]) used at the time the last IRQ was taken.
This field is only updated when the 56800E core jumps to a new interrupt service routine.

Note:

Nested interrupts may cause this field to be updated before the original interrupt service
routine can read it.

5.6.30.4 Interrupt Disable (INT_DIS)--Bit 5

This bit allows all interrupts to be disabled.

0 = Normal operation (default)

1 = All interrupts disabled

5.6.30.5 Reserved--Bit 4

This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.

5.6.30.6 IRQB State Pin (IRQB STATE)--Bit 3

This read-only bit reflects the state of the external IRQB pin.

Base + $1D

Read

INT

IPIC

VAB

INT_DIS

IRQB STATE

IRQA STATE

IRQB

EDG

IRQA

EDG

Write

RESET

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56F8346 Technical Data

Preliminary

5.6.30.7 IRQA State Pin (IRQA STATE)--Bit 2

This read-only bit reflects the state of the external IRQA pin.

5.6.30.8 IRQB Edge Pin (IRQB Edg)--Bit 1

This bit controls whether the external IRQB interrupt is edge- or level-sensitive. During Stop and
Wait modes, it is automatically level-sensitive.

0 = IRQB interrupt is a low-level sensitive (default)

1 = IRQB interrupt is falling-edge sensitive.

5.6.30.9 IRQA Edge Pin (IRQA Edg)--Bit 0

This bit controls whether the external IRQA interrupt is edge- or level-sensitive. During Stop and
Wait modes, it is automatically level-sensitive.

0 = IRQA interrupt is a low-level sensitive (default)

1 = IRQA interrupt is falling-edge sensitive.

5.7 Resets

5.7.1

Reset Handshake Timing

The ITCN provides the 56800E core with a reset vector address whenever RESET is asserted. The
reset vector will be presented until the second rising clock edge after RESET is released.

5.7.2

ITCN After Reset

After reset, all of the ITCN registers are in their default states. This means all interrupts are
disabled, except the core IRQs with fixed priorities:

Illegal Instruction

SW Interrupt 3

HW Stack Overflow

Misaligned Long Word Access

SW Interrupt 2

SW Interrupt 1

SW Interrupt 0

SW Interrupt LP

These interrupts are enabled at their fixed priority levels.

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Overview

56F8346 Technical Data

Preliminary

Part 6 System Integration Module (SIM)

6.1 Overview

The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It
controls distribution of resets and clocks and provides a number of control features. The system
integration module is responsible for the following functions:

Reset sequencing

Clock generation & distribution

Stop/Wait control

Pull-up enables for selected peripherals

System status registers

Registers for software access to the JTAG ID of the chip

Enforcing Flash security

These are discussed in more detail in the sections that follow.

6.2 Features

The SIM has the following features:

Flash security feature prevents unauthorized access to code/data contained in on-chip Flash
memory

Power-saving clock gating for peripheral

Three power modes (Run, Wait, Stop) to control power utilization

-- Stop mode shuts down the 56800E core, system clock, peripheral clock, and PLL operation

-- Stop mode entry can optionally disable PLL and Oscillator (low power vs. fast restart); must be

explicitly done

-- Wait mode shuts down the 56800E core and unnecessary system clock operation

-- Run mode supports full part operation

Controls to enable/disable the 56800E core WAIT and STOP instructions

Calculates base delay for reset extension based upon POR or RESET operations. Reset delay will
be either 3 x 32 clocks (phased release of reset) for reset, except for POR, which is 2

clock cycles.

Controls reset sequencing after reset

Software-initiated reset

Four 16-bit registers reset only by a Power-On Reset usable for general-purpose software control

System Control Register

Registers for software access to the JTAG ID of the chip

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56F8346 Technical Data

Preliminary

6.3 Operating Modes

Since the SIM is responsible for distributing clocks and resets across the chip, it must understand
the various chip operating modes and take appropriate action. These are:

Reset Mode, which has two submodes:

-- POR and RESET operation

The 56800E core and all peripherals are reset. This occurs when the internal POR is asserted or
the RESET pin is asserted.

-- COP reset and software reset operation

The 56800E core and all peripherals are reset. The MA bit within the OMR is not changed. This
allows the software to determine the boot mode (internal or external boot) to be used on the next
reset.

Run Mode
This is the primary mode of operation for this device. In this mode, the 56800E controls chip
operation.

Debug Mode
The 56800E is controlled via JTAG/EOnCE when in debug mode. All peripherals, except the COP
and PWMs, continue to run. COP is disabled and PWM outputs are optionally switched off to
disable any motor from being driven; see the PWM chapter in the 56F8300 Peripheral User
Manual for details.

Wait Mode
In Wait mode, the core clock and memory clocks are disabled. Optionally, the COP can be stopped.
Similarly, it is an option to switch off PWM outputs to disable any motor from being driven. All
other peripherals continue to run.

Stop Mode
When in Stop mode, the 56800E core, memory, and most peripheral clocks are shut down.
Optionally, the COP and CAN can be stopped. For lowest power consumption in Stop mode, the
PLL can be shut down. This must be done explicitly before entering Stop mode, since there is no
automatic mechanism for this. The CAN (along with any non-gated interrupt) is capable of waking
the chip up from Stop mode, but is not fully functional in Stop mode.

6.4 Operation Mode Register

Figure 6-1 OMR

See

Section 4.2

for detailed information on how the Operating Mode Register (OMR) MA and MB

bits operate in this device. For additional information on the EX bit, see

Section 4.4

. For all other

bits, see the DSP56800E Reference Manual.

Note:

The OMR is not a Memory Map register; it is directly accessible in code through the acronym
OMR.

Bit

Type

R/W

RESET

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56F8346 Technical Data

Preliminary

6.5 Register Descriptions

Table 6-1 SIM Registers (SIM_BASE = $00F350)

Address Offset

Address Acronym

Register Name

Section Location

Base + $0

SIM_CONTROL

Control Register

6.5.1

Base + $1

SIM_RSTSTS

Reset Status Register

6.5.2

Base + $2

SIM_SCR0

Software Control Register 0

6.5.3

Base + $3

SIM_SCR1

Software Control Register 1

6.5.3

Base + $4

SIM_SCR2

Software Control Register 2

6.5.3

Base + $5

SIM_SCR3

Software Control Register 3

6.5.3

Base + $6

SIM_MSH_ID

Most Significant Half of JTAG ID

6.5.4

Base + $7

SIM_LSH_ID

Least Significant Half of JTAG ID

6.5.5

Base + $8

SIM_PUDR

Pull-up Disable Register

6.5.6

Reserved

Base + $A

SIM_CLKOSR

CLKO Select Register

6.5.7

Base + $B

SIM_GPS

GPIO Peripheral Select Register

6.5.7

Base + $C

SIM_PCE

Peripheral Clock Enable Register

6.5.8

Base + $D

SIM_ISALH

I/O Short Address Location High Register

6.5.9

Base + $E

SIM_ISALL

I/O Short Address Location Low Register

6.5.10

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100

56F8346 Technical Data

Preliminary

6.5.1

SIM Control Register (SIM_CONTROL)

Figure 6-3 SIM Control Register (SIM_CONTROL)

6.5.1.1

Reserved--Bits 156

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.5.1.2

OnCE Enable (OnCE EBL)--Bit 5

0 = OnCE clock to 56800E core enabled when core TAP is enabled

1 = OnCE clock to 56800E core is always enabled

6.5.1.3

Software Reset (SWRST)--Bit 4

This bit is always read as 0. Writing a 1 to this field will cause the part to reset.

Add.

Offset

Register

Name

SIM_

CONTROL

ONCE

EBL

RST

STOP_

DISABLE

WAIT_

DISABLE

SIM_

RSTSTS

SWR

COPR EXTR

POR

SIM_SCR0

FIELD

SIM_SCR1

FIELD

SIM_SCR2

FIELD

SIM_SCR3

FIELD

SIM_MSH_

SIM_LSH_ID

SIM_PUDR

PWMA

CAN

EMI_

MODE

RESET

IRQ

XBOOT PWMB

PWMA

CTRL

JTAG

Reserved

SIM_

CLKOSR

A23

A22

A21

A20

CLKDIS

CLKOSEL

SIM_GPS

SIM_PCE

EMI

ADCB

ADCA

CAN

DEC1

DEC0

TMRD TMRC

TMRB

TMRA

SCI1

SCI0

SPI1

SPI0

PWM

SIM_ISALH

ISAL[23:22]

SIM_ISALL

ISAL[21:6]

= Reserved

Figure 6-2 SIM Register Map Summary

Base + $0

Read

ONCE

EBL

RST

STOP_

DISABLE

WAIT_

DISABLE

Write

RESET

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56F8346 Technical Data

101

Preliminary

6.5.1.4

Stop Disable (STOP_DISABLE)--Bits 32

00 - STOP mode will be entered when the 56800E core executes a STOP instruction

01 - The 56800E STOP instruction will not cause entry into Stop mode; STOP_DISABLE can be
reprogrammed in the future

10 - The 56800E STOP instruction will not cause entry into Stop mode; STOP_DISABLE can then
only be changed by resetting the device

11 - Same operation as 10

6.5.1.5

Wait Disable (WAIT_DISABLE)--Bits 10

00 - WAIT mode will be entered when the 56800E core executes a WAIT instruction

01 - The 56800E WAIT instruction will not cause entry into Wait mode; WAIT_DISABLE can be
reprogrammed in the future

10 - The 56800E WAIT instruction will not cause entry into Wait mode; WAIT_DISABLE can then
only be changed by resetting the device

11 - Same operation as 10

6.5.2

SIM Reset Status Register (SIM_RSTSTS)

Bits in this register are set upon any system reset and are initialized only by a Power-On Reset
(POR). A reset (other than POR) will only set bits in the register; bits are not cleared. Only software
should clear this register.

Figure 6-4 SIM Reset Status Register (SIM_RSTSTS)

6.5.2.1

Reserved--Bits 156

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.5.2.2

Software Reset (SWR)--Bit 5

When 1, this bit indicates that the previous reset occurred as a result of a software reset (write to
SW RST bit in the SIM_CONTROL register). This bit will be cleared by any hardware reset or by
software. Writing a 0 to this bit position will set the bit, while writing a 1 to the bit will clear it.

6.5.2.3

COP Reset (COPR)--Bit 4

When 1, the COPR bit indicates the Computer Operating Properly (COP) timer-generated reset has
occurred. This bit will be cleared by a Power-On Reset or by software. Writing a 0 to this bit
position will set the bit, while writing a 1 to the bit will clear it.

Base + $1

Read

SWR

COPR

EXTR

POR

Write

RESET

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102

56F8346 Technical Data

Preliminary

6.5.2.4

External Reset (EXTR)--Bit 3

If 1, the EXTR bit indicates an external system reset has occurred. This bit will be cleared by a
Power-On Reset or by software. Writing a 0 to this bit position will set the bit, while writing a 1 to
the bit position will clear it. Basically, when the EXTR bit is 1, the previous system reset was
caused by the external RESET pin being asserted low.

6.5.2.5

Power-On Reset (POR)--Bit 2

When 1, the POR bit indicates a Power-On Reset occurred some time in the past. This bit can be
cleared only by software or by another type of reset. Writing a 0 to this bit will set the bit, while
writing a 1 to the bit position will clear the bit. In summary, if the bit is 1, the previous system reset
was due to a Power-On Reset.

6.5.2.6

Reserved--Bits 10

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.5.3

SIM Software Control Registers (SIM_SCR0, SIM_SCR1,
SIM_SCR2, and SIM_SCR3)

Only SIM_SCR0 is shown below. SIM_SCR1, SIM_SCR2, and SIM_SCR3 are identical in
functionality.

Figure 6-5 SIM Software Control Register 0 (SIM_SCR0)

6.5.3.1

Software Control Data 1 (FIELD)--Bits 150

This register is reset only by the Power-On Reset (POR). It has no part-specific functionality and
is intended for use by a software developer to contain data that will be unaffected by the other reset
sources (RESET pin, software reset, and COP reset).

6.5.4

Most Significant Half of JTAG ID (SIM_MSH_ID)

This read-only register displays the most significant half of the JTAG ID for the chip. This register
reads $01F4.

Figure 6-6 Most Significant Half of JTAG ID (SIM_MSH_ID)

Base + $2

Read

FIELD

Write

POR

Base + $6

Read

Write

RESET

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56F8346 Technical Data

103

Preliminary

6.5.5

Least Significant Half of JTAG ID (SIM_LSH_ID)

This read-only register displays the least significant half of the JTAG ID for the chip. This register
reads $401D.

Figure 6-7 Least Significant Half of JTAG ID (SIM_LSH_ID)

6.5.6

SIM Pull-up Disable Register (SIM_PUDR)

Most of the pins on the chip have on-chip pull-up resistors. Pins which can operate as GPIO can
have these resistors disabled via the GPIO function. Non-GPIO pins can have their pull-ups
disabled by setting the appropriate bit in this register. Disabling pull-ups is done on a
peripheral-by-peripheral basis (for pins not muxed with GPIO). Each bit in the register (see

Figure 6-8

) corresponds to a functional group of pins. See

Table 2-2

to identify which pins can

deactivate the internal pull-up resistor.

Figure 6-8 SIM Pull-up Disable Register (SIM_PUDR)

6.5.6.1

Reserved--Bit 15

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.5.6.2

PWMA1--Bit 14

This bit controls the pull-up resistors on the FAULTA3 pin.

6.5.6.3

CAN--Bit 13

This bit controls the pull-up resistors on the CAN_RX pin.

6.5.6.4

EMI_MODE--Bit 12

This bit controls the pull-up resistors on the EMI_MODE pin.

6.5.6.5

RESET--Bit 11

This bit controls the pull-up resistors on the RESET pin.

6.5.6.6

IRQ--Bit 10

This bit controls the pull-up resistors on the IRQA and IRQB pins.

Base + $7

Read

Write

RESET

Base + $8

Read

PWMA1

CAN

EMI_

MODE

RESET

IRQ

XBOOT

PWMB

PWMA0

CTRL

JTAG

Write

RESET

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104

56F8346 Technical Data

Preliminary

6.5.6.7

XBOOT--Bit 9

This bit controls the pull-up resistors on the EXTBOOT pin.

6.5.6.8

PWMB--Bit 8

This bit controls the pull-up resistors on the FAULTB0, FAULTB1, FAULTB2, and FAULTB3
pins.

6.5.6.9

PWMA0--Bit 7

This bit controls the pull-up resistors on the FAULTA0, FAULTA1, and FAULTA2 pins.

6.5.6.10 Reserved--Bit 6

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.5.6.11 CTRL--Bit 5

This bit controls the pull-up resistors on the WR and RD pins.

6.5.6.12 Reserved--Bit 4

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.5.6.13 JTAG--Bit 3

This bit controls the pull-up resistors on the TRST, TMS and TDI pins.

6.5.6.14 Reserved--Bits 2 - 0

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.5.7

CLKO Select Register (SIM_CLKOSR)

The CLKO select register can be used to multiplex out any one of the clocks generated inside the
clock generation and SIM modules. The default value is SYS_CLK. All other clocks primarily
muxed out are for test purposes only, and are subject to significant unspecified latencies at high
frequencies.

The upper four bits of the GPIO B register can function as GPIOA23 through A20, or as additional
clock output signals. GPIO has priority and is enabled/disabled via the GPIOB_PER. If GPIO
B[7:4] are programmed to operate as peripheral outputs, then the choice between A23 through A20
and additional clock outputs is done here in the CLKOSR. The default state is for the peripheral
function of GPIO B[7:4] to be programmed as A23 through A20. This can be changed by altering
A23 through A20, as shown in

Figure 6-9

Figure 6-9 CLKO Select Register (SIM_CLKOSR)

Base + $A

Read

A23

A22

A21

A20

CLK

DIS

CLKOSEL

Write

RESET

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56F8346 Technical Data

105

Preliminary

6.5.7.1

Reserved--Bits 1510

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.5.7.2

Alternate GPIO_B Peripheral Function Select for A23 (A23)--Bit 9

0 = Peripheral output function of GPIO B[7] is defined to be A[23]

1 = Peripheral output function of GPIO B[7] is defined to be the oscillator clock (MSTR_OSC, see

Figure 3-4

)

6.5.7.3

Alternate GPIO_B Peripheral Function Select for A22 (A22)--Bit 8

0 = Peripheral output function of GPIO B[6] is defined to be A[22]

1 = Peripheral output function of GPIO B[6] is defined to be SYS_CLK2

6.5.7.4

Alternate GPIO_B Peripheral Function Select for A21 (A21)--Bit 7

0 = Peripheral output function of GPIO B[5] is defined to be A[21]

1 = Peripheral output function of GPIO B[5] is defined to be SYS_CLK

6.5.7.5

Alternate GPIO_B Peripheral Function Select for A20 (A20)--Bit 6

0 = Peripheral output function of GPIO B[4] is defined to be A[20]

1 = Peripheral output function of GPIO B[4] is defined to be the prescaler clock (FREF, see

Figure 3-4

)

6.5.7.6

Clockout Disable (CLKDIS)--Bit 5

0 = CLKOUT output is enabled and will output the signal indicated by CLKOSEL

1 = CLKOUT is tri-stated

6.5.7.7

CLockout Select (CLKOSEL)--Bits 40

Selects clock to be muxed out on the CLKO pin.

00000 = SYS_CLK (from OCCS - DEFAULT)

00001 = Reserved for factory test--56800E clock

00010 = Reserved for factory test--XRAM clock

00011 = Reserved for factory test--PFLASH odd clock

00100 = Reserved for factory test--PFLASH even clock

00101 = Reserved for factory test--BFLASH clock

00110 = Reserved for factory test--DFLASH clock

00111 = Oscillator output

01000 = F

out

(from OCCS)

01001 = Reserved for factory test--IPB clock

01010 = Reserved for factory test--Feedback (from OCCS, this is path to PLL)

01011 = Reserved for factory test--Prescaler clock (from OCCS)

01100 = Reserved for factory test--Postscaler clock (from OCCS)

01101 = Reserved for factory test--SYS_CLK2 (from OCCS)

01110 = Reserved for factory test--SYS_CLK_DIV2

01111 = Reserved for factory test--SYS_CLK_D

10000 = ADCA clock

10001 = ADCB clock

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106

56F8346 Technical Data

Preliminary

6.5.8

GPIO Peripheral Select Register (SIM_GPS)

The GPIO Peripheral Select register can be used to multiplex out any one of the three alternate
peripherals for GPIOC. The default peripheral is Quad Decoder 1 and Quad Timer B; these
peripherals work together.

The four I/O pins associated with GPIO C can function as GPIO, Quad Decoder 1/Quad Timer B,
or as SPI 1 signals. GPIO is not the default and is enabled/disabled via the GPIOC_PER, as shown
in

Figure 6-10

and

Table 6-2

. When GPIO C[3:0] are programmed to operate as peripheral I/O,

then the choice between decoder/timer and SPI inputs/outputs is made in the SIM_GPS register and
in conjunction with the Quad Timer Status and Control Registers (SCR). The default state is for
the peripheral function of GPIO C[3:0] to be programmed as decoder functions. This can be
changed by altering the appropriate controls in the indicated registers.

Figure 6-10 Overall Control of Pads Using SIM_GPS Control

GPIOC_PER Register

GPIO Controlled

I/O

Pad Control

SIM_

GPS Register

Quad Timer Controlled

SPI Controlled

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56F8346 Technical Data

107

Preliminary

Figure 6-11 GPIO Peripheral Select Register (SIM_GPS)

6.5.8.1

Reserved--Bits 154

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.5.8.2

GPIO C3 (C3)--Bit 3

This bit selects the alternate function for GPIOC3.

0 = HOME1/TB3 (default - see "Switch Matrix Mode" bits of the Quad Decoder DECCR register
in the 56F8300 Peripheral User Manual)

1 = SS1

6.5.8.3

GPIO C2 (C2)--Bit 2

This bit selects the alternate function for GPIOC2.

0 = INDEX1/TB2 (default)

1 = MISO1

Table 6-2 Control of Pads Using SIM_GPS Control

This applies to the four pins that serve as Quad Decoder / Quad Timer / SPI / GPIOC functions. A separate set of control

bits is used for each pin.

Pin Function

Control Registers

Comments

GPIOC_PER

GPIOC_

DTR

SCR Re

i
s

t
e

OEN

i
ts

GPIO Input

GPIO Output

Quad Timer Input /
Quad Decoder
Input

Reset configuration

See the "Switch Matrix for Inputs to the Timer"
table in the 56F8300 Peripheral User Manual
for the definition of the timer inputs based on
the Quad Decoder Mode configuration.

Quad Timer
Output / Quad

Decoder Input

Quad Decoder pins are always inputs and function in conjunction with the Quad Timer pins.

SPI input

See SPI controls for determining the direction
of each of the SPI pins.

SPI output

Base + $B

Read

Write

RESET

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108

56F8346 Technical Data

Preliminary

6.5.8.4

GPIO C1 (C1)--Bit 1

This bit selects the alternate function for GPIOC1.

0 = PHASEB1/TB1 (default)

1 = MOSI1

6.5.8.5

GPIO C0 (C0)--Bit 0

This bit selects the alternate function for GPIOC0.

0 = PHASEA1/TB0 (default)

1 = SCLK1

6.5.9

Peripheral Clock Enable Register (SIM_PCE)

The Peripheral Clock Enable register is used to enable or disable clocks to the peripherals as a
power savings feature. The clocks can be individually controlled for each peripheral on the chip.

Figure 6-12 Peripheral Clock Enable Register (SIM_PCE)

6.5.9.1

External Memory Interface Enable (EMI)--Bit 15

Each bit controls clocks to the indicated peripheral.

1 = Clocks are enabled

0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.2

Analog-to-Digital Converter B Enable (ADCB)--Bit 14

Each bit controls clocks to the indicated peripheral.

1 = Clocks are enabled

0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.3

Analog-to-Digital Converter A Enable (ADCA)--Bit 13

Each bit controls clocks to the indicated peripheral.

1 = Clocks are enabled

0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.4

FlexCAN Enable (CAN)--Bit 12

Each bit controls clocks to the indicated peripheral.

1 = Clocks are enabled

0 = The clock is not provided to the peripheral (the peripheral is disabled)

Base + $C

Read

EMI

ADCB ADCA

CAN

DEC1

DEC0

TMRD TMRC

TMRB

TMRA

SCI 1

SCI 0

SPI 1

SPI 0

PWMB

PWMA

Write

RESET

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56F8346 Technical Data

109

Preliminary

6.5.9.5

Decoder 1 Enable (DEC1)--Bit 11

Each bit controls clocks to the indicated peripheral.

1 = Clocks are enabled

0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.6

Decoder 0 Enable (DEC0)--Bit 10

Each bit controls clocks to the indicated peripheral.

1 = Clocks are enabled

0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.7

Quad Timer D Enable (TMRD)--Bit 9

Each bit controls clocks to the indicated peripheral.

1 = Clocks are enabled

0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.8

Quad Timer C Enable (TMRC)--Bit 8

Each bit controls clocks to the indicated peripheral.

1 = Clocks are enabled

0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.9

Quad Timer B Enable (TMRB)--Bit 7

Each bit controls clocks to the indicated peripheral.

1 = Clocks are enabled

0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.10 Quad Timer A Enable (TMRA)--Bit 6

Each bit controls clocks to the indicated peripheral.

1 = Clocks are enabled

0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.11 Serial Communications Interface 1 Enable (SCI1)--Bit 5

Each bit controls clocks to the indicated peripheral.

1 = Clocks are enabled

0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.12 Serial Communications Interface 0 Enable (SCI0)--Bit 4

Each bit controls clocks to the indicated peripheral.

1 = Clocks are enabled

0 = The clock is not provided to the peripheral (the peripheral is disabled)

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110

56F8346 Technical Data

Preliminary

6.5.9.13 Serial Peripheral Interface 1 Enable (SPI1)--Bit 3

Each bit controls clocks to the indicated peripheral.

1 = Clocks are enabled

0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.14 Serial Peripheral Interface 0 Enable (SPI0)--Bit 2

Each bit controls clocks to the indicated peripheral.

1 = Clocks are enabled

0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.15 Pulse Width Modulator B Enable (PWMB)--1

Each bit controls clocks to the indicated peripheral.

1 = Clocks are enabled

0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.16 Pulse Width Modulator A Enable (PWMA)--0

Each bit controls clocks to the indicated peripheral.

1 = Clocks are enabled

0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.10

I/O Short Address Location Register (SIM_ISALH and
SIM_ISALL)

The I/O Short Address Location registers are used to specify the memory referenced via the I/O
short address mode. The I/O short address mode allows the instruction to specify the lower six bits
of address; the upper address bits are not directly controllable. This register set allows limited
control of the full address, as shown in

Figure 6-13

Note:

If this register is set to something other than the top of memory (EOnCE register space) and
the EX bit in the OMR is set to 1, the JTAG port cannot access the on-chip EOnCE registers,
and debug functions will be affected.

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56F8346 Technical Data

111

Preliminary

Figure 6-13 I/O Short Address Determination

With this register set, an interrupt driver can set the SIM_ISALL register pair to point to its
peripheral registers and then use the I/O Short addressing mode to reference them. The ISR should
restore this register to its previous contents prior to returning from interrupt.

Note:

The default value of this register set points to the EOnCE registers.

Note:

The pipeline delay between setting this register set and using short I/O addressing with the
new value is three cycles.

Figure 6-14 I/O Short Address Location High Register (SIM_ISALH)

6.5.10.1 Input/Output Short Address Low (ISAL[23:22])--Bit 10

This field represents the upper two address bits of the "hard coded" I/O short address.

Figure 6-15 I/O Short Address Location Low Register (SIM_ISALL)

6.5.10.2 Input/Output Short Address Low (ISAL[21:6])--Bit 150

This field represents the lower 16 address bits of the "hard coded" I/O short address.

Base + $D

Read

ISAL[23:22]

Write

RESET

Base + $E

Read

ISAL[21:6]

Write

RESET

Instruction Portion

Hard Coded" Address Portion

6 Bits from I/O Short Address Mode Instruction

16 Bits from SIM_ISALL Register

2 bits from SIM_ISALH Register

Full 24-Bit for Short I/O Address

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112

56F8346 Technical Data

Preliminary

6.6 Clock Generation Overview

The SIM uses an internal master clock from the OCCS (CLKGEN) module to produce the
peripheral and system (core and memory) clocks. The maximum master clock frequency is
120MHz. Peripheral and system clocks are generated at half the master clock frequency and
therefore at a maximum 60MHz. The SIM provides power modes (Stop, Wait) and clock enables
(SIM_PCE register, CLK_DIS, ONCE_EBL) to control which clocks are in operation. The OCCS,
power modes, and clock enables provide a flexible means to manage power consumption.

Power utilization can be minimized in several ways. In the OCCS, crystal oscillator, and PLL may
be shut down when not in use. When the PLL is in use, its prescaler and postscaler can be used to
limit PLL and master clock frequency. Power modes permit system and/or peripheral clocks to be
disabled when unused. Clock enables provide the means to disable individual clocks. Some
peripherals provide further controls to disable unused subfunctions. Refer to the

Part 3, On-Chip

Clock Synthesis (OCCS)

and the 56F8300 Peripheral User Manual for further details.

6.7 Power-Down Modes Overview

The 56F8346 operates in one of three power-down modes, as shown in

Table 6-3

All peripherals, except the COP/watchdog timer, run off the IPBus clock frequency, which is the
same as the main processor frequency in this architecture. The maximum frequency of operation
is SYS_CLK = 60MHz.

Table 6-3 Clock Operation in Power-Down Modes

Mode

Core Clocks

Peripheral Clocks

Description

Run

Active

Device is fully functional

Wait

Core and memory
clocks disabled

Active

Peripherals are active and can product interrupts if they
have not been masked off.
Interrupts will cause the core to come out of its
suspended state and resume normal operation.
Typically used for power-conscious applications.

Stop

System clocks continue to be generated in
the SIM, but most are gated prior to
reaching memory, core and peripherals.

The only possible recoveries from Stop mode are:
1. CAN traffic (1st message will be lost)
2. Non-clocked interrupts
3. COP reset
4. External reset
5. Power-on reset

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Stop and Wait Mode Disable Function

56F8346 Technical Data

113

Preliminary

6.8 Stop and Wait Mode Disable Function

Figure 6-16 Internal Stop Disable Circuit

The 56800E core contains both STOP and WAIT instructions. Both put the CPU to sleep. For
lowest power consumption in Stop mode, the PLL can be shut down. This must be done explicitly
before entering Stop mode, since there is no automatic mechanism for this. When the PLL is shut
down, the 56800E system clock must be set equal to the prescaler output.

Some applications require the 56800E STOP and WAIT instructions be disabled. To disable those
instructions, write to the SIM control register (SIM_CONTROL), described in

Section 6.5.1

. This

procedure can be on either a permanent or temporary basis. Permanently assigned applications last
only until their next reset.

6.9 Resets

The SIM supports four sources of reset. The two asynchronous sources are the external RESET pin
and the Power-On Reset (POR). The two synchronous sources are the software reset, which is
generated within the SIM itself by writing to the SIM_CONTROL register, and the COP reset.

Reset begins with the assertion of any of the reset sources. Release of reset to various blocks is
sequenced to permit proper operation of the device. A POR reset is first extended for 2

clock

cycles to permit stabilization of the clock source, followed by a 32 clock window in which SIM
clocking is initiated. It is then followed by a 32 clock window in which peripherals are released to
implement Flash security, and, finally, followed by a 32 clock window in which the core is
initialized. After completion of the described reset sequence, application code will begin
execution.

Resets may be asserted asynchronously, but they are always released internally on a rising edge of
the system clock.

D-FLOP

56800E

STOP_DIS

Permanent
Disable

Reprogrammable Disable

Clock
Select

RESET

Note: Wait disable circuit is similar

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114

56F8346 Technical Data

Preliminary

Part 7 Security Features

The 56F8346 offers security features intended to prevent unauthorized users from reading the
contents of the Flash Memory (FM) array. The 56F8346's Flash security consists of several
hardware interlocks that block the means by which an unauthorized user could gain access to the
Flash array.

However, part of the security must lie with the user's code. An extreme example would be user's
code that dumps the contents of the internal program, as this code would defeat the purpose of
security. At the same time, the user may also wish to put a "backdoor" in his program. As an
example, the user downloads a security key through the SCI, allowing access to a programming
routine that updates parameters stored in another section of the Flash.

7.1 Operation with Security Enabled

Once the user has programmed the Flash with his application code, the 56F8346 can be secured by
programming the security bytes located in the FM configuration field, which occupies a portion of
the FM array. These non-volatile bytes will keep the part secured through reset and through
power-down of the device. Only two bytes within this field are used to enable or disable security.
Refer to the Flash Memory section in the 56F8300 Peripheral User Manual for the state of the
security bytes and the resulting state of security. When Flash security mode is enabled in
accordance with the method described in the Flash Memory module specification, the 56F8346
will disable external P-space accesses restricting code execution to internal memory, disable
EXTBOOT=1 mode, and disable the core EOnCE debug capabilities. Normal program execution
is otherwise unaffected.

7.2 Flash Access Blocking Mechanisms

The 56F8346 has several operating functional and test modes. Effective Flash security must
address operating mode selection and anticipate modes in which the on-chip Flash can be
compromised and read without explicit user permission. Methods to block these are outlined in the
next subsections.

7.2.1

Forced Operating Mode Selection

At boot time, the SIM determines in which functional modes the 56F8346 will operate. These are:

Internal Boot Mode

External Boot Mode

Secure Mode

When Flash security is enabled as described in the Flash Memory module specification, the
56F8346 will boot in internal boot mode, disable all access to external P-space, and start executing
code from the Boot Flash at address 0x02_0000.

This security affords protection only to applications in which the 56F8346 operates in internal
Flash security mode. Therefore, the security feature cannot be used unless all executing code
resides on-chip.

When security is enabled, any attempt to override the default internal operating mode by asserting
the EXTBOOT pin in conjunction with reset will be ignored.

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Flash Access Blocking Mechanisms

56F8346 Technical Data

115

Preliminary

7.2.2

Disabling EOnCE Access

On-chip Flash can be read by issuing commands across the EOnCE port, which is the debug
interface for the 56800E core. The TRST, TCLK, TMS, TDO, and TDI pins comprise a JTAG
interface onto which the EOnCE port functionality is mapped. When the 56F8346 boots, the
chip-level JTAG TAP (Test Access Port) is active and provides the chip's boundary scan capability
and access to the ID register.

Proper implementation of Flash security requires that no access to the EOnCE port is provided
when security is enabled. The 56800E core has an input which disables reading of internal memory
via the JTAG/EOnCE. The FM sets this input at reset to a value determined by the contents of the
FM security bytes.

7.2.3

Flash LOCKOUT_RECOVERY

If a user inadvertently enables security on the 56F8346, a lockout recovery mechanism is provided
which allows the complete erasure of the internal Flash contents, including the configuration field,
and thus disables security (the protection register is cleared). This does not compromise security,
as the entire contents of the user's secured code stored in Flash are erased before security is
disabled on the 56F8346 on the next reset or power-up sequence. To start the lockout recovery
sequence, the JTAG public instruction (LOCKOUT_RECOVERY) must first be shifted into the
chip-level TAP controller's instruction register.

The LOCKOUT_RECOVERY instruction has an associated 7-bit Data Register (DR) that is used
to control the clock divider circuit within the FM module. This divider, FM_CLKDIV[6:0], is used
to control the period of the clock used for timed events in the FM erase algorithm. This register
must be set with appropriate values before the lockout sequence can begin. Refer to the JTAG
section of the 56F8300 Peripheral User Manual for more details on setting this register value.

The value of the JTAG FM_CLKDIV[6:0] will replace the value of the FM register FMCLKD that
divides down the system clock for timed events, as illustrated in

Figure 7-1

. FM_CLKDIV[6] will

map to the PRDIV8 bit, and FM_CLKDIV[5:0] will map to the DIV[5:0] bits. The combination of
PRDIV8 and DIV must divide the FM input clock down to a frequency of 150kHz-200kHz. The
"Writing the FMCLKD Register" section in the Flash Memory chapter of the 56F8300
Peripheral User Manual gives specific equations for calculating the correct values.

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116

56F8346 Technical Data

Preliminary

Figure 7-1 JTAG to FM Connection for LOCKOUT_RECOVERY

Two examples of FM_CLKDIV calculations follow.

EXAMPLE 1: If the system clock is the 8MHz crystal frequency because the PLL has not been
set up, the input clock will be below 12.8MHz, so PRDIV8 = FM_CLKDIV[6] = 0. Using the
following equation yields a DIV value of 19 for a clock of 200kHz, and a DIV value of 20 for a
clock of 190kHz. This translates into an FM_CLKDIV[6:0] value of $13 or $14, respectively.

EXAMPLE 2: In this example, the system clock has been set up with a value of 32MHz, making
the FM input clock 16MHz. Because that is greater than 12.8MHz, PRDIV8 = FM_CLKDIV[6] =
1. Using the following equation yields a DIV value of 9 for a clock of 200kHz, and a DIV value of
10 for a clock of 181kHz. This translates to an FM_CLKDIV[6:0] value of $49 or $4A,
respectively.

SYS_CLK

JTAG

FMCLKD

DIVIDER

FM_CLKDIV

FM_ERASE

Flash Memory

clock

input

SYS_CLK

(2)

)

(

(DIV + 1)

150[kHz]

200[kHz]

)

(

(DIV + 1)

150[kHz]

200[kHz]

SYS_CLK

(2)

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Flash Access Blocking Mechanisms

56F8346 Technical Data

117

Preliminary

Once the LOCKOUT_RECOVERY instruction has been shifted into the instruction register, the
clock divider value must be shifted into the corresponding 7-bit data register. After the data register
has been updated, the user must transition the TAP controller into the RUN-TEST/IDLE state for
the lockout sequence to commence. The controller must remain in this state until the erase
sequence has completed. For details, see the JTAG Section in the 56F8300 Peripheral User
Manual.

Note:

Once the lockout recovery sequence has completed, the user must reset both the JTAG TAP
controller (by asserting TRST) and the 56F8346 (by asserting external chip reset) to return to
normal unsecured operation.

7.2.4

Product Analysis

The recommended method of unsecuring a programmed 56F8346 for product analysis of field
failures is via the backdoor key access. The customer would need to supply Motorola with the
backdoor key and the protocol to access the backdoor routine in the Flash. Additionally, the
KEYEN bit that allows backdoor key access must be set.

An alternative method for performing analysis on a secured hybrid controller would be to
mass-erase and reprogram the Flash with the original code, but modify the security bytes.

To insure that a customer does not inadvertently lock himself out of the 56F8346 during
programming, it is recommended that he program the backdoor access key first, his application
code second, and the security bytes within the FM configuration field last.

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118

56F8346 Technical Data

Preliminary

Part 8 General Purpose Input/Output (GPIO)

8.1 Introduction

This section is intended to supplement the GPIO information found in the 56F8300 Peripheral
User Manual and contains only chip-specific information. This information supercedes the
generic information in the 56F8300 Peripheral User Manual.

8.2 Configuration

There are six GPIO ports defined on the 56F8346. The width of each port and the associated
peripheral function is shown in

Table 8-1

. The specific mapping of GPIO port pins is shown in

Table 8-2

Table 8-1 GPIO Ports Configuration

GPIO

Port

Width

Available

Pins in

56F8346

Peripheral Function

Reset Function

14 pins - EMI Address pins

EMI Address

1 pin - EMI Address pin
7 pins - EMI Address pins - Not available in this package

EMI Address
N/A

4 pins -DEC1 / TMRB / SPI1
4 pins -DEC0 / TMRA
3 pins -PWMA current sense

DEC1 / TMRB
DEC0 / TMRA
PWMA current sense

2 pins - EMI CSn
4 pins - EMI CSn - Not available in this package
2 pins - SCI1
2 pins - EMI CSn
3 pins -PWMB current sense

EMI Chip Selects
N/A
SCI1
EMI Chip Selects
PWMB current sense

2 pins - SCI0
2 pins - EMI Address pins
4 pins - SPI0
1 pin - TMRC
1 pin - TMRC
2 pins - TMRD
2 pins - TMRD

SCI0
EMI Address
SPI0
TMRC
N/A
TMRD
N/A

16 pins - EMI Data

EMI Data

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120

56F8346 Technical Data

Preliminary

GPIOC

Peripheral

PhaseA1 / TB0 / SCLK1

Peripheral

PhaseB1 / TB1 / MOSI1

Peripheral

Index1 / TB2 / MISO1

Peripheral

Home1 / TB3 / SS1

Peripheral

PHASEA0 / TA0

139

Peripheral

PHASEB0 / TA1

140

Peripheral

Index0 / TA2

141

Peripheral

Home0 / TA3

142

Peripheral

ISA0

113

Peripheral

ISA1

114

Peripheral

ISA2

115

GPIOD

GPIO

CS2

GPIO

CS3

N/A

Peripheral

TXD1

Peripheral

RXD1

Peripheral

PS / CS0

Peripheral

DS / CS1

Peripheral

ISB0

Peripheral

ISB1

Peripheral

ISB2

Table 8-2 GPIO External Signals Map (Continued)

Pins in shaded rows are not available in 56F8346

GPIO Port

GPIO Bit

Reset

Function

Functional Signal

Package Pin

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122

56F8346 Technical Data

Preliminary

8.3 Memory Maps

The width of the GPIO port defines how many bits are implemented in each of the GPIO registers.
Based on this and the default function of each of the GPIO pins, the reset values of the GPIOx_PUR
and GPIOx_PER registers change from port to port. Tables

4-29

through

4-34

define the actual

reset values of these registers for the 56F8346.

Part 9 Joint Test Action Group (JTAG)

9.1 56F8346 Information

Please contact your Motorola marketing representative for device/package-specific BSDL
information.

GPIOF

Peripheral

D10

Peripheral

D11

133

Peripheral

D12

134

Peripheral

D13

135

Peripheral

D14

136

Peripheral

D15

137

Peripheral

See

Section 6.5.8

to determine how to select peripherals from this set; DEC1 is the selected peripheral at reset .

Table 8-2 GPIO External Signals Map (Continued)

Pins in shaded rows are not available in 56F8346

GPIO Port

GPIO Bit

Reset

Function

Functional Signal

Package Pin

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General Characteristics

56F8346 Technical Data

123

Preliminary

Part 10 Specifications

10.1 General Characteristics

The 56F8346 is fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs.
The term "5V-tolerant" refers to the capability of an I/O pin, built on a 3.3V-compatible process
technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a
mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both
3.3V- and 5V-compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a
maximum voltage of 3.3V

10% during normal operation without causing damage). This

5V-tolerant capability therefore offers the power savings of 3.3V I/O levels combined with the
ability to receive 5V levels without damage.

Absolute maximum ratings in

Table 10-1

are stress ratings only, and functional operation at the

maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause
permanent damage to the device.

Note:

All specifications meet both Automotive and Industrial requirements unless individual
specifications are listed.

CAUTION

This device contains protective circuitry to guard
against damage due to high static voltage or electrical
fields. However, normal precautions are advised to
avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit.
Reliability of operation is enhanced if unused inputs are
tied to an appropriate voltage level.

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124

56F8346 Technical Data

Preliminary

Note: The overall life of this device may be reduced if subjected to extended use over 110C
junction. For additional information, please contact your sales representative.

Table 10-1 Absolute Maximum Ratings

= V

SSA_ADC

Characteristic

Symbol

Notes

Min

Max

Unit

Supply voltage

DD_IO

- 0.3

4.0

ADC Supply Voltage

DDA_ADC,

REFH

must be

less than or equal

DDA_ADC

- 0.3

4.0

Oscillator / PLL Supply Voltage

DDA_OSC_PLL

- 0.3

4.0

Internal Logic Core Supply Voltage

DDA_CORE

OCR_DIS is High

- 0.3

3.0

Input Voltage (digital)

Pin Groups

1, 2, 5, 6, 9, 10, 14

-0.3

6.0

Input Voltage (analog)

INA

Pin Groups

11, 12, 13

-0.3

4.0

Output Voltage

OUT

Pin Groups

1, 2, 3, 4, 5, 6, 7, 8

-0.3

4.0

Output Voltage (open drain)

Pin Groups

4, 14

-0.3

6.0

Ambient Temperature (Automotive)

-40

125

°C

Ambient Temperature (Industrial)

-40

105

°C

Junction Temperature (Automotive)

-40

150

°C

Junction Temperature (Industrial)

-40

125

°C

Storage Temperature (Automotive)

STG

-55

150

°C

Storage Temperature (Industrial)

STG

-55

150

°C

Pin Group 1: TXD0-1, RXD0-1, SS0, MISO0, MOSI0
Pin Group 2: PHASEA0-1, PHASEB0-1, INDEX0-1,

HOME0-1, ISB0-2, RSTO, ISA0-2, TC0,
SCLK0

Pin Group 3: RSTO, TDO
Pin Group 4: CAN_TX
Pin Group 5: A0-5, D0-15, GPIOD0-1, PS, DS
Pin Group 6: A6-15, GPIOB0, TD0-1
Pin Group 7: CLKO, WR, RD

Pin Group 8: PWMA0-5, PWMB0-5

Pin Group 9: IRQA, IRQB, RESET, EXTBOOT, TRST,

TMS,

TDI,

CAN_RX,

EMI_MODE,

FAULTA0-3, FAULTB0-3

Pin Group 10: TCK
Pin Group 11: XTAL, EXTAL
Pin Group 12: ANA0-7, ANB0-7
Pin Group 13: OCR_DIS, CLKMODE

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General Characteristics

56F8346 Technical Data

125

Preliminary

Notes:

Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application.
Determined on 2s2p thermal test board.

Junction to ambient thermal resistance, Theta-JA (R

) was simulated to be equivalent to the JEDEC

specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was also simulated on a
thermal test board with two internal planes (2s2p, where "s" is the number of signal layers and "p" is the number
of planes) per JESD51-6 and JESD51-7. The correct name for Theta-JA for forced convection or with the
non-single layer boards is Theta-JMA.

Junction to case thermal resistance, Theta-JC (R

), was simulated to be equivalent to the measured values

using the cold plate technique with the cold plate temperature used as the "case" temperature. The basic cold
plate measurement technique is described by MIL-STD 883D, Method 1012.1. This is the correct thermal
metric to use to calculate thermal performance when the package is being used with a heat sink.

Thermal Characterization Parameter, Psi-JT (

), is the "resistance" from junction to reference point

thermocouple on top center of case as defined in JESD51-2.

is a useful value to use to estimate junction

temperature in steady-state customer environments.

Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and
board thermal resistance.

See

Section 12.1

for more details on thermal design considerations.

Table 10-2 Electrostatic Discharge Protection

Characteristic

Min

Typ

Max

Unit

ESD for Human Body Model (HBM)

2000

ESD for Machine Model (MM)

200

ESD for Charge Device Model (CDM)

500

Table 10-3 Thermal Characteristics

Characteristic

Comments

Symbol

Value

Unit

Notes

144-pin LQFP

Junction to ambient
Natural convection

47.1

°C/W

Junction to ambient (@1m/sec)

JMA

43.8

°C/W

Junction to ambient
Natural convection

Four layer board
(2s2p)

JMA

(2s2p)

40.8

°C/W

1,2

Junction to ambient (@1m/sec)

Four layer board
(2s2p)

JMA

39.2

°C/W

1,2

Junction to case

11.8

°C/W

Junction to center of case

°C/W

4, 5

I/O pin power dissipation

I/O

User-determined

Power dissipation

= (I

x V

+ P

I/O

)

Maximum allowed P

DMAX

(TJ - TA) /

°C

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126

56F8346 Technical Data

Preliminary

Note: Total chip source or sink current cannot exceed 200mA

See Pin Groups in

Table 10-1

Table 10-4 Recommended Operating Conditions

REFLO

= 0V, V

= V

SSA_ADC

= 0V

DDA

= V

DDA_ADC

= V

DDA_OSC_PLL

)

Characteristic

Symbol

Notes

Min

Typ

Max

Unit

Supply voltage

DD_IO

3.3

3.6

ADC Supply Voltage

DDA_ADC,

REFH

must be

less than or equal

to V

DDA_ADC

3.3

3.6

Oscillator / PLL Supply Voltage

DDA_OSC

_PLL

3.3

3.6

Internal Logic Core Supply
Voltage

DD_CORE

OCR_DIS is High

2.25

2.5

2.75

Device Clock Frequency

FSYSCLK

MHz

Input High Voltage (digital)

Pin Groups

1, 2, 5, 6, 9, 10

5.5

Input High Voltage (analog)

IHA

Pin Group 13

DDA

+0.3

Input High Voltage (XTAL/EXTAL,

XTAL is not driven by an external
clock)

IHC

Pin Group 11

DDA

-0.8

DDA

+0.3

Input high voltage (XTAL/EXTAL,

XTAL is driven by an external clock)

IHC

Pin Group 11

DDA

+0.3

Input Low Voltage

Pin Groups

1, 2, 5, 6, 9, 10,

11, 13

-0.3

0.8

Output High Source Current

= 2.4V (V

min.)

Pin Groups 1, 2, 3

-4

Pin Groups 5, 6, 7

-8

Pin Group 8

-12

Output Low Sink Current

= 0.4V (V

max)

Pin Groups

1, 2, 3, 4

Pin Groups 5, 6, 7

Pin Group 8

Ambient Operating Temperature
(Automotive)

-40

125 -

X P

)

°C

Ambient Operating Temperature
(Industrial)

-40

105 -

X P

)

°C

Flash Endurance (Automotive)
(Program Erase Cycles)

= -40°C

125°C

10,000

Cycles

Flash Endurance (Industrial)
(Program Erase Cycles)

= -40°C

105°C

10,000

Cycles

Flash Data Retention

<= 70°C

avg

Years

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DC Electrical Characteristics

56F8346 Technical Data

127

Preliminary

10.2 DC Electrical Characteristics

See Pin Groups in

Table 10-1

Table 10-5 DC Electrical Characteristics

Over Recommended Operating Conditions, V

DDA

= V

DDA_ADC,_

DDA_OSC_PLL

Characteristic

Symbol

Notes

Min

Typ

Max

Unit

Test

Conditions

Output High Voltage

2.4

OHmax

Output Low Voltage

0.4

OLmax

Digital Input Current High

pull-up enabled or disabled

Pin Groups
1, 2, 5, 6, 9

+/- 2.5

= 3.0V to 5.5V

Digital Input Current High

with pull-down

Pin Group 10

160

= 3.0V to 5.5V

Analog Input Current High

IHA

Pin Group 13

+/- 2.5

= V

DDA

ADC Input Current High

IHADC

Pin Group 12

+/- 3.5

= V

DDA

Digital Input Current Low

pull-up enabled

Pin Groups
1, 2, 5, 6, 9

-200

-100

-50

= 0V

Digital Input Current Low

pull-up disabled

Pin Groups
1, 2, 5, 6, 9

+/- 2.5

= 0V

Digital Input Current Low

with pull-down

Pin Group 10

+/- 2.5

= 0V

Analog Input Current Low

ILA

Pin Group 13

+/- 2.5

= 0V

ADC Input Current Low

ILADC

Pin Group 12

+/- 3.5

= 0V

EXTAL Input Current Low

clock input

EXTAL

+/- 2.5

= V

DDA

or 0V

XTAL Input Current Low

clock input

XTAL

CLKMODE =

High

+/- 2.5

= V

DDA

or 0V

CLKMODE =

Low

200

= V

DDA

or 0V

Output Current
High Impedance State

Pin Groups

1, 2, 3, 4, 5,

6, 7, 8

+/- 2.5

OUT

= 3.0V to

5.5V or 0V

Schmitt Trigger Input
Hysteresis

HYS

Pin Groups

2, 6, 9,10

0.3

Input Capacitance
(EXTAL/XTAL)

INC

4.5

Output Capacitance
(EXTAL/XTAL)

OUTC

5.5

Input Capacitance

Output Capacitance

OUT

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128

56F8346 Technical Data

Preliminary

Table 10-6 Power on Reset Low Voltage Parameters

Characteristic

Symbol

Min

Typ

Max

Units

POR Trip Point

POR

1.75

1.8

1.9

LVI, 2.5 volt Supply, trip point

When V

drops below V

EI2.5

, an interrupt is generated.

EI2.5

2.14

LVI, 3.3 volt supply, trip point

When V

drops below V

EI3.3

, an interrupt is generated.

EI3.3

2.7

Bias Current

bias

110

130

Table 10-7 Current Consumption per Power Supply Pin (Typical)

On-Chip Regulator Enabled (OCR_DIS = Low)

Mode

DD_IO

No Output Switching

DD_ADC

DD_OSC_PLL

Test Conditions

RUN1_MAC

155mA

50mA

2.5mA

· 60MHz Device Clock

· All peripheral clocks are enabled

· All peripherals running

· Continuous MAC instructions with fetches from

Data RAM

· ADC powered on and clocked

Wait3

91mA

2.5mA

· 60MHz Device Clock

· All peripheral clocks are enabled

· ADC powered off

Stop1

5.8mA

155

· 8MHz Device Clock

· All peripheral clocks are off

· ADC powered off

· PLL powered off

Stop2

5.1mA

145

· External Clock is off

· All peripheral clocks are off

· ADC powered off

· PLL powered off

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DC Electrical Characteristics

56F8346 Technical Data

129

Preliminary

Table 10-8 Current Consumption per Power Supply Pin (Typical)

On-Chip Regulator Disabled (OCR_DIS = High)

Mode

DD_Core

DD_IO

No Output Switching

DD_ADC

DD_OSC_PLL

Test Conditions

RUN1_MAC

150mA

50mA

2.5mA

· 60MHz Device Clock

· All peripheral clocks are enabled

· All peripherals running

· Continuous MAC instructions with

fetches from Data RAM

· ADC powered on and clocked

Wait3

86mA

2.5mA

· 60MHz Device Clock

· All peripheral clocks are enabled

· All peripherals running

· ADC powered off

Stop1

800

155

· 8MHz Device Clock

· All peripheral clocks are off

· ADC powered off

· PLL powered off

Stop2

100

145

· External Clock is off

· All peripheral clocks are off

· ADC powered off

· PLL powered off

Table 10-9. Regulator Parameters

Characteristic

Symbol

Min

Typical

Max

Unit

Unloaded Output Voltage
(0mA Load)

RNL

2.25

2.75

Loaded Output Voltage
(250mA load)

2.25

2.75

Line Regulation @ 250mA load
(V

33 ranges from 3.0V to 3.6V)

2.25

2.75

Short Circuit Current
(output shorted to ground)

Iss

700

Bias Current

bias

5.8

Power-down Current

Short-Circuit Tolerance
(output shorted to ground)

RSC

minutes

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130

56F8346 Technical Data

Preliminary

10.3 Temperature Sense

10.4 AC Electrical Characteristics

Tests are conducted using the input levels specified in

Table 10-5

. Unless otherwise specified,

propagation delays are measured from the 50% to the 50% point, and rise and fall times are
measured between the 10% and 90% points, as shown in

Figure 10-1

Figure 10-1 Input Signal Measurement References

Table 10-10. PLL Parameters

Characteristics

Symbol

Min

Typical

Max

Unit

PLL Start-up time

0.3

0.5

Resonator Start-up time

0.1

0.18

Min-Max Period Variation

120

200

Peak-to-Peak Jitter

175

Bias Current

BIAS

1.5

Quiescent Current, power-down mode

100

150

Table 10-11 Temperature Sense Parametrics

Characteristics

Symbol

Min

Typical

Max

Unit

K-factor

This is the inverse of the parameter "m" found in the Functional Description of the Temperature Sensor chapter of the

56F8300 Peripheral User Manual.

7.2

mV/°C

Supply Voltage

DDA

3.0

3.3

3.6

Supply Current - OFF

DD-OFF

Supply Current - ON

DD-ON

250

Accuracy

ACC

-2

°C

Resolution

°C / bit

Assuming a 10-bit range from 0V to 3.6V.

Fall Time

Input Signal

Note: The midpoint is V

+ (V

)/2.

Midpoint1

Low

High

90%

50%

10%

Rise Time

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Flash Memory Characteristics

56F8346 Technical Data

131

Preliminary

Figure 10-2

shows the definitions of the following signal states:

Active state, when a bus or signal is driven, and enters a low impedance state

Tri-stated, when a bus or signal is placed in a high impedance state

Data Valid state, when a signal level has reached V

or V

Data Invalid state, when a signal level is in transition between V

and V

Figure 10-2 Signal States

10.5 Flash Memory Characteristics

Table 10-12 Flash Timing Parameters

Characteristic

Symbol

Min

Typ

Max

Unit

Program time

There is additional overhead which is part of the programming sequence. See the 56F8300 Peripheral User Manual for

details. Program time is per 16-bit word in Flash memory. Two words at a time can be programmed within the Program Flash
module, as it contains two interleaved memories.

prog

Erase time

Specifies page erase time. There are 512 bytes per page in the Data and Boot Flash memories. The Program Flash mod-

ule uses two interleaved Flash memories, increasing the effective page size to 1024 bytes.

erase

Mass erase time

100

Data Invalid State

Data1

Data2 Valid

Data

Tri-stated

Data3 Valid

Data2

Data3

Data1 Valid

Data Active

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132

56F8346 Technical Data

Preliminary

10.6 External Clock Operation Timing

Figure 10-3 External Clock Timing

10.7 Phase Locked Loop Timing

Table 10-13 External Clock Operation Timing Requirements

Parameters listed are guaranteed by design.

Characteristic

Symbol

Min

Typ

Max

Unit

Frequency of operation (external clock driver)

See

Figure 10-3

for details on using the recommended connection of an external clock driver.

osc

120

MHz

Clock Pulse Width

The high or low pulse width must be no smaller than 8.0ns or the chip will not function.

3.0

External clock input rise time

External clock input rise time is measured from 10% to 90%.

rise

External clock input fall time

External clock input fall time is measured from 90% to 10%.

fall

Table 10-14 PLL Timing

Characteristic

Symbol

Min

Typ

Max

Unit

External reference crystal frequency for the PLL

An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work

correctly. The PLL is optimized for 8MHz input crystal.

osc

MHz

PLL output frequency

OUT

)

ZCLK may not exceed 60MHz. For additional information on ZCLK and (f

OUT

/2), please refer to the OCCS chapter in the

56F8300 Peripheral User Manual.

160

260

MHz

PLL stabilization time

-40

to +125

This is the minimum time required after the PLL set up is changed to ensure reliable operation.

plls

External

Clock

Note: The midpoint is V

+ (V

)/2.

90%

50%

10%

90%

50%

10%

fall

rise

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Crystal Oscillator Timing

56F8346 Technical Data

133

Preliminary

10.8 Crystal Oscillator Timing

10.9 External Memory Interface Timing

The External Memory Interface is designed to access static memory and peripheral devices.

Figure 10-4

shows sample timing and parameters that are detailed in

Table 10-16

The timing of each parameter consists of both a fixed delay portion and a clock related portion, as
well as user controlled wait states. The equation:

t = D + P * (M + W)

should be used to determine the actual time of each parameter. The terms in this equation are defined
as:

When using the XTAL clock input directly as the chip clock without prescaling (ZSRC selects
prescaler clock and prescaler set to

1),

the EMI quadrature clock is generated using both edges

of the EXTAL clock input. In this one situation parameter values need to be adjusted for the duty

Table 10-15 Crystal Oscillator Parameters

Characteristic

Symbol

Min

Typ

Max

Unit

Crystal Start-up time

Resonator Start-up time

0.1

0.18

Crystal ESR

ESR

120

ohms

Crystal Peak-to-Peak Jitter

250

Crystal Min-Max Period Variation

0.12

1.5

Resonator Peak-to-Peak Jitter

300

Resonator Min-Max Period Variation

300

Bias Current, high-drive mode

BIASH

250

290

Bias Current, low-drive mode

BIASL

110

Quiescent Current, power-down mode

= Parameter delay time

= Fixed portion of the delay, due to on-chip path delays

= Period of the system clock, which determines the execution rate of the part

(i.e., when the device is operating at 60MHz, P = 16.67 ns)

= Fixed portion of a clock period inherent in the design; this number is adjusted to account

for possible derating of clock duty cycle

= Sum of the applicable wait state controls. The "Wait State Controls" column of

Table 10-16

shows the applicable controls for each parameter and the EMI chapter of the

56F8300 Peripheral User Manual details what each wait state field controls.

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134

56F8346 Technical Data

Preliminary

cycle at XTAL. DCAOE and DCAEO are used to make this duty cycle adjustment where needed.
DCAOE and DCAEO are calculated as follows:

The timing of write cycles is different when WWS = 0 than when WWS > 0. Therefore, some
parameters contain two sets of numbers to account for this difference. Use the "Wait States
Configuration" column of

Table 10-16

to make the appropriate selection.

Figure 10-4 External Memory Interface Timing

Note:

When multiple lines are given for the same wait state configuration, calculate each and then
select the smallest or most negative.

DCAOE =

0.5 - MAX XTAL duty cycle, if ZSRC selects prescaler clock and the prescaler is set to

0.0 all other cases

DCAEO =

MIN XTAL duty cycle - 0.5, if ZSRC selects prescaler clock and the prescaler is set to

0.0 all other cases

Example of DCAOE and DCAEO calculation:

Assuming prescaler is set for

1 and prescaler clock is selected by ZSRC, if XTAL duty cycle

ranges between 45% and 60% high;

DCAOE = .50 - .60 = - 0.1
DCAEO = .45 - .50 = - 0.05

DRD

RDD

DOH

DOS

DWR

RDWR

WAC

WRRD

AWR

WRWR

ARDD

RDA

RDRD

ARDA

Data Out

Data In

A0-Axx,CS

D0-D15

Note: During read-modify-write instructions and internal instructions, the address lines do not change state.

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External Memory Interface Timing

56F8346 Technical Data

135

Preliminary

Table 10-16 External Memory Interface Timing

Operating Conditions: V

= V

SSIO

= V

SSA

= 0V, V

= 1.62-1.98V, V

DDIO

= V

DDA

3.03.6V, T

= 40

to +125

C, C

50pF

Characteristic

Symbol

Wait States

Configuration

Wait States

Controls

Unit

Address Valid to WR Asserted

AWR

WWS=0

-2.121

0.50

WWSS

WWS>0

-1.805

0.75 + DCAOE

WR Width Asserted to WR
Deasserted

WWS=0

-0.063

0.25 + DCAOE

WWS

WWS>0

-0.253

1.00

Data Out Valid to WR Asserted

DWR

WWS=0

-10.252

0.25 + DCAEO

WWSS

WWS=0

-2.868

0.00

WWS>0

-9.505

0.50

WWS>0

-2.552

0.25 + DCAOE

Valid Data Out Hold Time after WR
Deasserted

DOH

-1.512

0.25 + DCAEO

WWSH

Valid Data Out Set Up Time to WR
Deasserted

DOS

-2.047

0.25 + DCAOE

WWS,WWSS

-9.000

0.50

Valid Address after WR
Deasserted

WAC

-3.888

0.25 + DCAEO

WWSH

RD Deasserted to Address Invalid

RDA

-2.922

0.00

RWSH

Address Valid to RD Deasserted

ARDD

-1.645

1.00

RWSS,RWS

Valid Input Data Hold after RD
Deasserted

DRD

0.00

N/A

1.N/A, since device captures data before it deasserts RD

RD Assertion Width

0.257

1.00

RWS

Address Valid to Input Data Valid

-14.414

1.00

RWSS,RWS

-19.299

1.25 + DCAOE

Address Valid to RD Asserted

ARDA

-2.002

0.00

RWSS

RD Asserted to Input Data Valid

RDD

-12.411

1.00

RWSS,RWS

-17.297

1.25 + DCAOE

WR Deasserted to RD Asserted

WRRD

-1.323

0.25 + DCAEO WWSH,RWSS

RD Deasserted to RD Asserted

RDRD

-0.357

2.If RWSS = RWSH = 0, RD does not deassert during back-to-back reads and D = 0.00 should be used.

0.00

RWSS,RWSH

MDAR

3.Substitute BMDAR for MDAR if there is no chip select

WR Deasserted to WR Asserted

WRWR

WWS=0

-1.442

0.75 + DCAEO

WWSS,

WWSH

WWS>0

-0.695

1.00

RD Deasserted to WR Asserted

RDWR

WWS=0

-0.476

0.50

RWSH,

WWSS,

MDAR

WWS>0

-0.160

0.75 + DCAOE

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136

56F8346 Technical Data

Preliminary

10.10 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Figure 10-5 Asynchronous Reset Timing

Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing

1,2

In the formulas, T = clock cycle. For an operating frequency of 60MHz, T = 16.67ns. At 8MHz (used during Reset and

Stop modes), T = 125ns.

Parameters listed are guaranteed by design.

Characteristic

Symbol

Typical

Min

Typical

Max

Unit

See Figure

RESET Assertion to Address, Data and Control
Signals High Impedance

RAZ

10-5

Minimum RESET Assertion Duration

16T

10-5

RESET Deassertion to First External Address

Output

During Power-On Reset, it is possible to use the 56F8346 internal reset stretching circuitry to extend this period to 2

RDA

63T

64T

10-5

Edge-sensitive Interrupt Request Width

IRW

1.5T

10-6

IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction
execution in the interrupt service routine

IDM

10-7

IDM - FAST

IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine

10-7

IG - FAST

Delay from IRQA Assertion (exiting Wait) to

External Data Memory access

The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state.

This is not the minimum required so that the IRQA interrupt is accepted.

IRI

10-8

IRI - FAST

Delay from IRQA Assertion to External Data
Memory Access (exiting Stop)

10-9

IF - FAST

IRQA Width Assertion to Recover from Stop

State

The interrupt instruction fetch is visible on the pins only in Mode 3.

1.5T

10-9

First Fetch

RAZ

RDA

A0A15,

D0D15

RESET

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138

56F8346 Technical Data

Preliminary

10.11 Serial Peripheral Interface (SPI) Timing

Table 10-18 SPI Timing

Parameters listed are guaranteed by design.

Characteristic

Symbol

Min

Max

Unit

See Figure

Cycle time
Master
Slave

50
50

--
--

ns
ns

10-10

10-11

10-12

10-13

Enable lead time
Master
Slave

ELD

--
--

ns
ns

10-13

Enable lag time
Master
Slave

ELG

100

--
--

ns
ns

10-13

Clock (SCK) high time
Master
Slave

17.6

--
--

ns
ns

10-10

10-11

10-12

10-13

Clock (SCK) low time
Master
Slave

24.1

--
--

ns
ns

10-13

Data set-up time required for inputs
Master
Slave

--
--

ns
ns

10-10

10-11

10-12

10-13

Data hold time required for inputs
Master
Slave

0
2

--
--

ns
ns

10-10

10-11

10-12

10-13

Access time (time to data active from
high-impedance state)
Slave

4.8

10-13

Disable time (hold time to high-impedance state)
Slave

3.7

15.2

10-13

Data Valid for outputs
Master
Slave (after enable edge)

--
--

4.5

20.4

ns
ns

10-10

10-11

10-12

10-13

Data invalid
Master
Slave

0
0

--
--

ns
ns

10-10

10-11

10-12

Rise time
Master
Slave

--
--

11.5
10.0

ns
ns

10-10

10-11

10-12

10-13

Fall time
Master
Slave

--
--

9.7
9.0

ns
ns

10-10

10-11

10-12

10-13

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Quad Timer Timing

56F8346 Technical Data

141

Preliminary

10.12 Quad Timer Timing

Figure 10-14 Timer Timing

10.13 Quadrature Decoder Timing

Table 10-19 Timer Timing

1, 2

In the formulas listed, T = the clock cycle. For 60MHz operation, T = 16.67ns.

Parameters listed are guaranteed by design.

Characteristic

Symbol

Min

Max

Unit

See Figure

Timer input period

2T + 6

10-14

Timer input high / low period

INHL

1T + 3

10-14

Timer output period

OUT

1T - 3

10-14

Timer output high / low period

OUTHL

0.5T - 3

10-14

Table 10-20 Quadrature Decoder Timing

1, 2

In the formulas listed, T = the clock cycle. For 60MHz operation, T=16.67ns.

Parameters listed are guaranteed by design.

Characteristic

Symbol

Min

Max

Unit

See Figure

Quadrature input period

4T + 12

10-15

Quadrature input high / low period

2T + 6

10-15

Quadrature phase period

1T + 3

10-15

OUT

OUTHL

INHL

Timer Inputs

Timer Outputs

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142

56F8346 Technical Data

Preliminary

Figure 10-15 Quadrature Decoder Timing

10.14 Serial Communication Interface (SCI) Timing

Figure 10-16 RXD Pulse Width

Figure 10-17 TXD Pulse Width

Table 10-21 SCI Timing

Parameters listed are guaranteed by design.

Characteristic

Symbol

Min

Max

Unit

See Figure

Baud Rate

MAX

is the frequency of operation of the system clock, ZCLK, in MHz, which is 60MHz for the 56F8346 device.

MAX

/16)

Mbps

RXD

Pulse Width

The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.

RXD

0.965/BR

1.04/BR

10-16

TXD

Pulse Width

The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.

TXD

0.965/BR

1.04/BR

10-17

Phase B

(Input)

Phase A

(Input)

RXD

SCI receive

data pin

(Input)

TXD

SCI receive

data pin

(Input)

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Controller Area Network (CAN) Timing

56F8346 Technical Data

143

Preliminary

10.15 Controller Area Network (CAN) Timing

Figure 10-18 Bus Wake Up Detection

10.16 JTAG Timing

Table 10-22 CAN Timing

Parameters listed are guaranteed by design

Characteristic

Symbol

Min

Max

Unit

See Figure

Baud Rate

CAN

Mbps

Bus Wake Up detection

WAKEUP

10-18

Table 10-23 JTAG Timing

Characteristic

Symbol

Min

Max

Unit

See Figure

TCK frequency of operation

using EOnCE

TCK frequency of operation must be less than 1/8 the processor rate.

SYS_CLK/8

MHz

10-19

TCK frequency of operation not

using EOnCE

SYS_CLK/4

MHz

10-19

TCK clock pulse width

10-19

TMS, TDI data set-up time

10-20

TMS, TDI data hold time

10-20

TCK low to TDO data valid

10-20

TCK low to TDO tri-state

10-20

TRST assertion time

TRST

T = processor clock period (nominally 1/60MHz)

10-21

WAKEUP

CAN_RX

CAN receive

data pin

(Input)

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Analog-to-Digital Converter (ADC) Parameters

56F8346 Technical Data

145

Preliminary

10.17 Analog-to-Digital Converter (ADC) Parameters

Table 10-24 ADC Parameters

Characteristic

Symbol

Min

Typ

Max

Unit

Input voltages

ADIN

REFL

REFH

Resolution

Bits

Integral Non-Linearity

INL

+/- 1

+/- 2.4

+/- 3.2

LSB

Differential Non-Linearity

DNL

> -1

+/- 0.7

< +1

LSB

Monotonicity

GUARANTEED

ADC internal clock

ADIC

0.5

MHz

Conversion range

REFL

REFH

ADC channel power-up time

ADPU

AIC

cycles

ADC reference circuit power-up time

VREF

Conversion time

ADC

AIC

cycles

Sample time

ADS

AIC

cycles

Input capacitance

ADI

Input injection current

, per pin

ADI

Input injection current, total

ADIT

REFH

current

VREFH

1.2

ADC A current

ADCA

ADC B current

ADCB

Quiescent current

ADCQ

Uncalibrated Gain Error

GAIN

.99

.996 to 1.004

1.01

Uncalibrated Offset Voltage

OFFSET

+/- 18

+/- 30

Calibrated Absolute Error

CAL

See

Figure 10-22

LSBs

Calibration Factor 1

CF1

-0.003141

Calibration Factor 2

CF2

-17.6

Crosstalk between channels

-60

Common Mode Voltage

common

REFH

- V

REFLO

) / 2

Signal-to-noise ratio

SNR

64.6

Signal-to-noise plus distortion ratio

SINAD

59.1

Total Harmonic Distortion

THD

60.6

Spurious Free Dynamic Range

SFDR

61.1

Effective Number Of Bits

ENOB

9.6

Bits

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146

56F8346 Technical Data

Preliminary

Figure 10-22 ADC Absolute Error Over Processing and Temperature Extremes

Before and After Calibration for VDC

= 0.60V and 2.70V

Note: The absolute error data shown in the graphs above reflects the effects of both gain error and
offset error. The data was taken on 15 parts: three each from four processing corner lots as well as
three from one nominally processed lot, each at three temperatures: -40°C, 27°C, and 150°C (giving
the 45 data points shown above), for two input DC voltages: 0.60V and 2.70V. The data indicates

INL measured from V

= .1V

REFH

to V

= .9V

REFH

10% to 90% Input Signal Range

LSB = Least Significant Bit

ADC clock cycles

Assumes each voltage reference pin is bypassed with 0.1

F ceramic capacitors to ground

The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of
the ADC. This allows the ADC to operate in noisy industrial environments where inductive flyback is possible.

Absolute error includes the effects of both gain error and offset error.

Please see the 56F8300 Peripheral User's Manual for additional information on ADC calibration.

ENOB = (SINAD - 1.76)/6.02

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Equivalent Circuit for ADC Inputs

56F8346 Technical Data

147

Preliminary

that for the given population of parts, calibration significantly reduced (by as much as 39%) the
collective variation (spread) of the absolute error of the population. It also significantly reduced
(by as much as 80%) the mean (average) of the absolute error and thereby brought it significantly
closer to the ideal value of zero. Although not guaranteed, it is believed that calibration will
produce results similar to those shown above for any population of parts including those which
represent processing and temperature extremes.

10.18 Equivalent Circuit for ADC Inputs

Figure 10-23

illustrates the ADC input circuit during sample and hold. S1 and S2 are always

open/closed at the same time that S3 is closed/open. When S1/S2 are closed & S3 is open, one input
of the sample and hold circuit moves to V

REFH

- V

REFH

/ 2, while the other charges to the analog

input voltage. When the switches are flipped, the charge on C1 and C2 are averaged via S3, with
the result that a single-ended analog input is switched to a differential voltage centered about
V

REFH

- V

REFH

/ 2. The switches switch on every cycle of the ADC clock (open one-half ADC

clock, closed one-half ADC clock). Note that there are additional capacitances associated with the
analog input pad, routing, etc., but these do not filter into the S/H output voltage, as S1 provides
isolation during the charge-sharing phase.

One aspect of this circuit is that there is an on-going input current, which is a function of the analog
input voltage, V

REF

and the ADC clock frequency.

Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pf

Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pf

Equivalent resistance for the ESD isolation resistor and the channel select mux; 500 ohms

Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is
only connected to it at sampling time; 1pf

Figure 10-23 Equivalent Circuit for A/D Loading

10.19 Power Consumption

This section provides additional detail which can be used to optimize power consumption for a
given application.

Power consumption is given by the following equation:

Total power =

A: internal [static component]

+ B: internal [state-dependent component]
+ C: internal [dynamic component]
+ D: external [dynamic component]
+ E: external [static]

Analog Input

S/H

C1 = C2 = 1pF

REFH

- V

REFLO

) / 2

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148

56F8346 Technical Data

Preliminary

A, the internal [static component], is comprised of the DC bias currents for the oscillator, leakage
current, PLL, and voltage references. These sources operate independently of processor state or
operating frequency.

B, the internal [state-dependent component], reflects the supply current required by certain on-chip
resources only when those resources are in use. These include RAM, Flash memory and the ADCs.

C, the internal [dynamic component], is classic C*V

*F CMOS power dissipation corresponding

to the 56800E core and standard cell logic.

D, the external [dynamic component], reflects power dissipated on-chip as a result of capacitive
loading on the external pins of the chip. This is also commonly described as C*V

*F, although

simulations on two of the IO cell types used on the 56F8346 reveal that the power-versus-load
curve does have a non-zero Y-intercept.

Power due to capacitive loading on output pins is (first order) a function of the capacitive load and
frequency at which the outputs change.

Table 10-25

provides coefficients for calculating power

dissipated in the IO cells as a function of capacitive load. In these cases:

TotalPower =

((Intercept +Slope*Cload)*frequency/10MHz)

where:

Summation is performed over all output pins with capacitive loads

TotalPower is expressed in mW

Cload is expressed in pF

Because of the low duty cycle on most device pins, power dissipation due to capacitive loads was
found to be fairly low when averaged over a period of time. The one possible exception to this is
if the chip is using the external address and data buses at a rate approaching the maximum system
rate. In this case, power from these buses can be significant.

E, the external [static component], reflects the effects of placing resistive loads on the outputs of
the device. Sum the total of all V

/R or IV to arrive at the resistive load contribution to power.

Assume V = 0.5 for the purposes of these rough calculations. For instance, if there is a total of 8
PWM outputs driving 10mA into LEDs, then P = 8*.5*.01 = 40mW.

In previous discussions, power consumption due to parasitics associated with pure input pins is
ignored, as it is assumed to be negligible.

Table 10-25 IO Loading Coefficients at 10MHz

Intercept

Slope

PDU08DGZ_ME

1.3

0.11mW / pF

PDU04DGZ_ME

1.15mW

0.11mW / pF

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Package and Pin-Out Information 56F8346

56F8346 Technical Data

149

Preliminary

Part 11 Packaging

11.1 Package and Pin-Out Information 56F8346

This section contains package and pin-out information for the 56F8346. This device comes in a
144-pin Low-profile Quad Flat Pack (LQFP).

Figure 11-1

shows the package outline for the

LQFP;

Figure 11-2

shows the mechanical parameters for this package, and

Table 11-1

lists the

pin-out for the 144-pin LQFP.

Figure 11-1 Top View, 56F8346 144-Pin LQFP Package

DD_IO

CLKO

TXD0

RXD0

PHASEA1
PHASEB1

INDEX1
HOME1

A1
A2
A3
A4
A5

CAP

DD_IO

A6
A7
A8
A9

A10

A11

A12
A13
A14
A15
V

D7
D8
D9

DD_IO

D10

GPIOB0

PWMB0
PWMB1
PWMB2

DD_

I
O

PWM

I
SB0

I
SB1

I
SB2

IRQA

IRQB

PWM

I
O

PWM

FAULTA1

FAULTA2

OCR_DIS

DDA_OSC_PLL

XTAL

EXTAL

CAP

DD_IO

RSTO

RESET

CLKMODE

ANA0

ANA1

ANA2

ANA3

ANA4

ANA5

ANA6

ANA7

Temp_Sense

REFLO

REFN

REFMID

REFP

REFH

DDA_ADC

SSA_ADC

ANB0

ANB1

ANB2

ANB3

ANB4

ANB5

ANB6

ANB7

EXTBO

I
SA0

I
SA1

I
O

TMS

CAN_

SS0

SCL

I
0

PHASEA0

PHASEB0

I
NDEX0

HOM

I
_

Motorola

56F8346

Pin 1

Orientation Mark

109

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150

56F8346 Technical Data

Preliminary

Table 11-1 56F8346 144-Pin LQFP Package Identification by Pin Number

Pin No.

Signal

Name

Pin No.

Signal Name

Pin No.

Signal Name

Pin No.

Signal Name

DD_IO

FAULTA1

109

ANB5

DD_IO

FAULTA2

110

ANB6

CLKO

PWMB3

111

ANB7

TXD0

PWMB4

112

EXTBOOT

RXD0

PWMB5

113

ISA0

PHASEA1

TXD1

114

ISA1

PHASEB1

RXD1

OCR_DIS

115

ISA2

INDEX1

DDA_OSC_PLL

116

TD0

HOME1

XTAL

117

TD1

EXTAL

118

TC0

CAP

119

DD_IO

GPIOD0

DD_IO

120

TRST

GPIOD1

RSTO

121

TCK

ISB0

RESET

122

TMS

CAP

CLKMODE

123

TDI

DD_IO

ISB1

ANA0

124

TDO

ISB2

ANA1

125

IRQA

ANA2

126

CAN_TX

IRQB

ANA3

127

CAN_RX

FAULTB0

ANA4

128

CAP

A10

FAULTB1

ANA5

129

SS0

A11

FAULTB2

ANA6

130

SCLK0

A12

ANA7

131

MISO0

A13

TEMP_SENSE

132

MOSI0

A14

FAULTB3

REFLO

133

D11

A15

PWMA0

REFN

134

D12

REFMID

135

D13

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152

56F8346 Technical Data

Preliminary

Figure 11-2 56F8346 144-pin LQFP Mechanical Information

0.20 H B-C

144

GAGE PLANE

109

SEATING

108

PLANE

4X 36 TIPS

PIN 1
INDEX

VIEW A

E1/2

E/2

D1/2

D/2

e/2

0.1

VIEW B

140X

VIEW A

PLATING

BASE
METAL

SECTION A-A

(ROTATED 90 )

144 PLACES

0.08

A B-C

DIM

MIN

MAX

20.00 BSC

MILLIMETERS

20.00 BSC

---

1.60

0.05

0.15

1.35

1.45

0.17

0.27

0.45

0.75

0.17

0.23

0.50 BSC

0.09

0.20

0.50 REF

0.13

0.20

0.13

---

22.00 BSC

0.25 REF

1.00 REF

0.09

0.16

---

1
2

NOTES:
1.

ALL DIMENSIONS ARE IN MILLIMETERS.

INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.

DATUMS B, C AND D TO BE DETERMINED AT DATUM
H.

THE TOP PACKAGE BODY SIZE MAY BE SMALLER
THAN THE BOTTOM PACKAGE SIZE BY A MAXIMUM
OF 0.1 mm.

DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSIONS. THE MAXIMUM ALLOWABLE
PROTRUSION IS 0.25 mm PER SIDE. D1 AND E1 ARE
MAXIMUM BODY SIZE DIMENSIONS INCLUDING MOLD
MISMATCH.

DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. PROTRUSIONS SHALL NOT CAUSE
THE LEAD WIDTH TO EXCEED 0.35. MINIMUM SPACE
BETWEEN PROTRUSION AND AN ADJACENT LEAD
SHALL BE 0.07 mm.

DIMENSIONS D AND E TO BE DETERMINED AT THE
SEATING PLANE, DATUM A.

CASE 918-03

ISSUE D

DATE 08/22/00

0.05

0.25

VIEW B

0.20 A B-C

144X

X=B, C or D

12 REF

TOP VIEW

SIDE VIEW

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Thermal Design Considerations

56F8346 Technical Data

153

Preliminary

Part 12 Design Considerations

12.1 Thermal Design Considerations

An estimation of the chip junction temperature, T

, can be obtained from the equation:

= T

+ (R

)

where:

The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and
easy estimation of thermal performance. Unfortunately, there are two values in common usage: the
value determined on a single-layer board and the value obtained on a board with two planes. For
packages such as the PBGA, these values can be different by a factor of two. Which value is closer
to the application depends on the power dissipated by other components on the board. The value
obtained on a single-layer board is appropriate for the tightly packed printed circuit board. The
value obtained on the board with the internal planes is usually appropriate if the board has
low-power dissipation and the components are well separated.

When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case
thermal resistance and a case-to-ambient thermal resistance:

where:

is device-related and cannot be influenced by the user. The user controls the thermal

environment to change the case-to-ambient thermal resistance, R

. For instance, the user can

change the size of the heat sink, the air flow around the device, the interface material, the mounting
arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board
surrounding the device.

To determine the junction temperature of the device in the application when heat sinks are not used,
the Thermal Characterization Parameter (

) can be used to determine the junction temperature

with a measurement of the temperature at the top center of the package case using the following
equation:

= T

+ (

x P

)

where:

= Ambient temperature for the package (

= Junction-to-ambient thermal resistance (

C/W)

= Power dissipation in the package (W)

= Package junction-to-ambient thermal resistance °C/W

= Package junction-to-case thermal resistance °C/W

= Package case-to-ambient thermal resistance °C/W

Thermocouple temperature on top of package (

Thermal characterization parameter (

C)/W

Power dissipation in package (W)

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154

56F8346 Technical Data

Preliminary

The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge
type T thermocouple epoxied to the top center of the package case. The thermocouple should be
positioned so that the thermocouple junction rests on the package. A small amount of epoxy is
placed over the thermocouple junction and over about 1mm of wire extending from the junction.
The thermocouple wire is placed flat against the package case to avoid measurement errors caused
by cooling effects of the thermocouple wire.

When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is
normally required in the heat sink. Minimizing the size of the clearance is important to minimize
the change in thermal performance caused by removing part of the thermal interface to the heat
sink. Because of the experimental difficulties with this technique, many engineers measure the heat
sink temperature and then back-calculate the case temperature using a separate measurement of the
thermal resistance of the interface. From this case temperature, the junction temperature is
determined from the junction-to-case thermal resistance.

12.2 Electrical Design Considerations

Use the following list of considerations to assure correct device operation:

Provide a low-impedance path from the board power supply to each V

pin on the device, and

from the board ground to each V

(GND) pin

The minimum bypass requirement is to place six 0.010.1

F capacitors positioned as close as

possible to the package supply pins. The recommended bypass configuration is to place one bypass
capacitor on each of the V

pairs, including V

DDA

SSA.

Ceramic and tantalum capacitors

tend to provide better performance tolerances.

Ensure that capacitor leads and associated printed circuit traces that connect to the chip V

and

(GND)

pins are less than 0.5 inch per capacitor lead

Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for V

and V

Bypass the V

and V

layers of the PCB with approximately 100

F, preferably with a

high-grade capacitor such as a tantalum capacitor

Because the 56F8346's output signals have fast rise and fall times, PCB trace lengths should be
minimal

CAUTION

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Freescale Semiconductor, Inc.

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Power Distribution and I/O Ring Implementation

56F8346 Technical Data

155

Preliminary

Consider all device loads as well as parasitic capacitance due to PCB traces when calculating
capacitance. This is especially critical in systems with higher capacitive loads that could create
higher transient currents in the V

and V

circuits.

Take special care to minimize noise levels on the V

REF

, V

DDA

and V

SSA

pins

Designs that utilize the TRST pin for JTAG port or EOnCE module functionality (such as
development or debugging systems) should allow a means to assert TRST whenever RESET is
asserted, as well as a means to assert TRST independently of RESET. Designs that do not require
debugging functionality, such as consumer products, should tie these pins together.

Because the Flash memory is programmed through the JTAG/EOnCE port, the designer should
provide an interface to this port to allow in-circuit Flash programming

12.3 Power Distribution and I/O Ring Implementation

Figure 12-1

illustrates the general power control incorporated in the 56F8346. This chip contains

an internal regulator which cannot be disabled. The regulator takes regulated 3.3V power from the
V

DD_IO

pins and provides 2.5V to the internal logic of the chip. This means the entire part is

powered from the 3.3V supply.

Notes:

Flash, RAM and internal logic are powered from the core regulator output

1 and V

2 are not connected in the customer system

All circuitry, analog and digital, shares a common V

bus

Figure 12-1 56F8346 Power Management

REG

CORE

CAP

I/O

ADC

OCS

REG

DDA_OSC_PLL

ROSC

SSA_ADC

DDA_ADC

REFH

REFP

REFMID

REFN

REFLO

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HOW TO REACH US:

USA/EUROPE/LOCATIONS NOT LISTED:
Motorola Literature Distribution
P.O. Box 5405, Denver, Colorado 80217
1-800-521-6274 or 480-768-2130

JAPAN:
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SPS, Technical Information Center
3-20-1, Minami-Azabu
Minato-ku
Tokyo 106-8573, Japan
81-3-3440-3569

ASIA/PACIFIC:
Motorola Semiconductors H.K. Ltd.
Silicon Harbour Centre
2 Dai King Street
Tai Po Industrial Estate
Tai Po, N.T. Hong Kong
852-26668334

HOME PAGE:
http://motorola.com/semiconductors

Information in this document is provided solely to enable system and software

implementers to use Motorola products. There are no express or implied copyright licenses

granted hereunder to design or fabricate any integrated circuits or integrated circuits based

on the information in this document.

Motorola reserves the right to make changes without further notice to any products herein.

Motorola makes no warranty, representation or guarantee regarding the suitability of its

products for any particular purpose, nor does Motorola assume any liability arising out of

the application or use of any product or circuit, and specifically disclaims any and all

liability, including without limitation consequential or incidental damages. "Typical"

parameters which may be provided in Motorola data sheets and/or specifications can and

do vary in different applications and actual performance may vary over time. All operating

parameters, including "Typicals" must be validated for each customer application by

customer's technical experts. Motorola does not convey any license under its patent rights

nor the rights of others. Motorola products are not designed, intended, or authorized for use

as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the

Motorola product could create a situation where personal injury or death may occur. Should

Buyer purchase or use Motorola products for any such unintended or unauthorized

application, Buyer shall indemnify and hold Motorola and its officers, employees,

subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of

personal injury or death associated with such unintended or unauthorized use, even if such

claim alleges that Motorola was negligent regarding the design or manufacture of the part.

Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office.
digital dna is a trademark of Motorola, Inc. This product incorporates SuperFlash®
technology licensed from SST. All other product or service names are the property of their
respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

MC56F8346/D

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